1 2018-11-12 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
4 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
5 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
6 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
7 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
8 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
9 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
10 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
11 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
12 * aarch64-asm-2.c: Regenerated.
13 * aarch64-dis-2.c: Regenerated.
14 * aarch64-opc-2.c: Regenerated.
16 2018-11-12 Sudakshina Das <sudi.das@arm.com>
18 * aarch64-tbl.h (QL_LDG): New.
19 (aarch64_opcode_table): Add ldg.
20 * aarch64-asm-2.c: Regenerated.
21 * aarch64-dis-2.c: Regenerated.
22 * aarch64-opc-2.c: Regenerated.
24 2018-11-12 Sudakshina Das <sudi.das@arm.com>
26 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
27 for AARCH64_OPND_QLF_imm_tag.
28 (operand_general_constraint_met_p): Add case for
29 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
30 (aarch64_print_operand): Likewise.
31 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
32 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
33 for both offset and pre/post indexed versions.
34 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
35 * aarch64-asm-2.c: Regenerated.
36 * aarch64-dis-2.c: Regenerated.
37 * aarch64-opc-2.c: Regenerated.
39 2018-11-12 Sudakshina Das <sudi.das@arm.com>
41 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
42 * aarch64-asm-2.c: Regenerated.
43 * aarch64-dis-2.c: Regenerated.
44 * aarch64-opc-2.c: Regenerated.
46 2018-11-12 Sudakshina Das <sudi.das@arm.com>
48 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
49 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
50 * aarch64-opc.c (fields): Add entry for imm4_3.
51 (operand_general_constraint_met_p): Add cases for
52 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
53 (aarch64_print_operand): Likewise.
54 * aarch64-tbl.h (QL_ADDG): New.
55 (aarch64_opcode_table): Add addg, subg, irg and gmi.
56 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
57 * aarch64-asm.c (aarch64_ins_imm): Add case for
58 operand_need_shift_by_four.
59 * aarch64-asm-2.c: Regenerated.
60 * aarch64-dis-2.c: Regenerated.
61 * aarch64-opc-2.c: Regenerated.
63 2018-11-12 Sudakshina Das <sudi.das@arm.com>
65 * aarch64-tbl.h (aarch64_feature_memtag): New.
66 (MEMTAG, MEMTAG_INSN): New.
68 2018-11-06 Sudakshina Das <sudi.das@arm.com>
70 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
71 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
73 2018-11-06 Alan Modra <amodra@gmail.com>
75 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
76 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
77 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
78 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
79 Don't return zero on error, insert mask bits instead.
80 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
81 (insert_sh6, extract_sh6): Delete dead code.
82 (insert_sprbat, insert_sprg): Use unsigned comparisions.
83 (powerpc_operands <OIMM>): Set shift count rather than using
85 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
87 2018-11-06 Jan Beulich <jbeulich@suse.com>
89 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
90 vpbroadcast{d,q} with GPR operand.
92 2018-11-06 Jan Beulich <jbeulich@suse.com>
94 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
95 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
96 cases up one level in the hierarchy.
98 2018-11-06 Jan Beulich <jbeulich@suse.com>
100 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
101 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
102 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
103 into MOD_VEX_0F93_P_3_LEN_0.
104 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
105 operand cases up one level in the hierarchy.
107 2018-11-06 Jan Beulich <jbeulich@suse.com>
109 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
110 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
111 EVEX_W_0F3A22_P_2): Delete.
112 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
113 entries up one level in the hierarchy.
114 (OP_E_memory): Handle dq_mode when determining Disp8 shift
116 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
117 entries up one level in the hierarchy.
118 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
119 VexWIG for AVX flavors.
120 * i386-tbl.h: Re-generate.
122 2018-11-06 Jan Beulich <jbeulich@suse.com>
124 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
125 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
126 vcvtusi2ss, kmovd): Drop VexW=1.
127 * i386-tbl.h: Re-generate.
129 2018-11-06 Jan Beulich <jbeulich@suse.com>
131 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
132 EVex512, EVexLIG, EVexDYN): New.
133 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
134 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
135 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
136 of EVex=4 (aka EVexLIG).
137 * i386-tbl.h: Re-generate.
139 2018-11-06 Jan Beulich <jbeulich@suse.com>
141 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
142 (vpmaxub): Re-order attributes on AVX512BW flavor.
143 * i386-tbl.h: Re-generate.
145 2018-11-06 Jan Beulich <jbeulich@suse.com>
147 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
148 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
149 Vex=1 on AVX / AVX2 flavors.
150 (vpmaxub): Re-order attributes on AVX512BW flavor.
151 * i386-tbl.h: Re-generate.
153 2018-11-06 Jan Beulich <jbeulich@suse.com>
155 * i386-opc.tbl (VexW0, VexW1): New.
156 (vphadd*, vphsub*): Use VexW0 on XOP variants.
157 * i386-tbl.h: Re-generate.
159 2018-10-22 John Darrington <john@darrington.wattle.id.au>
161 * s12z-dis.c (decode_possible_symbol): Add fallback case.
162 (rel_15_7): Likewise.
164 2018-10-19 Tamar Christina <tamar.christina@arm.com>
166 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
167 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
168 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
170 2018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
172 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
173 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
175 2018-10-10 Jan Beulich <jbeulich@suse.com>
177 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
179 * i386-opc.h (Size16, Size32, Size64): Delete.
181 (SIZE16, SIZE32, SIZE64): Define.
182 (struct i386_opcode_modifier): Drop size16, size32, and size64.
184 * i386-opc.tbl (Size16, Size32, Size64): Define.
185 * i386-tbl.h: Re-generate.
187 2018-10-09 Sudakshina Das <sudi.das@arm.com>
189 * aarch64-opc.c (operand_general_constraint_met_p): Add
190 SSBS in the check for one-bit immediate.
191 (aarch64_sys_regs): New entry for SSBS.
192 (aarch64_sys_reg_supported_p): New check for above.
193 (aarch64_pstatefields): New entry for SSBS.
194 (aarch64_pstatefield_supported_p): New check for above.
196 2018-10-09 Sudakshina Das <sudi.das@arm.com>
198 * aarch64-opc.c (aarch64_sys_regs): New entries for
199 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
200 (aarch64_sys_reg_supported_p): New checks for above.
202 2018-10-09 Sudakshina Das <sudi.das@arm.com>
204 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
205 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
206 with the hint immediate.
207 * aarch64-opc.c (aarch64_hint_options): New entries for
208 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
209 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
210 while checking for HINT_OPD_F_NOPRINT flag.
211 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
213 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
214 (aarch64_opcode_table): Add entry for BTI.
215 (AARCH64_OPERANDS): Add new description for BTI targets.
216 * aarch64-asm-2.c: Regenerate.
217 * aarch64-dis-2.c: Regenerate.
218 * aarch64-opc-2.c: Regenerate.
220 2018-10-09 Sudakshina Das <sudi.das@arm.com>
222 * aarch64-opc.c (aarch64_sys_regs): New entries for
224 (aarch64_sys_reg_supported_p): New check for above.
226 2018-10-09 Sudakshina Das <sudi.das@arm.com>
228 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
229 (aarch64_sys_ins_reg_supported_p): New check for above.
231 2018-10-09 Sudakshina Das <sudi.das@arm.com>
233 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
234 AARCH64_OPND_SYSREG_SR.
235 * aarch64-opc.c (aarch64_print_operand): Likewise.
236 (aarch64_sys_regs_sr): Define table.
237 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
238 AARCH64_FEATURE_PREDRES.
239 * aarch64-tbl.h (aarch64_feature_predres): New.
240 (PREDRES, PREDRES_INSN): New.
241 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
242 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
243 * aarch64-asm-2.c: Regenerate.
244 * aarch64-dis-2.c: Regenerate.
245 * aarch64-opc-2.c: Regenerate.
247 2018-10-09 Sudakshina Das <sudi.das@arm.com>
249 * aarch64-tbl.h (aarch64_feature_sb): New.
251 (aarch64_opcode_table): Add entry for sb.
252 * aarch64-asm-2.c: Regenerate.
253 * aarch64-dis-2.c: Regenerate.
254 * aarch64-opc-2.c: Regenerate.
256 2018-10-09 Sudakshina Das <sudi.das@arm.com>
258 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
259 (aarch64_feature_frintts): New.
260 (FLAGMANIP, FRINTTS): New.
261 (aarch64_opcode_table): Add entries for xaflag, axflag
262 and frint[32,64][x,z] instructions.
263 * aarch64-asm-2.c: Regenerate.
264 * aarch64-dis-2.c: Regenerate.
265 * aarch64-opc-2.c: Regenerate.
267 2018-10-09 Sudakshina Das <sudi.das@arm.com>
269 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
270 (ARMV8_5, V8_5_INSN): New.
272 2018-10-08 Tamar Christina <tamar.christina@arm.com>
274 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
276 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
278 * i386-dis.c (rm_table): Add enclv.
279 * i386-opc.tbl: Add enclv.
280 * i386-tbl.h: Regenerated.
282 2018-10-05 Sudakshina Das <sudi.das@arm.com>
284 * arm-dis.c (arm_opcodes): Add sb.
285 (thumb32_opcodes): Likewise.
287 2018-10-05 Richard Henderson <rth@twiddle.net>
288 Stafford Horne <shorne@gmail.com>
290 * or1k-desc.c: Regenerate.
291 * or1k-desc.h: Regenerate.
292 * or1k-opc.c: Regenerate.
293 * or1k-opc.h: Regenerate.
294 * or1k-opinst.c: Regenerate.
296 2018-10-05 Richard Henderson <rth@twiddle.net>
298 * or1k-asm.c: Regenerated.
299 * or1k-desc.c: Regenerated.
300 * or1k-desc.h: Regenerated.
301 * or1k-dis.c: Regenerated.
302 * or1k-ibld.c: Regenerated.
303 * or1k-opc.c: Regenerated.
304 * or1k-opc.h: Regenerated.
305 * or1k-opinst.c: Regenerated.
307 2018-10-05 Richard Henderson <rth@twiddle.net>
309 * or1k-asm.c: Regenerate.
311 2018-10-03 Tamar Christina <tamar.christina@arm.com>
313 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
314 * aarch64-dis.c (print_operands): Refactor to take notes.
315 (print_verifier_notes): New.
316 (print_aarch64_insn): Apply constraint verifier.
317 (print_insn_aarch64_word): Update call to print_aarch64_insn.
318 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
320 2018-10-03 Tamar Christina <tamar.christina@arm.com>
322 * aarch64-opc.c (init_insn_block): New.
323 (verify_constraints, aarch64_is_destructive_by_operands): New.
324 * aarch64-opc.h (verify_constraints): New.
326 2018-10-03 Tamar Christina <tamar.christina@arm.com>
328 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
329 * aarch64-opc.c (verify_ldpsw): Update arguments.
331 2018-10-03 Tamar Christina <tamar.christina@arm.com>
333 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
334 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
336 2018-10-03 Tamar Christina <tamar.christina@arm.com>
338 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
339 * aarch64-dis.c (insn_sequence): New.
341 2018-10-03 Tamar Christina <tamar.christina@arm.com>
343 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
344 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
345 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
346 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
349 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
351 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
353 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
354 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
355 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
356 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
357 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
358 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
359 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
361 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
363 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
365 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
367 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
368 are used when extracting signed fields and converting them to
369 potentially 64-bit types.
371 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
373 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
374 * Makefile.in: Re-generate.
375 * aclocal.m4: Re-generate.
376 * configure: Re-generate.
377 * configure.ac: Remove check for -Wno-missing-field-initializers.
378 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
379 (csky_v2_opcodes): Likewise.
381 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
383 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
385 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
387 * nds32-asm.c (operand_fields): Remove the unused fields.
388 (nds32_opcodes): Remove the unused instructions.
389 * nds32-dis.c (nds32_ex9_info): Removed.
390 (nds32_parse_opcode): Updated.
391 (print_insn_nds32): Likewise.
392 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
393 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
394 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
395 build_opcode_hash_table): New functions.
396 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
397 nds32_opcode_table): New.
398 (hw_ktabs): Declare it to a pointer rather than an array.
399 (build_hash_table): Removed.
400 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
401 SYN_ROPT and upadte HW_GPR and HW_INT.
402 * nds32-dis.c (keywords): Remove const.
403 (match_field): New function.
404 (nds32_parse_opcode): Updated.
405 * disassemble.c (disassemble_init_for_target):
406 Add disassemble_init_nds32.
407 * nds32-dis.c (eum map_type): New.
408 (nds32_private_data): Likewise.
409 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
410 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
411 (print_insn_nds32): Updated.
412 * nds32-asm.c (parse_aext_reg): Add new parameter.
413 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
416 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
417 (operand_fields): Add new fields.
418 (nds32_opcodes): Add new instructions.
419 (keyword_aridxi_mx): New keyword.
420 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
422 (ALU2_1, ALU2_2, ALU2_3): New macros.
423 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
425 2018-09-17 Kito Cheng <kito@andestech.com>
427 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
429 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
432 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
433 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
434 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
435 (EVEX_LEN_0F7E_P_1): Likewise.
436 (EVEX_LEN_0F7E_P_2): Likewise.
437 (EVEX_LEN_0FD6_P_2): Likewise.
438 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
439 (EVEX_LEN_TABLE): Likewise.
440 (EVEX_LEN_0F6E_P_2): New enum.
441 (EVEX_LEN_0F7E_P_1): Likewise.
442 (EVEX_LEN_0F7E_P_2): Likewise.
443 (EVEX_LEN_0FD6_P_2): Likewise.
444 (evex_len_table): New.
445 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
446 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
447 * i386-tbl.h: Regenerated.
449 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
452 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
453 VEX_LEN_0F7E_P_2 entries.
454 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
455 * i386-tbl.h: Regenerated.
457 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
459 * i386-dis.c (VZERO_Fixup): Removed.
461 (VEX_LEN_0F10_P_1): Likewise.
462 (VEX_LEN_0F10_P_3): Likewise.
463 (VEX_LEN_0F11_P_1): Likewise.
464 (VEX_LEN_0F11_P_3): Likewise.
465 (VEX_LEN_0F2E_P_0): Likewise.
466 (VEX_LEN_0F2E_P_2): Likewise.
467 (VEX_LEN_0F2F_P_0): Likewise.
468 (VEX_LEN_0F2F_P_2): Likewise.
469 (VEX_LEN_0F51_P_1): Likewise.
470 (VEX_LEN_0F51_P_3): Likewise.
471 (VEX_LEN_0F52_P_1): Likewise.
472 (VEX_LEN_0F53_P_1): Likewise.
473 (VEX_LEN_0F58_P_1): Likewise.
474 (VEX_LEN_0F58_P_3): Likewise.
475 (VEX_LEN_0F59_P_1): Likewise.
476 (VEX_LEN_0F59_P_3): Likewise.
477 (VEX_LEN_0F5A_P_1): Likewise.
478 (VEX_LEN_0F5A_P_3): Likewise.
479 (VEX_LEN_0F5C_P_1): Likewise.
480 (VEX_LEN_0F5C_P_3): Likewise.
481 (VEX_LEN_0F5D_P_1): Likewise.
482 (VEX_LEN_0F5D_P_3): Likewise.
483 (VEX_LEN_0F5E_P_1): Likewise.
484 (VEX_LEN_0F5E_P_3): Likewise.
485 (VEX_LEN_0F5F_P_1): Likewise.
486 (VEX_LEN_0F5F_P_3): Likewise.
487 (VEX_LEN_0FC2_P_1): Likewise.
488 (VEX_LEN_0FC2_P_3): Likewise.
489 (VEX_LEN_0F3A0A_P_2): Likewise.
490 (VEX_LEN_0F3A0B_P_2): Likewise.
491 (VEX_W_0F10_P_0): Likewise.
492 (VEX_W_0F10_P_1): Likewise.
493 (VEX_W_0F10_P_2): Likewise.
494 (VEX_W_0F10_P_3): Likewise.
495 (VEX_W_0F11_P_0): Likewise.
496 (VEX_W_0F11_P_1): Likewise.
497 (VEX_W_0F11_P_2): Likewise.
498 (VEX_W_0F11_P_3): Likewise.
499 (VEX_W_0F12_P_0_M_0): Likewise.
500 (VEX_W_0F12_P_0_M_1): Likewise.
501 (VEX_W_0F12_P_1): Likewise.
502 (VEX_W_0F12_P_2): Likewise.
503 (VEX_W_0F12_P_3): Likewise.
504 (VEX_W_0F13_M_0): Likewise.
505 (VEX_W_0F14): Likewise.
506 (VEX_W_0F15): Likewise.
507 (VEX_W_0F16_P_0_M_0): Likewise.
508 (VEX_W_0F16_P_0_M_1): Likewise.
509 (VEX_W_0F16_P_1): Likewise.
510 (VEX_W_0F16_P_2): Likewise.
511 (VEX_W_0F17_M_0): Likewise.
512 (VEX_W_0F28): Likewise.
513 (VEX_W_0F29): Likewise.
514 (VEX_W_0F2B_M_0): Likewise.
515 (VEX_W_0F2E_P_0): Likewise.
516 (VEX_W_0F2E_P_2): Likewise.
517 (VEX_W_0F2F_P_0): Likewise.
518 (VEX_W_0F2F_P_2): Likewise.
519 (VEX_W_0F50_M_0): Likewise.
520 (VEX_W_0F51_P_0): Likewise.
521 (VEX_W_0F51_P_1): Likewise.
522 (VEX_W_0F51_P_2): Likewise.
523 (VEX_W_0F51_P_3): Likewise.
524 (VEX_W_0F52_P_0): Likewise.
525 (VEX_W_0F52_P_1): Likewise.
526 (VEX_W_0F53_P_0): Likewise.
527 (VEX_W_0F53_P_1): Likewise.
528 (VEX_W_0F58_P_0): Likewise.
529 (VEX_W_0F58_P_1): Likewise.
530 (VEX_W_0F58_P_2): Likewise.
531 (VEX_W_0F58_P_3): Likewise.
532 (VEX_W_0F59_P_0): Likewise.
533 (VEX_W_0F59_P_1): Likewise.
534 (VEX_W_0F59_P_2): Likewise.
535 (VEX_W_0F59_P_3): Likewise.
536 (VEX_W_0F5A_P_0): Likewise.
537 (VEX_W_0F5A_P_1): Likewise.
538 (VEX_W_0F5A_P_3): Likewise.
539 (VEX_W_0F5B_P_0): Likewise.
540 (VEX_W_0F5B_P_1): Likewise.
541 (VEX_W_0F5B_P_2): Likewise.
542 (VEX_W_0F5C_P_0): Likewise.
543 (VEX_W_0F5C_P_1): Likewise.
544 (VEX_W_0F5C_P_2): Likewise.
545 (VEX_W_0F5C_P_3): Likewise.
546 (VEX_W_0F5D_P_0): Likewise.
547 (VEX_W_0F5D_P_1): Likewise.
548 (VEX_W_0F5D_P_2): Likewise.
549 (VEX_W_0F5D_P_3): Likewise.
550 (VEX_W_0F5E_P_0): Likewise.
551 (VEX_W_0F5E_P_1): Likewise.
552 (VEX_W_0F5E_P_2): Likewise.
553 (VEX_W_0F5E_P_3): Likewise.
554 (VEX_W_0F5F_P_0): Likewise.
555 (VEX_W_0F5F_P_1): Likewise.
556 (VEX_W_0F5F_P_2): Likewise.
557 (VEX_W_0F5F_P_3): Likewise.
558 (VEX_W_0F60_P_2): Likewise.
559 (VEX_W_0F61_P_2): Likewise.
560 (VEX_W_0F62_P_2): Likewise.
561 (VEX_W_0F63_P_2): Likewise.
562 (VEX_W_0F64_P_2): Likewise.
563 (VEX_W_0F65_P_2): Likewise.
564 (VEX_W_0F66_P_2): Likewise.
565 (VEX_W_0F67_P_2): Likewise.
566 (VEX_W_0F68_P_2): Likewise.
567 (VEX_W_0F69_P_2): Likewise.
568 (VEX_W_0F6A_P_2): Likewise.
569 (VEX_W_0F6B_P_2): Likewise.
570 (VEX_W_0F6C_P_2): Likewise.
571 (VEX_W_0F6D_P_2): Likewise.
572 (VEX_W_0F6F_P_1): Likewise.
573 (VEX_W_0F6F_P_2): Likewise.
574 (VEX_W_0F70_P_1): Likewise.
575 (VEX_W_0F70_P_2): Likewise.
576 (VEX_W_0F70_P_3): Likewise.
577 (VEX_W_0F71_R_2_P_2): Likewise.
578 (VEX_W_0F71_R_4_P_2): Likewise.
579 (VEX_W_0F71_R_6_P_2): Likewise.
580 (VEX_W_0F72_R_2_P_2): Likewise.
581 (VEX_W_0F72_R_4_P_2): Likewise.
582 (VEX_W_0F72_R_6_P_2): Likewise.
583 (VEX_W_0F73_R_2_P_2): Likewise.
584 (VEX_W_0F73_R_3_P_2): Likewise.
585 (VEX_W_0F73_R_6_P_2): Likewise.
586 (VEX_W_0F73_R_7_P_2): Likewise.
587 (VEX_W_0F74_P_2): Likewise.
588 (VEX_W_0F75_P_2): Likewise.
589 (VEX_W_0F76_P_2): Likewise.
590 (VEX_W_0F77_P_0): Likewise.
591 (VEX_W_0F7C_P_2): Likewise.
592 (VEX_W_0F7C_P_3): Likewise.
593 (VEX_W_0F7D_P_2): Likewise.
594 (VEX_W_0F7D_P_3): Likewise.
595 (VEX_W_0F7E_P_1): Likewise.
596 (VEX_W_0F7F_P_1): Likewise.
597 (VEX_W_0F7F_P_2): Likewise.
598 (VEX_W_0FAE_R_2_M_0): Likewise.
599 (VEX_W_0FAE_R_3_M_0): Likewise.
600 (VEX_W_0FC2_P_0): Likewise.
601 (VEX_W_0FC2_P_1): Likewise.
602 (VEX_W_0FC2_P_2): Likewise.
603 (VEX_W_0FC2_P_3): Likewise.
604 (VEX_W_0FD0_P_2): Likewise.
605 (VEX_W_0FD0_P_3): Likewise.
606 (VEX_W_0FD1_P_2): Likewise.
607 (VEX_W_0FD2_P_2): Likewise.
608 (VEX_W_0FD3_P_2): Likewise.
609 (VEX_W_0FD4_P_2): Likewise.
610 (VEX_W_0FD5_P_2): Likewise.
611 (VEX_W_0FD6_P_2): Likewise.
612 (VEX_W_0FD7_P_2_M_1): Likewise.
613 (VEX_W_0FD8_P_2): Likewise.
614 (VEX_W_0FD9_P_2): Likewise.
615 (VEX_W_0FDA_P_2): Likewise.
616 (VEX_W_0FDB_P_2): Likewise.
617 (VEX_W_0FDC_P_2): Likewise.
618 (VEX_W_0FDD_P_2): Likewise.
619 (VEX_W_0FDE_P_2): Likewise.
620 (VEX_W_0FDF_P_2): Likewise.
621 (VEX_W_0FE0_P_2): Likewise.
622 (VEX_W_0FE1_P_2): Likewise.
623 (VEX_W_0FE2_P_2): Likewise.
624 (VEX_W_0FE3_P_2): Likewise.
625 (VEX_W_0FE4_P_2): Likewise.
626 (VEX_W_0FE5_P_2): Likewise.
627 (VEX_W_0FE6_P_1): Likewise.
628 (VEX_W_0FE6_P_2): Likewise.
629 (VEX_W_0FE6_P_3): Likewise.
630 (VEX_W_0FE7_P_2_M_0): Likewise.
631 (VEX_W_0FE8_P_2): Likewise.
632 (VEX_W_0FE9_P_2): Likewise.
633 (VEX_W_0FEA_P_2): Likewise.
634 (VEX_W_0FEB_P_2): Likewise.
635 (VEX_W_0FEC_P_2): Likewise.
636 (VEX_W_0FED_P_2): Likewise.
637 (VEX_W_0FEE_P_2): Likewise.
638 (VEX_W_0FEF_P_2): Likewise.
639 (VEX_W_0FF0_P_3_M_0): Likewise.
640 (VEX_W_0FF1_P_2): Likewise.
641 (VEX_W_0FF2_P_2): Likewise.
642 (VEX_W_0FF3_P_2): Likewise.
643 (VEX_W_0FF4_P_2): Likewise.
644 (VEX_W_0FF5_P_2): Likewise.
645 (VEX_W_0FF6_P_2): Likewise.
646 (VEX_W_0FF7_P_2): Likewise.
647 (VEX_W_0FF8_P_2): Likewise.
648 (VEX_W_0FF9_P_2): Likewise.
649 (VEX_W_0FFA_P_2): Likewise.
650 (VEX_W_0FFB_P_2): Likewise.
651 (VEX_W_0FFC_P_2): Likewise.
652 (VEX_W_0FFD_P_2): Likewise.
653 (VEX_W_0FFE_P_2): Likewise.
654 (VEX_W_0F3800_P_2): Likewise.
655 (VEX_W_0F3801_P_2): Likewise.
656 (VEX_W_0F3802_P_2): Likewise.
657 (VEX_W_0F3803_P_2): Likewise.
658 (VEX_W_0F3804_P_2): Likewise.
659 (VEX_W_0F3805_P_2): Likewise.
660 (VEX_W_0F3806_P_2): Likewise.
661 (VEX_W_0F3807_P_2): Likewise.
662 (VEX_W_0F3808_P_2): Likewise.
663 (VEX_W_0F3809_P_2): Likewise.
664 (VEX_W_0F380A_P_2): Likewise.
665 (VEX_W_0F380B_P_2): Likewise.
666 (VEX_W_0F3817_P_2): Likewise.
667 (VEX_W_0F381C_P_2): Likewise.
668 (VEX_W_0F381D_P_2): Likewise.
669 (VEX_W_0F381E_P_2): Likewise.
670 (VEX_W_0F3820_P_2): Likewise.
671 (VEX_W_0F3821_P_2): Likewise.
672 (VEX_W_0F3822_P_2): Likewise.
673 (VEX_W_0F3823_P_2): Likewise.
674 (VEX_W_0F3824_P_2): Likewise.
675 (VEX_W_0F3825_P_2): Likewise.
676 (VEX_W_0F3828_P_2): Likewise.
677 (VEX_W_0F3829_P_2): Likewise.
678 (VEX_W_0F382A_P_2_M_0): Likewise.
679 (VEX_W_0F382B_P_2): Likewise.
680 (VEX_W_0F3830_P_2): Likewise.
681 (VEX_W_0F3831_P_2): Likewise.
682 (VEX_W_0F3832_P_2): Likewise.
683 (VEX_W_0F3833_P_2): Likewise.
684 (VEX_W_0F3834_P_2): Likewise.
685 (VEX_W_0F3835_P_2): Likewise.
686 (VEX_W_0F3837_P_2): Likewise.
687 (VEX_W_0F3838_P_2): Likewise.
688 (VEX_W_0F3839_P_2): Likewise.
689 (VEX_W_0F383A_P_2): Likewise.
690 (VEX_W_0F383B_P_2): Likewise.
691 (VEX_W_0F383C_P_2): Likewise.
692 (VEX_W_0F383D_P_2): Likewise.
693 (VEX_W_0F383E_P_2): Likewise.
694 (VEX_W_0F383F_P_2): Likewise.
695 (VEX_W_0F3840_P_2): Likewise.
696 (VEX_W_0F3841_P_2): Likewise.
697 (VEX_W_0F38DB_P_2): Likewise.
698 (VEX_W_0F3A08_P_2): Likewise.
699 (VEX_W_0F3A09_P_2): Likewise.
700 (VEX_W_0F3A0A_P_2): Likewise.
701 (VEX_W_0F3A0B_P_2): Likewise.
702 (VEX_W_0F3A0C_P_2): Likewise.
703 (VEX_W_0F3A0D_P_2): Likewise.
704 (VEX_W_0F3A0E_P_2): Likewise.
705 (VEX_W_0F3A0F_P_2): Likewise.
706 (VEX_W_0F3A21_P_2): Likewise.
707 (VEX_W_0F3A40_P_2): Likewise.
708 (VEX_W_0F3A41_P_2): Likewise.
709 (VEX_W_0F3A42_P_2): Likewise.
710 (VEX_W_0F3A62_P_2): Likewise.
711 (VEX_W_0F3A63_P_2): Likewise.
712 (VEX_W_0F3ADF_P_2): Likewise.
713 (VEX_LEN_0F77_P_0): New.
714 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
715 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
716 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
717 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
718 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
719 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
720 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
721 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
722 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
723 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
724 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
725 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
726 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
727 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
728 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
729 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
730 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
731 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
732 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
733 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
734 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
735 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
736 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
737 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
738 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
739 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
740 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
741 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
742 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
743 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
744 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
745 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
746 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
747 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
748 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
749 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
750 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
751 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
752 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
753 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
754 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
755 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
756 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
757 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
758 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
759 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
760 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
761 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
762 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
763 (vex_table): Update VEX 0F28 and 0F29 entries.
764 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
765 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
766 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
767 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
768 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
769 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
770 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
771 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
772 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
773 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
774 VEX_LEN_0F3A0B_P_2 entries.
775 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
776 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
777 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
778 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
779 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
780 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
781 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
782 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
783 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
784 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
785 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
786 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
787 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
788 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
789 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
790 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
791 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
792 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
793 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
794 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
795 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
796 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
797 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
798 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
799 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
800 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
801 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
802 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
803 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
804 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
805 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
806 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
807 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
808 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
809 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
810 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
811 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
812 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
813 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
814 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
815 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
816 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
817 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
818 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
819 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
820 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
821 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
822 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
823 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
824 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
825 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
826 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
827 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
828 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
829 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
830 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
831 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
832 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
833 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
834 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
835 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
836 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
837 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
838 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
839 VEX_W_0F3ADF_P_2 entries.
840 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
841 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
842 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
844 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
846 * i386-opc.tbl (VexWIG): New.
847 Replace VexW=3 with VexWIG.
849 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
851 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
852 * i386-tbl.h: Regenerated.
854 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
857 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
858 VEX_LEN_0FD6_P_2 entries.
859 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
860 * i386-tbl.h: Regenerated.
862 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
865 * i386-opc.h (VEXWIG): New.
866 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
867 * i386-tbl.h: Regenerated.
869 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
872 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
873 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
874 * i386-dis.c (EXxEVexR64): New.
875 (evex_rounding_64_mode): Likewise.
876 (OP_Rounding): Handle evex_rounding_64_mode.
878 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
881 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
882 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
883 * i386-dis.c (Edqa): New.
884 (dqa_mode): Likewise.
885 (intel_operand_size): Handle dqa_mode as m_mode.
886 (OP_E_register): Handle dqa_mode as dq_mode.
887 (OP_E_memory): Set shift for dqa_mode based on address_mode.
889 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
891 * i386-dis.c (OP_E_memory): Reformat.
893 2018-09-14 Jan Beulich <jbeulich@suse.com>
895 * i386-opc.tbl (crc32): Fold byte and word forms.
896 * i386-tbl.h: Re-generate.
898 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
900 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
901 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
902 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
903 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
904 * i386-tbl.h: Regenerated.
906 2018-09-13 Jan Beulich <jbeulich@suse.com>
908 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
910 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
911 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
912 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
913 * i386-tbl.h: Re-generate.
915 2018-09-13 Jan Beulich <jbeulich@suse.com>
917 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
919 * i386-tbl.h: Re-generate.
921 2018-09-13 Jan Beulich <jbeulich@suse.com>
923 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
925 * i386-tbl.h: Re-generate.
927 2018-09-13 Jan Beulich <jbeulich@suse.com>
929 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
931 * i386-tbl.h: Re-generate.
933 2018-09-13 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
937 * i386-tbl.h: Re-generate.
939 2018-09-13 Jan Beulich <jbeulich@suse.com>
941 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
943 * i386-tbl.h: Re-generate.
945 2018-09-13 Jan Beulich <jbeulich@suse.com>
947 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
949 * i386-tbl.h: Re-generate.
951 2018-09-13 Jan Beulich <jbeulich@suse.com>
953 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
954 * i386-tbl.h: Re-generate.
956 2018-09-13 Jan Beulich <jbeulich@suse.com>
958 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
959 * i386-tbl.h: Re-generate.
961 2018-09-13 Jan Beulich <jbeulich@suse.com>
963 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
965 * i386-tbl.h: Re-generate.
967 2018-09-13 Jan Beulich <jbeulich@suse.com>
969 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
971 * i386-tbl.h: Re-generate.
973 2018-09-13 Jan Beulich <jbeulich@suse.com>
975 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
976 * i386-tbl.h: Re-generate.
978 2018-09-13 Jan Beulich <jbeulich@suse.com>
980 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
981 * i386-tbl.h: Re-generate.
983 2018-09-13 Jan Beulich <jbeulich@suse.com>
985 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
986 * i386-tbl.h: Re-generate.
988 2018-09-13 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
992 * i386-tbl.h: Re-generate.
994 2018-09-13 Jan Beulich <jbeulich@suse.com>
996 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
998 * i386-tbl.h: Re-generate.
1000 2018-09-13 Jan Beulich <jbeulich@suse.com>
1002 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1004 * i386-tbl.h: Re-generate.
1006 2018-09-13 Jan Beulich <jbeulich@suse.com>
1008 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1009 * i386-tbl.h: Re-generate.
1011 2018-09-13 Jan Beulich <jbeulich@suse.com>
1013 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1014 * i386-tbl.h: Re-generate.
1016 2018-09-13 Jan Beulich <jbeulich@suse.com>
1018 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1019 * i386-tbl.h: Re-generate.
1021 2018-09-13 Jan Beulich <jbeulich@suse.com>
1023 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1024 (vpbroadcastw, rdpid): Drop NoRex64.
1025 * i386-tbl.h: Re-generate.
1027 2018-09-13 Jan Beulich <jbeulich@suse.com>
1029 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1030 store templates, adding D.
1031 * i386-tbl.h: Re-generate.
1033 2018-09-13 Jan Beulich <jbeulich@suse.com>
1035 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1036 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1037 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1038 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1039 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1040 Fold load and store templates where possible, adding D. Drop
1041 IgnoreSize where it was pointlessly present. Drop redundant
1043 * i386-tbl.h: Re-generate.
1045 2018-09-13 Jan Beulich <jbeulich@suse.com>
1047 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1048 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1049 (intel_operand_size): Handle v_bndmk_mode.
1050 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1052 2018-09-08 John Darrington <john@darrington.wattle.id.au>
1054 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1056 2018-08-31 Kito Cheng <kito@andestech.com>
1058 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1059 compressed floating point instructions.
1061 2018-08-30 Kito Cheng <kito@andestech.com>
1063 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1064 riscv_opcode.xlen_requirement.
1065 * riscv-opc.c (riscv_opcodes): Update for struct change.
1067 2018-08-29 Martin Aberg <maberg@gaisler.com>
1069 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1070 psr (PWRPSR) instruction.
1072 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1074 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1076 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1078 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1080 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1082 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1083 loongson3a as an alias of gs464 for compatibility.
1084 * mips-opc.c (mips_opcodes): Change Comments.
1086 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1088 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1090 (print_mips_disassembler_options): Document -M loongson-ext.
1091 * mips-opc.c (LEXT2): New macro.
1092 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1094 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1096 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1098 (parse_mips_ase_option): Handle -M loongson-ext option.
1099 (print_mips_disassembler_options): Document -M loongson-ext.
1100 * mips-opc.c (IL3A): Delete.
1101 * mips-opc.c (LEXT): New macro.
1102 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1105 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1107 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1109 (parse_mips_ase_option): Handle -M loongson-cam option.
1110 (print_mips_disassembler_options): Document -M loongson-cam.
1111 * mips-opc.c (LCAM): New macro.
1112 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1115 2018-08-21 Alan Modra <amodra@gmail.com>
1117 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1118 (skip_optional_operands): Count optional operands, and update
1119 ppc_optional_operand_value call.
1120 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1121 (extract_vlensi): Likewise.
1122 (extract_fxm): Return default value for missing optional operand.
1123 (extract_ls, extract_raq, extract_tbr): Likewise.
1124 (insert_sxl, extract_sxl): New functions.
1125 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1126 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1127 flag and extra entry.
1128 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1131 2018-08-20 Alan Modra <amodra@gmail.com>
1133 * sh-opc.h (MASK): Simplify.
1135 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1137 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1138 BM_RESERVED0 or BM_RESERVED1
1139 (bm_rel_decode, bm_n_bytes): Ditto.
1141 2018-08-18 John Darrington <john@darrington.wattle.id.au>
1145 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1147 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1148 address with the addr32 prefix and without base nor index
1151 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1153 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1154 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1155 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1156 (cpu_flags): Add CpuCMOV and CpuFXSR.
1157 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1158 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1159 * i386-init.h: Regenerated.
1160 * i386-tbl.h: Likewise.
1162 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1164 * arc-regs.h: Update auxiliary registers.
1166 2018-08-06 Jan Beulich <jbeulich@suse.com>
1168 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1169 (RegIP, RegIZ): Define.
1170 * i386-reg.tbl: Adjust comments.
1171 (rip): Use Qword instead of BaseIndex. Use RegIP.
1172 (eip): Use Dword instead of BaseIndex. Use RegIP.
1173 (riz): Add Qword. Use RegIZ.
1174 (eiz): Add Dword. Use RegIZ.
1175 * i386-tbl.h: Re-generate.
1177 2018-08-03 Jan Beulich <jbeulich@suse.com>
1179 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1180 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1181 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1182 * i386-tbl.h: Re-generate.
1184 2018-08-03 Jan Beulich <jbeulich@suse.com>
1186 * i386-gen.c (operand_types): Remove Mem field.
1187 * i386-opc.h (union i386_operand_type): Remove mem field.
1188 * i386-init.h, i386-tbl.h: Re-generate.
1190 2018-08-01 Alan Modra <amodra@gmail.com>
1192 * po/POTFILES.in: Regenerate.
1194 2018-07-31 Nick Clifton <nickc@redhat.com>
1196 * po/sv.po: Updated Swedish translation.
1198 2018-07-31 Jan Beulich <jbeulich@suse.com>
1200 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1201 * i386-init.h, i386-tbl.h: Re-generate.
1203 2018-07-31 Jan Beulich <jbeulich@suse.com>
1205 * i386-opc.h (ZEROING_MASKING) Rename to ...
1206 (DYNAMIC_MASKING): ... this. Adjust comment.
1207 * i386-opc.tbl (MaskingMorZ): Define.
1208 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1209 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1210 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1211 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1212 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1213 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1214 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1215 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1216 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1218 2018-07-31 Jan Beulich <jbeulich@suse.com>
1220 * i386-opc.tbl: Use element rather than vector size for AVX512*
1221 scatter/gather insns.
1222 * i386-tbl.h: Re-generate.
1224 2018-07-31 Jan Beulich <jbeulich@suse.com>
1226 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1227 (cpu_flags): Drop CpuVREX.
1228 * i386-opc.h (CpuVREX): Delete.
1229 (union i386_cpu_flags): Remove cpuvrex.
1230 * i386-init.h, i386-tbl.h: Re-generate.
1232 2018-07-30 Jim Wilson <jimw@sifive.com>
1234 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1236 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1238 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1240 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1241 * Makefile.in: Regenerated.
1242 * configure.ac: Add C-SKY.
1243 * configure: Regenerated.
1244 * csky-dis.c: New file.
1245 * csky-opc.h: New file.
1246 * disassemble.c (ARCH_csky): Define.
1247 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1248 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1250 2018-07-27 Alan Modra <amodra@gmail.com>
1252 * ppc-opc.c (insert_sprbat): Correct function parameter and
1254 (extract_sprbat): Likewise, variable too.
1256 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1257 Alan Modra <amodra@gmail.com>
1259 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1260 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1261 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1262 support disjointed BAT.
1263 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1264 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1265 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1267 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1268 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1270 * i386-gen.c (adjust_broadcast_modifier): New function.
1271 (process_i386_opcode_modifier): Add an argument for operands.
1272 Adjust the Broadcast value based on operands.
1273 (output_i386_opcode): Pass operand_types to
1274 process_i386_opcode_modifier.
1275 (process_i386_opcodes): Pass NULL as operands to
1276 process_i386_opcode_modifier.
1277 * i386-opc.h (BYTE_BROADCAST): New.
1278 (WORD_BROADCAST): Likewise.
1279 (DWORD_BROADCAST): Likewise.
1280 (QWORD_BROADCAST): Likewise.
1281 (i386_opcode_modifier): Expand broadcast to 3 bits.
1282 * i386-tbl.h: Regenerated.
1284 2018-07-24 Alan Modra <amodra@gmail.com>
1287 * or1k-desc.h: Regenerate.
1289 2018-07-24 Jan Beulich <jbeulich@suse.com>
1291 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1292 vcvtusi2ss, and vcvtusi2sd.
1293 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1294 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1295 * i386-tbl.h: Re-generate.
1297 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1299 * arc-opc.c (extract_w6): Fix extending the sign.
1301 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1303 * arc-tbl.h (vewt): Allow it for ARC EM family.
1305 2018-07-23 Alan Modra <amodra@gmail.com>
1308 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1309 opcode variants for mtspr/mfspr encodings.
1311 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1312 Maciej W. Rozycki <macro@mips.com>
1314 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1315 loongson3a descriptors.
1316 (parse_mips_ase_option): Handle -M loongson-mmi option.
1317 (print_mips_disassembler_options): Document -M loongson-mmi.
1318 * mips-opc.c (LMMI): New macro.
1319 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1322 2018-07-19 Jan Beulich <jbeulich@suse.com>
1324 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1325 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1326 IgnoreSize and [XYZ]MMword where applicable.
1327 * i386-tbl.h: Re-generate.
1329 2018-07-19 Jan Beulich <jbeulich@suse.com>
1331 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1332 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1333 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1334 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1335 * i386-tbl.h: Re-generate.
1337 2018-07-19 Jan Beulich <jbeulich@suse.com>
1339 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1340 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1341 VPCLMULQDQ templates into their respective AVX512VL counterparts
1342 where possible, using Disp8ShiftVL and CheckRegSize instead of
1343 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1344 * i386-tbl.h: Re-generate.
1346 2018-07-19 Jan Beulich <jbeulich@suse.com>
1348 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1349 AVX512VL counterparts where possible, using Disp8ShiftVL and
1350 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1351 IgnoreSize) as appropriate.
1352 * i386-tbl.h: Re-generate.
1354 2018-07-19 Jan Beulich <jbeulich@suse.com>
1356 * i386-opc.tbl: Fold AVX512BW templates into their respective
1357 AVX512VL counterparts where possible, using Disp8ShiftVL and
1358 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1359 IgnoreSize) as appropriate.
1360 * i386-tbl.h: Re-generate.
1362 2018-07-19 Jan Beulich <jbeulich@suse.com>
1364 * i386-opc.tbl: Fold AVX512CD templates into their respective
1365 AVX512VL counterparts where possible, using Disp8ShiftVL and
1366 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1367 IgnoreSize) as appropriate.
1368 * i386-tbl.h: Re-generate.
1370 2018-07-19 Jan Beulich <jbeulich@suse.com>
1372 * i386-opc.h (DISP8_SHIFT_VL): New.
1373 * i386-opc.tbl (Disp8ShiftVL): Define.
1374 (various): Fold AVX512VL templates into their respective
1375 AVX512F counterparts where possible, using Disp8ShiftVL and
1376 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1377 IgnoreSize) as appropriate.
1378 * i386-tbl.h: Re-generate.
1380 2018-07-19 Jan Beulich <jbeulich@suse.com>
1382 * Makefile.am: Change dependencies and rule for
1383 $(srcdir)/i386-init.h.
1384 * Makefile.in: Re-generate.
1385 * i386-gen.c (process_i386_opcodes): New local variable
1386 "marker". Drop opening of input file. Recognize marker and line
1388 * i386-opc.tbl (OPCODE_I386_H): Define.
1389 (i386-opc.h): Include it.
1392 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1395 * i386-opc.h (Byte): Update comments.
1401 (Xmmword): Likewise.
1402 (Ymmword): Likewise.
1403 (Zmmword): Likewise.
1404 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1406 * i386-tbl.h: Regenerated.
1408 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1410 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1411 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1412 * aarch64-asm-2.c: Regenerate.
1413 * aarch64-dis-2.c: Regenerate.
1414 * aarch64-opc-2.c: Regenerate.
1416 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1419 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1420 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1421 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1422 sqdmulh, sqrdmulh): Use Em16.
1424 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1426 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1427 csdb together with them.
1428 (thumb32_opcodes): Likewise.
1430 2018-07-11 Jan Beulich <jbeulich@suse.com>
1432 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1433 requiring 32-bit registers as operands 2 and 3. Improve
1435 (mwait, mwaitx): Fold templates. Improve comments.
1436 OPERAND_TYPE_INOUTPORTREG.
1437 * i386-tbl.h: Re-generate.
1439 2018-07-11 Jan Beulich <jbeulich@suse.com>
1441 * i386-gen.c (operand_type_init): Remove
1442 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1443 OPERAND_TYPE_INOUTPORTREG.
1444 * i386-init.h: Re-generate.
1446 2018-07-11 Jan Beulich <jbeulich@suse.com>
1448 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1449 (wrssq, wrussq): Add Qword.
1450 * i386-tbl.h: Re-generate.
1452 2018-07-11 Jan Beulich <jbeulich@suse.com>
1454 * i386-opc.h: Rename OTMax to OTNum.
1455 (OTNumOfUints): Adjust calculation.
1456 (OTUnused): Directly alias to OTNum.
1458 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1460 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1462 (lea_reg_xys): Likewise.
1463 (print_insn_loop_primitive): Rename `reg' local variable to
1466 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1469 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1471 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1474 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1475 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1477 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1480 * mips-dis.c (mips_option_arg_t): New enumeration.
1481 (mips_options): New variable.
1482 (disassembler_options_mips): New function.
1483 (print_mips_disassembler_options): Reimplement in terms of
1484 `disassembler_options_mips'.
1485 * arm-dis.c (disassembler_options_arm): Adapt to using the
1486 `disasm_options_and_args_t' structure.
1487 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1488 * s390-dis.c (disassembler_options_s390): Likewise.
1490 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1492 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1494 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1495 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1496 * testsuite/ld-arm/tls-longplt.d: Likewise.
1498 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1501 * aarch64-asm-2.c: Regenerate.
1502 * aarch64-dis-2.c: Likewise.
1503 * aarch64-opc-2.c: Likewise.
1504 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1505 * aarch64-opc.c (operand_general_constraint_met_p,
1506 aarch64_print_operand): Likewise.
1507 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1508 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1510 (AARCH64_OPERANDS): Add Em2.
1512 2018-06-26 Nick Clifton <nickc@redhat.com>
1514 * po/uk.po: Updated Ukranian translation.
1515 * po/de.po: Updated German translation.
1516 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1518 2018-06-26 Nick Clifton <nickc@redhat.com>
1520 * nfp-dis.c: Fix spelling mistake.
1522 2018-06-24 Nick Clifton <nickc@redhat.com>
1524 * configure: Regenerate.
1525 * po/opcodes.pot: Regenerate.
1527 2018-06-24 Nick Clifton <nickc@redhat.com>
1529 2.31 branch created.
1531 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1533 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1534 * aarch64-asm-2.c: Regenerate.
1535 * aarch64-dis-2.c: Likewise.
1537 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1539 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1540 `-M ginv' option description.
1542 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1545 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1548 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1550 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1551 * configure.ac: Remove AC_PREREQ.
1552 * Makefile.in: Re-generate.
1553 * aclocal.m4: Re-generate.
1554 * configure: Re-generate.
1556 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1558 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1559 mips64r6 descriptors.
1560 (parse_mips_ase_option): Handle -Mginv option.
1561 (print_mips_disassembler_options): Document -Mginv.
1562 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1564 (mips_opcodes): Define ginvi and ginvt.
1566 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1567 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1569 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1570 * mips-opc.c (CRC, CRC64): New macros.
1571 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1572 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1575 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1578 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1579 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1581 2018-06-06 Alan Modra <amodra@gmail.com>
1583 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1584 setjmp. Move init for some other vars later too.
1586 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1588 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1589 (dis_private): Add new fields for property section tracking.
1590 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1591 (xtensa_instruction_fits): New functions.
1592 (fetch_data): Bump minimal fetch size to 4.
1593 (print_insn_xtensa): Make struct dis_private static.
1594 Load and prepare property table on section change.
1595 Don't disassemble literals. Don't disassemble instructions that
1596 cross property table boundaries.
1598 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1600 * configure: Regenerated.
1602 2018-06-01 Jan Beulich <jbeulich@suse.com>
1604 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1605 * i386-tbl.h: Re-generate.
1607 2018-06-01 Jan Beulich <jbeulich@suse.com>
1609 * i386-opc.tbl (sldt, str): Add NoRex64.
1610 * i386-tbl.h: Re-generate.
1612 2018-06-01 Jan Beulich <jbeulich@suse.com>
1614 * i386-opc.tbl (invpcid): Add Oword.
1615 * i386-tbl.h: Re-generate.
1617 2018-06-01 Alan Modra <amodra@gmail.com>
1619 * sysdep.h (_bfd_error_handler): Don't declare.
1620 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1621 * rl78-decode.opc: Likewise.
1622 * msp430-decode.c: Regenerate.
1623 * rl78-decode.c: Regenerate.
1625 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1627 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1628 * i386-init.h : Regenerated.
1630 2018-05-25 Alan Modra <amodra@gmail.com>
1632 * Makefile.in: Regenerate.
1633 * po/POTFILES.in: Regenerate.
1635 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1637 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1638 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1639 (insert_bab, extract_bab, insert_btab, extract_btab,
1640 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1641 (BAT, BBA VBA RBS XB6S): Delete macros.
1642 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1643 (BB, BD, RBX, XC6): Update for new macros.
1644 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1645 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1646 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1647 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1649 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1651 * Makefile.am: Add support for s12z architecture.
1652 * configure.ac: Likewise.
1653 * disassemble.c: Likewise.
1654 * disassemble.h: Likewise.
1655 * Makefile.in: Regenerate.
1656 * configure: Regenerate.
1657 * s12z-dis.c: New file.
1660 2018-05-18 Alan Modra <amodra@gmail.com>
1662 * nfp-dis.c: Don't #include libbfd.h.
1663 (init_nfp3200_priv): Use bfd_get_section_contents.
1664 (nit_nfp6000_mecsr_sec): Likewise.
1666 2018-05-17 Nick Clifton <nickc@redhat.com>
1668 * po/zh_CN.po: Updated simplified Chinese translation.
1670 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1673 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1674 * aarch64-dis-2.c: Regenerate.
1676 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1679 * aarch64-asm.c (opintl.h): Include.
1680 (aarch64_ins_sysreg): Enforce read/write constraints.
1681 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1682 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1683 (F_REG_READ, F_REG_WRITE): New.
1684 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1685 AARCH64_OPND_SYSREG.
1686 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1687 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1688 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1689 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1690 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1691 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1692 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1693 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1694 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1695 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1696 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1697 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1698 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1699 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1700 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1701 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1702 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1704 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1707 * aarch64-dis.c (no_notes: New.
1708 (parse_aarch64_dis_option): Support notes.
1709 (aarch64_decode_insn, print_operands): Likewise.
1710 (print_aarch64_disassembler_options): Document notes.
1711 * aarch64-opc.c (aarch64_print_operand): Support notes.
1713 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1716 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1717 and take error struct.
1718 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1719 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1720 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1721 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1722 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1723 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1724 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1725 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1726 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1727 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1728 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1729 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1730 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1731 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1732 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1733 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1734 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1735 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1736 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1737 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1738 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1739 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1740 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1741 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1742 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1743 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1744 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1745 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1746 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1747 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1748 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1749 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1750 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1751 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1752 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1753 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1754 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1755 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1756 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1757 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1758 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1759 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1760 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1761 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1762 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1763 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1764 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1765 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1766 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1767 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1768 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1769 (determine_disassembling_preference, aarch64_decode_insn,
1770 print_insn_aarch64_word, print_insn_data): Take errors struct.
1771 (print_insn_aarch64): Use errors.
1772 * aarch64-asm-2.c: Regenerate.
1773 * aarch64-dis-2.c: Regenerate.
1774 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1775 boolean in aarch64_insert_operan.
1776 (print_operand_extractor): Likewise.
1777 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1779 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1781 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1783 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1785 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1787 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1789 * cr16-opc.c (cr16_instruction): Comment typo fix.
1790 * hppa-dis.c (print_insn_hppa): Likewise.
1792 2018-05-08 Jim Wilson <jimw@sifive.com>
1794 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1795 (match_c_slli64, match_srxi_as_c_srxi): New.
1796 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1797 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1798 <c.slli, c.srli, c.srai>: Use match_s_slli.
1799 <c.slli64, c.srli64, c.srai64>: New.
1801 2018-05-08 Alan Modra <amodra@gmail.com>
1803 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1804 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1805 partition opcode space for index lookup.
1807 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1809 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1810 <insn_length>: ...with this. Update usage.
1811 Remove duplicate call to *info->memory_error_func.
1813 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1814 H.J. Lu <hongjiu.lu@intel.com>
1816 * i386-dis.c (Gva): New.
1817 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1818 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1819 (prefix_table): New instructions (see prefix above).
1820 (mod_table): New instructions (see prefix above).
1821 (OP_G): Handle va_mode.
1822 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1823 CPU_MOVDIR64B_FLAGS.
1824 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1825 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1826 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1827 * i386-opc.tbl: Add movidir{i,64b}.
1828 * i386-init.h: Regenerated.
1829 * i386-tbl.h: Likewise.
1831 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1833 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1835 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1836 (AddrPrefixOpReg): This.
1837 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1838 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1840 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1842 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1843 (vle_num_opcodes): Likewise.
1844 (spe2_num_opcodes): Likewise.
1845 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1846 initialization loop.
1847 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1848 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1851 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1853 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1855 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1857 Makefile.am: Added nfp-dis.c.
1858 configure.ac: Added bfd_nfp_arch.
1859 disassemble.h: Added print_insn_nfp prototype.
1860 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1861 nfp-dis.c: New, for NFP support.
1862 po/POTFILES.in: Added nfp-dis.c to the list.
1863 Makefile.in: Regenerate.
1864 configure: Regenerate.
1866 2018-04-26 Jan Beulich <jbeulich@suse.com>
1868 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1869 templates into their base ones.
1870 * i386-tlb.h: Re-generate.
1872 2018-04-26 Jan Beulich <jbeulich@suse.com>
1874 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1875 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1876 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1877 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1878 * i386-init.h: Re-generate.
1880 2018-04-26 Jan Beulich <jbeulich@suse.com>
1882 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1883 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1884 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1885 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1887 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1889 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1891 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1892 cpuregzmm, and cpuregmask.
1893 * i386-init.h: Re-generate.
1894 * i386-tbl.h: Re-generate.
1896 2018-04-26 Jan Beulich <jbeulich@suse.com>
1898 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1899 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1900 * i386-init.h: Re-generate.
1902 2018-04-26 Jan Beulich <jbeulich@suse.com>
1904 * i386-gen.c (VexImmExt): Delete.
1905 * i386-opc.h (VexImmExt, veximmext): Delete.
1906 * i386-opc.tbl: Drop all VexImmExt uses.
1907 * i386-tlb.h: Re-generate.
1909 2018-04-25 Jan Beulich <jbeulich@suse.com>
1911 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1912 register-only forms.
1913 * i386-tlb.h: Re-generate.
1915 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1917 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1919 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1921 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1923 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1924 (cpu_flags): Add CpuCLDEMOTE.
1925 * i386-init.h: Regenerate.
1926 * i386-opc.h (enum): Add CpuCLDEMOTE,
1927 (i386_cpu_flags): Add cpucldemote.
1928 * i386-opc.tbl: Add cldemote.
1929 * i386-tbl.h: Regenerate.
1931 2018-04-16 Alan Modra <amodra@gmail.com>
1933 * Makefile.am: Remove sh5 and sh64 support.
1934 * configure.ac: Likewise.
1935 * disassemble.c: Likewise.
1936 * disassemble.h: Likewise.
1937 * sh-dis.c: Likewise.
1938 * sh64-dis.c: Delete.
1939 * sh64-opc.c: Delete.
1940 * sh64-opc.h: Delete.
1941 * Makefile.in: Regenerate.
1942 * configure: Regenerate.
1943 * po/POTFILES.in: Regenerate.
1945 2018-04-16 Alan Modra <amodra@gmail.com>
1947 * Makefile.am: Remove w65 support.
1948 * configure.ac: Likewise.
1949 * disassemble.c: Likewise.
1950 * disassemble.h: Likewise.
1951 * w65-dis.c: Delete.
1952 * w65-opc.h: Delete.
1953 * Makefile.in: Regenerate.
1954 * configure: Regenerate.
1955 * po/POTFILES.in: Regenerate.
1957 2018-04-16 Alan Modra <amodra@gmail.com>
1959 * configure.ac: Remove we32k support.
1960 * configure: Regenerate.
1962 2018-04-16 Alan Modra <amodra@gmail.com>
1964 * Makefile.am: Remove m88k support.
1965 * configure.ac: Likewise.
1966 * disassemble.c: Likewise.
1967 * disassemble.h: Likewise.
1968 * m88k-dis.c: Delete.
1969 * Makefile.in: Regenerate.
1970 * configure: Regenerate.
1971 * po/POTFILES.in: Regenerate.
1973 2018-04-16 Alan Modra <amodra@gmail.com>
1975 * Makefile.am: Remove i370 support.
1976 * configure.ac: Likewise.
1977 * disassemble.c: Likewise.
1978 * disassemble.h: Likewise.
1979 * i370-dis.c: Delete.
1980 * i370-opc.c: Delete.
1981 * Makefile.in: Regenerate.
1982 * configure: Regenerate.
1983 * po/POTFILES.in: Regenerate.
1985 2018-04-16 Alan Modra <amodra@gmail.com>
1987 * Makefile.am: Remove h8500 support.
1988 * configure.ac: Likewise.
1989 * disassemble.c: Likewise.
1990 * disassemble.h: Likewise.
1991 * h8500-dis.c: Delete.
1992 * h8500-opc.h: Delete.
1993 * Makefile.in: Regenerate.
1994 * configure: Regenerate.
1995 * po/POTFILES.in: Regenerate.
1997 2018-04-16 Alan Modra <amodra@gmail.com>
1999 * configure.ac: Remove tahoe support.
2000 * configure: Regenerate.
2002 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2004 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2006 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2008 * i386-tbl.h: Regenerated.
2010 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2012 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2013 PREFIX_MOD_1_0FAE_REG_6.
2015 (OP_E_register): Use va_mode.
2016 * i386-dis-evex.h (prefix_table):
2017 New instructions (see prefixes above).
2018 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2019 (cpu_flags): Likewise.
2020 * i386-opc.h (enum): Likewise.
2021 (i386_cpu_flags): Likewise.
2022 * i386-opc.tbl: Add umonitor, umwait, tpause.
2023 * i386-init.h: Regenerate.
2024 * i386-tbl.h: Likewise.
2026 2018-04-11 Alan Modra <amodra@gmail.com>
2028 * opcodes/i860-dis.c: Delete.
2029 * opcodes/i960-dis.c: Delete.
2030 * Makefile.am: Remove i860 and i960 support.
2031 * configure.ac: Likewise.
2032 * disassemble.c: Likewise.
2033 * disassemble.h: Likewise.
2034 * Makefile.in: Regenerate.
2035 * configure: Regenerate.
2036 * po/POTFILES.in: Regenerate.
2038 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2041 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2043 (print_insn): Clear vex instead of vex.evex.
2045 2018-04-04 Nick Clifton <nickc@redhat.com>
2047 * po/es.po: Updated Spanish translation.
2049 2018-03-28 Jan Beulich <jbeulich@suse.com>
2051 * i386-gen.c (opcode_modifiers): Delete VecESize.
2052 * i386-opc.h (VecESize): Delete.
2053 (struct i386_opcode_modifier): Delete vecesize.
2054 * i386-opc.tbl: Drop VecESize.
2055 * i386-tlb.h: Re-generate.
2057 2018-03-28 Jan Beulich <jbeulich@suse.com>
2059 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2060 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2061 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2062 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2063 * i386-tlb.h: Re-generate.
2065 2018-03-28 Jan Beulich <jbeulich@suse.com>
2067 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2069 * i386-tlb.h: Re-generate.
2071 2018-03-28 Jan Beulich <jbeulich@suse.com>
2073 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2074 (vex_len_table): Drop Y for vcvt*2si.
2075 (putop): Replace plain 'Y' handling by abort().
2077 2018-03-28 Nick Clifton <nickc@redhat.com>
2080 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2081 instructions with only a base address register.
2082 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2083 handle AARHC64_OPND_SVE_ADDR_R.
2084 (aarch64_print_operand): Likewise.
2085 * aarch64-asm-2.c: Regenerate.
2086 * aarch64_dis-2.c: Regenerate.
2087 * aarch64-opc-2.c: Regenerate.
2089 2018-03-22 Jan Beulich <jbeulich@suse.com>
2091 * i386-opc.tbl: Drop VecESize from register only insn forms and
2092 memory forms not allowing broadcast.
2093 * i386-tlb.h: Re-generate.
2095 2018-03-22 Jan Beulich <jbeulich@suse.com>
2097 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2098 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2099 sha256*): Drop Disp<N>.
2101 2018-03-22 Jan Beulich <jbeulich@suse.com>
2103 * i386-dis.c (EbndS, bnd_swap_mode): New.
2104 (prefix_table): Use EbndS.
2105 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2106 * i386-opc.tbl (bndmov): Move misplaced Load.
2107 * i386-tlb.h: Re-generate.
2109 2018-03-22 Jan Beulich <jbeulich@suse.com>
2111 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2112 templates allowing memory operands and folded ones for register
2114 * i386-tlb.h: Re-generate.
2116 2018-03-22 Jan Beulich <jbeulich@suse.com>
2118 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2119 256-bit templates. Drop redundant leftover Disp<N>.
2120 * i386-tlb.h: Re-generate.
2122 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
2124 * riscv-opc.c (riscv_insn_types): New.
2126 2018-03-13 Nick Clifton <nickc@redhat.com>
2128 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2130 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2132 * i386-opc.tbl: Add Optimize to clr.
2133 * i386-tbl.h: Regenerated.
2135 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2137 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2138 * i386-opc.h (OldGcc): Removed.
2139 (i386_opcode_modifier): Remove oldgcc.
2140 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2141 instructions for old (<= 2.8.1) versions of gcc.
2142 * i386-tbl.h: Regenerated.
2144 2018-03-08 Jan Beulich <jbeulich@suse.com>
2146 * i386-opc.h (EVEXDYN): New.
2147 * i386-opc.tbl: Fold various AVX512VL templates.
2148 * i386-tlb.h: Re-generate.
2150 2018-03-08 Jan Beulich <jbeulich@suse.com>
2152 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2153 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2154 vpexpandd, vpexpandq): Fold AFX512VF templates.
2155 * i386-tlb.h: Re-generate.
2157 2018-03-08 Jan Beulich <jbeulich@suse.com>
2159 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2160 Fold 128- and 256-bit VEX-encoded templates.
2161 * i386-tlb.h: Re-generate.
2163 2018-03-08 Jan Beulich <jbeulich@suse.com>
2165 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2166 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2167 vpexpandd, vpexpandq): Fold AVX512F templates.
2168 * i386-tlb.h: Re-generate.
2170 2018-03-08 Jan Beulich <jbeulich@suse.com>
2172 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2173 64-bit templates. Drop Disp<N>.
2174 * i386-tlb.h: Re-generate.
2176 2018-03-08 Jan Beulich <jbeulich@suse.com>
2178 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2179 and 256-bit templates.
2180 * i386-tlb.h: Re-generate.
2182 2018-03-08 Jan Beulich <jbeulich@suse.com>
2184 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2185 * i386-tlb.h: Re-generate.
2187 2018-03-08 Jan Beulich <jbeulich@suse.com>
2189 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2191 * i386-tlb.h: Re-generate.
2193 2018-03-08 Jan Beulich <jbeulich@suse.com>
2195 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2196 * i386-tlb.h: Re-generate.
2198 2018-03-08 Jan Beulich <jbeulich@suse.com>
2200 * i386-gen.c (opcode_modifiers): Delete FloatD.
2201 * i386-opc.h (FloatD): Delete.
2202 (struct i386_opcode_modifier): Delete floatd.
2203 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2205 * i386-tlb.h: Re-generate.
2207 2018-03-08 Jan Beulich <jbeulich@suse.com>
2209 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2211 2018-03-08 Jan Beulich <jbeulich@suse.com>
2213 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2214 * i386-tlb.h: Re-generate.
2216 2018-03-08 Jan Beulich <jbeulich@suse.com>
2218 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2220 * i386-tlb.h: Re-generate.
2222 2018-03-07 Alan Modra <amodra@gmail.com>
2224 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2226 * disassemble.h (print_insn_rs6000): Delete.
2227 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2228 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2229 (print_insn_rs6000): Delete.
2231 2018-03-03 Alan Modra <amodra@gmail.com>
2233 * sysdep.h (opcodes_error_handler): Define.
2234 (_bfd_error_handler): Declare.
2235 * Makefile.am: Remove stray #.
2236 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2238 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2239 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2240 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2241 opcodes_error_handler to print errors. Standardize error messages.
2242 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2243 and include opintl.h.
2244 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2245 * i386-gen.c: Standardize error messages.
2246 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2247 * Makefile.in: Regenerate.
2248 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2249 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2250 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2251 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2252 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2253 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2254 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2255 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2256 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2257 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2258 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2259 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2260 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2262 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2264 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2265 vpsub[bwdq] instructions.
2266 * i386-tbl.h: Regenerated.
2268 2018-03-01 Alan Modra <amodra@gmail.com>
2270 * configure.ac (ALL_LINGUAS): Sort.
2271 * configure: Regenerate.
2273 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2275 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2276 macro by assignements.
2278 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2281 * i386-gen.c (opcode_modifiers): Add Optimize.
2282 * i386-opc.h (Optimize): New enum.
2283 (i386_opcode_modifier): Add optimize.
2284 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2285 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2286 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2287 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2288 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2290 * i386-tbl.h: Regenerated.
2292 2018-02-26 Alan Modra <amodra@gmail.com>
2294 * crx-dis.c (getregliststring): Allocate a large enough buffer
2295 to silence false positive gcc8 warning.
2297 2018-02-22 Shea Levy <shea@shealevy.com>
2299 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2301 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2303 * i386-opc.tbl: Add {rex},
2304 * i386-tbl.h: Regenerated.
2306 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2308 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2309 (mips16_opcodes): Replace `M' with `m' for "restore".
2311 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2313 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2315 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2317 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2318 variable to `function_index'.
2320 2018-02-13 Nick Clifton <nickc@redhat.com>
2323 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2324 about truncation of printing.
2326 2018-02-12 Henry Wong <henry@stuffedcow.net>
2328 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2330 2018-02-05 Nick Clifton <nickc@redhat.com>
2332 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2334 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2336 * i386-dis.c (enum): Add pconfig.
2337 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2338 (cpu_flags): Add CpuPCONFIG.
2339 * i386-opc.h (enum): Add CpuPCONFIG.
2340 (i386_cpu_flags): Add cpupconfig.
2341 * i386-opc.tbl: Add PCONFIG instruction.
2342 * i386-init.h: Regenerate.
2343 * i386-tbl.h: Likewise.
2345 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2347 * i386-dis.c (enum): Add PREFIX_0F09.
2348 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2349 (cpu_flags): Add CpuWBNOINVD.
2350 * i386-opc.h (enum): Add CpuWBNOINVD.
2351 (i386_cpu_flags): Add cpuwbnoinvd.
2352 * i386-opc.tbl: Add WBNOINVD instruction.
2353 * i386-init.h: Regenerate.
2354 * i386-tbl.h: Likewise.
2356 2018-01-17 Jim Wilson <jimw@sifive.com>
2358 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2360 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2362 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2363 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2364 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2365 (cpu_flags): Add CpuIBT, CpuSHSTK.
2366 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2367 (i386_cpu_flags): Add cpuibt, cpushstk.
2368 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2369 * i386-init.h: Regenerate.
2370 * i386-tbl.h: Likewise.
2372 2018-01-16 Nick Clifton <nickc@redhat.com>
2374 * po/pt_BR.po: Updated Brazilian Portugese translation.
2375 * po/de.po: Updated German translation.
2377 2018-01-15 Jim Wilson <jimw@sifive.com>
2379 * riscv-opc.c (match_c_nop): New.
2380 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2382 2018-01-15 Nick Clifton <nickc@redhat.com>
2384 * po/uk.po: Updated Ukranian translation.
2386 2018-01-13 Nick Clifton <nickc@redhat.com>
2388 * po/opcodes.pot: Regenerated.
2390 2018-01-13 Nick Clifton <nickc@redhat.com>
2392 * configure: Regenerate.
2394 2018-01-13 Nick Clifton <nickc@redhat.com>
2396 2.30 branch created.
2398 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2400 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2401 * i386-tbl.h: Regenerate.
2403 2018-01-10 Jan Beulich <jbeulich@suse.com>
2405 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2406 * i386-tbl.h: Re-generate.
2408 2018-01-10 Jan Beulich <jbeulich@suse.com>
2410 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2411 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2412 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2413 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2414 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2415 Disp8MemShift of AVX512VL forms.
2416 * i386-tbl.h: Re-generate.
2418 2018-01-09 Jim Wilson <jimw@sifive.com>
2420 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2421 then the hi_addr value is zero.
2423 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2425 * arm-dis.c (arm_opcodes): Add csdb.
2426 (thumb32_opcodes): Add csdb.
2428 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2430 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2431 * aarch64-asm-2.c: Regenerate.
2432 * aarch64-dis-2.c: Regenerate.
2433 * aarch64-opc-2.c: Regenerate.
2435 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2438 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2439 Remove AVX512 vmovd with 64-bit operands.
2440 * i386-tbl.h: Regenerated.
2442 2018-01-05 Jim Wilson <jimw@sifive.com>
2444 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2447 2018-01-03 Alan Modra <amodra@gmail.com>
2449 Update year range in copyright notice of all files.
2451 2018-01-02 Jan Beulich <jbeulich@suse.com>
2453 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2454 and OPERAND_TYPE_REGZMM entries.
2456 For older changes see ChangeLog-2017
2458 Copyright (C) 2018 Free Software Foundation, Inc.
2460 Copying and distribution of this file, with or without modification,
2461 are permitted in any medium without royalty provided the copyright
2462 notice and this notice are preserved.
2468 version-control: never