1 2018-07-12 Tamar Christina <tamar.christina@arm.com>
4 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
5 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
6 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
7 sqdmulh, sqrdmulh): Use Em16.
9 2018-07-11 Sudakshina Das <sudi.das@arm.com>
11 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
12 csdb together with them.
13 (thumb32_opcodes): Likewise.
15 2018-07-11 Jan Beulich <jbeulich@suse.com>
17 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
18 requiring 32-bit registers as operands 2 and 3. Improve
20 (mwait, mwaitx): Fold templates. Improve comments.
21 OPERAND_TYPE_INOUTPORTREG.
22 * i386-tbl.h: Re-generate.
24 2018-07-11 Jan Beulich <jbeulich@suse.com>
26 * i386-gen.c (operand_type_init): Remove
27 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
28 OPERAND_TYPE_INOUTPORTREG.
29 * i386-init.h: Re-generate.
31 2018-07-11 Jan Beulich <jbeulich@suse.com>
33 * i386-opc.tbl (wrssd, wrussd): Add Dword.
34 (wrssq, wrussq): Add Qword.
35 * i386-tbl.h: Re-generate.
37 2018-07-11 Jan Beulich <jbeulich@suse.com>
39 * i386-opc.h: Rename OTMax to OTNum.
40 (OTNumOfUints): Adjust calculation.
41 (OTUnused): Directly alias to OTNum.
43 2018-07-09 Maciej W. Rozycki <macro@mips.com>
45 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
47 (lea_reg_xys): Likewise.
48 (print_insn_loop_primitive): Rename `reg' local variable to
51 2018-07-06 Tamar Christina <tamar.christina@arm.com>
54 * aarch64-tbl.h (ldarh): Fix disassembly mask.
56 2018-07-06 Tamar Christina <tamar.christina@arm.com>
59 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
60 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
62 2018-07-02 Maciej W. Rozycki <macro@mips.com>
65 * mips-dis.c (mips_option_arg_t): New enumeration.
66 (mips_options): New variable.
67 (disassembler_options_mips): New function.
68 (print_mips_disassembler_options): Reimplement in terms of
69 `disassembler_options_mips'.
70 * arm-dis.c (disassembler_options_arm): Adapt to using the
71 `disasm_options_and_args_t' structure.
72 * ppc-dis.c (disassembler_options_powerpc): Likewise.
73 * s390-dis.c (disassembler_options_s390): Likewise.
75 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
77 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
79 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
80 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
81 * testsuite/ld-arm/tls-longplt.d: Likewise.
83 2018-06-29 Tamar Christina <tamar.christina@arm.com>
86 * aarch64-asm-2.c: Regenerate.
87 * aarch64-dis-2.c: Likewise.
88 * aarch64-opc-2.c: Likewise.
89 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
90 * aarch64-opc.c (operand_general_constraint_met_p,
91 aarch64_print_operand): Likewise.
92 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
93 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
95 (AARCH64_OPERANDS): Add Em2.
97 2018-06-26 Nick Clifton <nickc@redhat.com>
99 * po/uk.po: Updated Ukranian translation.
100 * po/de.po: Updated German translation.
101 * po/pt_BR.po: Updated Brazilian Portuguese translation.
103 2018-06-26 Nick Clifton <nickc@redhat.com>
105 * nfp-dis.c: Fix spelling mistake.
107 2018-06-24 Nick Clifton <nickc@redhat.com>
109 * configure: Regenerate.
110 * po/opcodes.pot: Regenerate.
112 2018-06-24 Nick Clifton <nickc@redhat.com>
116 2018-06-19 Tamar Christina <tamar.christina@arm.com>
118 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
119 * aarch64-asm-2.c: Regenerate.
120 * aarch64-dis-2.c: Likewise.
122 2018-06-21 Maciej W. Rozycki <macro@mips.com>
124 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
125 `-M ginv' option description.
127 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
130 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
133 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
135 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
136 * configure.ac: Remove AC_PREREQ.
137 * Makefile.in: Re-generate.
138 * aclocal.m4: Re-generate.
139 * configure: Re-generate.
141 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
143 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
144 mips64r6 descriptors.
145 (parse_mips_ase_option): Handle -Mginv option.
146 (print_mips_disassembler_options): Document -Mginv.
147 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
149 (mips_opcodes): Define ginvi and ginvt.
151 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
152 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
154 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
155 * mips-opc.c (CRC, CRC64): New macros.
156 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
157 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
160 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
163 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
164 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
166 2018-06-06 Alan Modra <amodra@gmail.com>
168 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
169 setjmp. Move init for some other vars later too.
171 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
173 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
174 (dis_private): Add new fields for property section tracking.
175 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
176 (xtensa_instruction_fits): New functions.
177 (fetch_data): Bump minimal fetch size to 4.
178 (print_insn_xtensa): Make struct dis_private static.
179 Load and prepare property table on section change.
180 Don't disassemble literals. Don't disassemble instructions that
181 cross property table boundaries.
183 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
185 * configure: Regenerated.
187 2018-06-01 Jan Beulich <jbeulich@suse.com>
189 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
190 * i386-tbl.h: Re-generate.
192 2018-06-01 Jan Beulich <jbeulich@suse.com>
194 * i386-opc.tbl (sldt, str): Add NoRex64.
195 * i386-tbl.h: Re-generate.
197 2018-06-01 Jan Beulich <jbeulich@suse.com>
199 * i386-opc.tbl (invpcid): Add Oword.
200 * i386-tbl.h: Re-generate.
202 2018-06-01 Alan Modra <amodra@gmail.com>
204 * sysdep.h (_bfd_error_handler): Don't declare.
205 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
206 * rl78-decode.opc: Likewise.
207 * msp430-decode.c: Regenerate.
208 * rl78-decode.c: Regenerate.
210 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
212 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
213 * i386-init.h : Regenerated.
215 2018-05-25 Alan Modra <amodra@gmail.com>
217 * Makefile.in: Regenerate.
218 * po/POTFILES.in: Regenerate.
220 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
222 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
223 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
224 (insert_bab, extract_bab, insert_btab, extract_btab,
225 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
226 (BAT, BBA VBA RBS XB6S): Delete macros.
227 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
228 (BB, BD, RBX, XC6): Update for new macros.
229 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
230 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
231 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
232 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
234 2018-05-18 John Darrington <john@darrington.wattle.id.au>
236 * Makefile.am: Add support for s12z architecture.
237 * configure.ac: Likewise.
238 * disassemble.c: Likewise.
239 * disassemble.h: Likewise.
240 * Makefile.in: Regenerate.
241 * configure: Regenerate.
242 * s12z-dis.c: New file.
245 2018-05-18 Alan Modra <amodra@gmail.com>
247 * nfp-dis.c: Don't #include libbfd.h.
248 (init_nfp3200_priv): Use bfd_get_section_contents.
249 (nit_nfp6000_mecsr_sec): Likewise.
251 2018-05-17 Nick Clifton <nickc@redhat.com>
253 * po/zh_CN.po: Updated simplified Chinese translation.
255 2018-05-16 Tamar Christina <tamar.christina@arm.com>
258 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
259 * aarch64-dis-2.c: Regenerate.
261 2018-05-15 Tamar Christina <tamar.christina@arm.com>
264 * aarch64-asm.c (opintl.h): Include.
265 (aarch64_ins_sysreg): Enforce read/write constraints.
266 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
267 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
268 (F_REG_READ, F_REG_WRITE): New.
269 * aarch64-opc.c (aarch64_print_operand): Generate notes for
271 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
272 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
273 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
274 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
275 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
276 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
277 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
278 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
279 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
280 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
281 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
282 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
283 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
284 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
285 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
286 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
287 msr (F_SYS_WRITE), mrs (F_SYS_READ).
289 2018-05-15 Tamar Christina <tamar.christina@arm.com>
292 * aarch64-dis.c (no_notes: New.
293 (parse_aarch64_dis_option): Support notes.
294 (aarch64_decode_insn, print_operands): Likewise.
295 (print_aarch64_disassembler_options): Document notes.
296 * aarch64-opc.c (aarch64_print_operand): Support notes.
298 2018-05-15 Tamar Christina <tamar.christina@arm.com>
301 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
302 and take error struct.
303 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
304 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
305 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
306 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
307 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
308 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
309 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
310 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
311 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
312 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
313 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
314 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
315 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
316 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
317 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
318 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
319 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
320 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
321 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
322 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
323 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
324 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
325 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
326 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
327 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
328 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
329 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
330 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
331 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
332 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
333 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
334 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
335 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
336 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
337 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
338 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
339 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
340 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
341 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
342 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
343 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
344 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
345 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
346 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
347 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
348 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
349 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
350 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
351 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
352 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
353 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
354 (determine_disassembling_preference, aarch64_decode_insn,
355 print_insn_aarch64_word, print_insn_data): Take errors struct.
356 (print_insn_aarch64): Use errors.
357 * aarch64-asm-2.c: Regenerate.
358 * aarch64-dis-2.c: Regenerate.
359 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
360 boolean in aarch64_insert_operan.
361 (print_operand_extractor): Likewise.
362 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
364 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
366 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
368 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
370 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
372 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
374 * cr16-opc.c (cr16_instruction): Comment typo fix.
375 * hppa-dis.c (print_insn_hppa): Likewise.
377 2018-05-08 Jim Wilson <jimw@sifive.com>
379 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
380 (match_c_slli64, match_srxi_as_c_srxi): New.
381 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
382 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
383 <c.slli, c.srli, c.srai>: Use match_s_slli.
384 <c.slli64, c.srli64, c.srai64>: New.
386 2018-05-08 Alan Modra <amodra@gmail.com>
388 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
389 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
390 partition opcode space for index lookup.
392 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
394 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
395 <insn_length>: ...with this. Update usage.
396 Remove duplicate call to *info->memory_error_func.
398 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
399 H.J. Lu <hongjiu.lu@intel.com>
401 * i386-dis.c (Gva): New.
402 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
403 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
404 (prefix_table): New instructions (see prefix above).
405 (mod_table): New instructions (see prefix above).
406 (OP_G): Handle va_mode.
407 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
409 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
410 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
411 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
412 * i386-opc.tbl: Add movidir{i,64b}.
413 * i386-init.h: Regenerated.
414 * i386-tbl.h: Likewise.
416 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
420 * i386-opc.h (AddrPrefixOp0): Renamed to ...
421 (AddrPrefixOpReg): This.
422 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
423 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
425 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
427 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
428 (vle_num_opcodes): Likewise.
429 (spe2_num_opcodes): Likewise.
430 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
432 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
433 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
436 2018-05-01 Tamar Christina <tamar.christina@arm.com>
438 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
440 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
442 Makefile.am: Added nfp-dis.c.
443 configure.ac: Added bfd_nfp_arch.
444 disassemble.h: Added print_insn_nfp prototype.
445 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
446 nfp-dis.c: New, for NFP support.
447 po/POTFILES.in: Added nfp-dis.c to the list.
448 Makefile.in: Regenerate.
449 configure: Regenerate.
451 2018-04-26 Jan Beulich <jbeulich@suse.com>
453 * i386-opc.tbl: Fold various non-memory operand AVX512VL
454 templates into their base ones.
455 * i386-tlb.h: Re-generate.
457 2018-04-26 Jan Beulich <jbeulich@suse.com>
459 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
460 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
461 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
462 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
463 * i386-init.h: Re-generate.
465 2018-04-26 Jan Beulich <jbeulich@suse.com>
467 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
468 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
469 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
470 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
472 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
474 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
476 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
477 cpuregzmm, and cpuregmask.
478 * i386-init.h: Re-generate.
479 * i386-tbl.h: Re-generate.
481 2018-04-26 Jan Beulich <jbeulich@suse.com>
483 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
484 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
485 * i386-init.h: Re-generate.
487 2018-04-26 Jan Beulich <jbeulich@suse.com>
489 * i386-gen.c (VexImmExt): Delete.
490 * i386-opc.h (VexImmExt, veximmext): Delete.
491 * i386-opc.tbl: Drop all VexImmExt uses.
492 * i386-tlb.h: Re-generate.
494 2018-04-25 Jan Beulich <jbeulich@suse.com>
496 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
498 * i386-tlb.h: Re-generate.
500 2018-04-25 Tamar Christina <tamar.christina@arm.com>
502 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
504 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
506 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
508 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
509 (cpu_flags): Add CpuCLDEMOTE.
510 * i386-init.h: Regenerate.
511 * i386-opc.h (enum): Add CpuCLDEMOTE,
512 (i386_cpu_flags): Add cpucldemote.
513 * i386-opc.tbl: Add cldemote.
514 * i386-tbl.h: Regenerate.
516 2018-04-16 Alan Modra <amodra@gmail.com>
518 * Makefile.am: Remove sh5 and sh64 support.
519 * configure.ac: Likewise.
520 * disassemble.c: Likewise.
521 * disassemble.h: Likewise.
522 * sh-dis.c: Likewise.
523 * sh64-dis.c: Delete.
524 * sh64-opc.c: Delete.
525 * sh64-opc.h: Delete.
526 * Makefile.in: Regenerate.
527 * configure: Regenerate.
528 * po/POTFILES.in: Regenerate.
530 2018-04-16 Alan Modra <amodra@gmail.com>
532 * Makefile.am: Remove w65 support.
533 * configure.ac: Likewise.
534 * disassemble.c: Likewise.
535 * disassemble.h: Likewise.
538 * Makefile.in: Regenerate.
539 * configure: Regenerate.
540 * po/POTFILES.in: Regenerate.
542 2018-04-16 Alan Modra <amodra@gmail.com>
544 * configure.ac: Remove we32k support.
545 * configure: Regenerate.
547 2018-04-16 Alan Modra <amodra@gmail.com>
549 * Makefile.am: Remove m88k support.
550 * configure.ac: Likewise.
551 * disassemble.c: Likewise.
552 * disassemble.h: Likewise.
553 * m88k-dis.c: Delete.
554 * Makefile.in: Regenerate.
555 * configure: Regenerate.
556 * po/POTFILES.in: Regenerate.
558 2018-04-16 Alan Modra <amodra@gmail.com>
560 * Makefile.am: Remove i370 support.
561 * configure.ac: Likewise.
562 * disassemble.c: Likewise.
563 * disassemble.h: Likewise.
564 * i370-dis.c: Delete.
565 * i370-opc.c: Delete.
566 * Makefile.in: Regenerate.
567 * configure: Regenerate.
568 * po/POTFILES.in: Regenerate.
570 2018-04-16 Alan Modra <amodra@gmail.com>
572 * Makefile.am: Remove h8500 support.
573 * configure.ac: Likewise.
574 * disassemble.c: Likewise.
575 * disassemble.h: Likewise.
576 * h8500-dis.c: Delete.
577 * h8500-opc.h: Delete.
578 * Makefile.in: Regenerate.
579 * configure: Regenerate.
580 * po/POTFILES.in: Regenerate.
582 2018-04-16 Alan Modra <amodra@gmail.com>
584 * configure.ac: Remove tahoe support.
585 * configure: Regenerate.
587 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
589 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
591 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
593 * i386-tbl.h: Regenerated.
595 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
597 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
598 PREFIX_MOD_1_0FAE_REG_6.
600 (OP_E_register): Use va_mode.
601 * i386-dis-evex.h (prefix_table):
602 New instructions (see prefixes above).
603 * i386-gen.c (cpu_flag_init): Add WAITPKG.
604 (cpu_flags): Likewise.
605 * i386-opc.h (enum): Likewise.
606 (i386_cpu_flags): Likewise.
607 * i386-opc.tbl: Add umonitor, umwait, tpause.
608 * i386-init.h: Regenerate.
609 * i386-tbl.h: Likewise.
611 2018-04-11 Alan Modra <amodra@gmail.com>
613 * opcodes/i860-dis.c: Delete.
614 * opcodes/i960-dis.c: Delete.
615 * Makefile.am: Remove i860 and i960 support.
616 * configure.ac: Likewise.
617 * disassemble.c: Likewise.
618 * disassemble.h: Likewise.
619 * Makefile.in: Regenerate.
620 * configure: Regenerate.
621 * po/POTFILES.in: Regenerate.
623 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
628 (print_insn): Clear vex instead of vex.evex.
630 2018-04-04 Nick Clifton <nickc@redhat.com>
632 * po/es.po: Updated Spanish translation.
634 2018-03-28 Jan Beulich <jbeulich@suse.com>
636 * i386-gen.c (opcode_modifiers): Delete VecESize.
637 * i386-opc.h (VecESize): Delete.
638 (struct i386_opcode_modifier): Delete vecesize.
639 * i386-opc.tbl: Drop VecESize.
640 * i386-tlb.h: Re-generate.
642 2018-03-28 Jan Beulich <jbeulich@suse.com>
644 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
645 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
646 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
647 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
648 * i386-tlb.h: Re-generate.
650 2018-03-28 Jan Beulich <jbeulich@suse.com>
652 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
654 * i386-tlb.h: Re-generate.
656 2018-03-28 Jan Beulich <jbeulich@suse.com>
658 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
659 (vex_len_table): Drop Y for vcvt*2si.
660 (putop): Replace plain 'Y' handling by abort().
662 2018-03-28 Nick Clifton <nickc@redhat.com>
665 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
666 instructions with only a base address register.
667 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
668 handle AARHC64_OPND_SVE_ADDR_R.
669 (aarch64_print_operand): Likewise.
670 * aarch64-asm-2.c: Regenerate.
671 * aarch64_dis-2.c: Regenerate.
672 * aarch64-opc-2.c: Regenerate.
674 2018-03-22 Jan Beulich <jbeulich@suse.com>
676 * i386-opc.tbl: Drop VecESize from register only insn forms and
677 memory forms not allowing broadcast.
678 * i386-tlb.h: Re-generate.
680 2018-03-22 Jan Beulich <jbeulich@suse.com>
682 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
683 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
684 sha256*): Drop Disp<N>.
686 2018-03-22 Jan Beulich <jbeulich@suse.com>
688 * i386-dis.c (EbndS, bnd_swap_mode): New.
689 (prefix_table): Use EbndS.
690 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
691 * i386-opc.tbl (bndmov): Move misplaced Load.
692 * i386-tlb.h: Re-generate.
694 2018-03-22 Jan Beulich <jbeulich@suse.com>
696 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
697 templates allowing memory operands and folded ones for register
699 * i386-tlb.h: Re-generate.
701 2018-03-22 Jan Beulich <jbeulich@suse.com>
703 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
704 256-bit templates. Drop redundant leftover Disp<N>.
705 * i386-tlb.h: Re-generate.
707 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
709 * riscv-opc.c (riscv_insn_types): New.
711 2018-03-13 Nick Clifton <nickc@redhat.com>
713 * po/pt_BR.po: Updated Brazilian Portuguese translation.
715 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
717 * i386-opc.tbl: Add Optimize to clr.
718 * i386-tbl.h: Regenerated.
720 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
722 * i386-gen.c (opcode_modifiers): Remove OldGcc.
723 * i386-opc.h (OldGcc): Removed.
724 (i386_opcode_modifier): Remove oldgcc.
725 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
726 instructions for old (<= 2.8.1) versions of gcc.
727 * i386-tbl.h: Regenerated.
729 2018-03-08 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.h (EVEXDYN): New.
732 * i386-opc.tbl: Fold various AVX512VL templates.
733 * i386-tlb.h: Re-generate.
735 2018-03-08 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
738 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
739 vpexpandd, vpexpandq): Fold AFX512VF templates.
740 * i386-tlb.h: Re-generate.
742 2018-03-08 Jan Beulich <jbeulich@suse.com>
744 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
745 Fold 128- and 256-bit VEX-encoded templates.
746 * i386-tlb.h: Re-generate.
748 2018-03-08 Jan Beulich <jbeulich@suse.com>
750 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
751 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
752 vpexpandd, vpexpandq): Fold AVX512F templates.
753 * i386-tlb.h: Re-generate.
755 2018-03-08 Jan Beulich <jbeulich@suse.com>
757 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
758 64-bit templates. Drop Disp<N>.
759 * i386-tlb.h: Re-generate.
761 2018-03-08 Jan Beulich <jbeulich@suse.com>
763 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
764 and 256-bit templates.
765 * i386-tlb.h: Re-generate.
767 2018-03-08 Jan Beulich <jbeulich@suse.com>
769 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
770 * i386-tlb.h: Re-generate.
772 2018-03-08 Jan Beulich <jbeulich@suse.com>
774 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
776 * i386-tlb.h: Re-generate.
778 2018-03-08 Jan Beulich <jbeulich@suse.com>
780 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
781 * i386-tlb.h: Re-generate.
783 2018-03-08 Jan Beulich <jbeulich@suse.com>
785 * i386-gen.c (opcode_modifiers): Delete FloatD.
786 * i386-opc.h (FloatD): Delete.
787 (struct i386_opcode_modifier): Delete floatd.
788 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
790 * i386-tlb.h: Re-generate.
792 2018-03-08 Jan Beulich <jbeulich@suse.com>
794 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
796 2018-03-08 Jan Beulich <jbeulich@suse.com>
798 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
799 * i386-tlb.h: Re-generate.
801 2018-03-08 Jan Beulich <jbeulich@suse.com>
803 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
805 * i386-tlb.h: Re-generate.
807 2018-03-07 Alan Modra <amodra@gmail.com>
809 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
811 * disassemble.h (print_insn_rs6000): Delete.
812 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
813 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
814 (print_insn_rs6000): Delete.
816 2018-03-03 Alan Modra <amodra@gmail.com>
818 * sysdep.h (opcodes_error_handler): Define.
819 (_bfd_error_handler): Declare.
820 * Makefile.am: Remove stray #.
821 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
823 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
824 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
825 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
826 opcodes_error_handler to print errors. Standardize error messages.
827 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
828 and include opintl.h.
829 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
830 * i386-gen.c: Standardize error messages.
831 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
832 * Makefile.in: Regenerate.
833 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
834 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
835 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
836 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
837 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
838 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
839 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
840 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
841 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
842 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
843 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
844 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
845 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
847 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
849 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
850 vpsub[bwdq] instructions.
851 * i386-tbl.h: Regenerated.
853 2018-03-01 Alan Modra <amodra@gmail.com>
855 * configure.ac (ALL_LINGUAS): Sort.
856 * configure: Regenerate.
858 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
860 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
861 macro by assignements.
863 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
866 * i386-gen.c (opcode_modifiers): Add Optimize.
867 * i386-opc.h (Optimize): New enum.
868 (i386_opcode_modifier): Add optimize.
869 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
870 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
871 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
872 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
873 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
875 * i386-tbl.h: Regenerated.
877 2018-02-26 Alan Modra <amodra@gmail.com>
879 * crx-dis.c (getregliststring): Allocate a large enough buffer
880 to silence false positive gcc8 warning.
882 2018-02-22 Shea Levy <shea@shealevy.com>
884 * disassemble.c (ARCH_riscv): Define if ARCH_all.
886 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
888 * i386-opc.tbl: Add {rex},
889 * i386-tbl.h: Regenerated.
891 2018-02-20 Maciej W. Rozycki <macro@mips.com>
893 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
894 (mips16_opcodes): Replace `M' with `m' for "restore".
896 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
898 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
900 2018-02-13 Maciej W. Rozycki <macro@mips.com>
902 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
903 variable to `function_index'.
905 2018-02-13 Nick Clifton <nickc@redhat.com>
908 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
909 about truncation of printing.
911 2018-02-12 Henry Wong <henry@stuffedcow.net>
913 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
915 2018-02-05 Nick Clifton <nickc@redhat.com>
917 * po/pt_BR.po: Updated Brazilian Portuguese translation.
919 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
921 * i386-dis.c (enum): Add pconfig.
922 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
923 (cpu_flags): Add CpuPCONFIG.
924 * i386-opc.h (enum): Add CpuPCONFIG.
925 (i386_cpu_flags): Add cpupconfig.
926 * i386-opc.tbl: Add PCONFIG instruction.
927 * i386-init.h: Regenerate.
928 * i386-tbl.h: Likewise.
930 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
932 * i386-dis.c (enum): Add PREFIX_0F09.
933 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
934 (cpu_flags): Add CpuWBNOINVD.
935 * i386-opc.h (enum): Add CpuWBNOINVD.
936 (i386_cpu_flags): Add cpuwbnoinvd.
937 * i386-opc.tbl: Add WBNOINVD instruction.
938 * i386-init.h: Regenerate.
939 * i386-tbl.h: Likewise.
941 2018-01-17 Jim Wilson <jimw@sifive.com>
943 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
945 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
947 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
948 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
949 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
950 (cpu_flags): Add CpuIBT, CpuSHSTK.
951 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
952 (i386_cpu_flags): Add cpuibt, cpushstk.
953 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
954 * i386-init.h: Regenerate.
955 * i386-tbl.h: Likewise.
957 2018-01-16 Nick Clifton <nickc@redhat.com>
959 * po/pt_BR.po: Updated Brazilian Portugese translation.
960 * po/de.po: Updated German translation.
962 2018-01-15 Jim Wilson <jimw@sifive.com>
964 * riscv-opc.c (match_c_nop): New.
965 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
967 2018-01-15 Nick Clifton <nickc@redhat.com>
969 * po/uk.po: Updated Ukranian translation.
971 2018-01-13 Nick Clifton <nickc@redhat.com>
973 * po/opcodes.pot: Regenerated.
975 2018-01-13 Nick Clifton <nickc@redhat.com>
977 * configure: Regenerate.
979 2018-01-13 Nick Clifton <nickc@redhat.com>
983 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
985 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
986 * i386-tbl.h: Regenerate.
988 2018-01-10 Jan Beulich <jbeulich@suse.com>
990 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
991 * i386-tbl.h: Re-generate.
993 2018-01-10 Jan Beulich <jbeulich@suse.com>
995 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
996 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
997 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
998 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
999 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1000 Disp8MemShift of AVX512VL forms.
1001 * i386-tbl.h: Re-generate.
1003 2018-01-09 Jim Wilson <jimw@sifive.com>
1005 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1006 then the hi_addr value is zero.
1008 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1010 * arm-dis.c (arm_opcodes): Add csdb.
1011 (thumb32_opcodes): Add csdb.
1013 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1015 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1016 * aarch64-asm-2.c: Regenerate.
1017 * aarch64-dis-2.c: Regenerate.
1018 * aarch64-opc-2.c: Regenerate.
1020 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1023 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1024 Remove AVX512 vmovd with 64-bit operands.
1025 * i386-tbl.h: Regenerated.
1027 2018-01-05 Jim Wilson <jimw@sifive.com>
1029 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1032 2018-01-03 Alan Modra <amodra@gmail.com>
1034 Update year range in copyright notice of all files.
1036 2018-01-02 Jan Beulich <jbeulich@suse.com>
1038 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1039 and OPERAND_TYPE_REGZMM entries.
1041 For older changes see ChangeLog-2017
1043 Copyright (C) 2018 Free Software Foundation, Inc.
1045 Copying and distribution of this file, with or without modification,
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