1 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
4 sve_size_13 icode to account for variant behaviour of
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
8 sve_size_13 icode to account for variant behaviour of
10 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
11 (OP_SVE_VVV_Q_D): Add new qualifier.
12 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
13 (struct aarch64_opcode): Split pmull{t,b} into those requiring
16 2019-07-01 Jan Beulich <jbeulich@suse.com>
18 * opcodes/i386-gen.c (operand_type_init): Remove
19 OPERAND_TYPE_VEC_IMM4 entry.
20 (operand_types): Remove Vec_Imm4.
21 * opcodes/i386-opc.h (Vec_Imm4): Delete.
22 (union i386_operand_type): Remove vec_imm4.
23 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
24 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
26 2019-07-01 Jan Beulich <jbeulich@suse.com>
28 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
29 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
30 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
31 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
32 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
33 monitorx, mwaitx): Drop ImmExt from operand-less forms.
34 * i386-tbl.h: Re-generate.
36 2019-07-01 Jan Beulich <jbeulich@suse.com>
38 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
40 * i386-tbl.h: Re-generate.
42 2019-07-01 Jan Beulich <jbeulich@suse.com>
44 * i386-opc.tbl (C): New.
45 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
46 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
47 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
48 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
49 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
50 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
51 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
52 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
53 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
54 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
55 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
56 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
57 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
58 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
59 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
60 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
61 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
62 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
63 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
64 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
65 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
66 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
67 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
68 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
69 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
70 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
72 * i386-tbl.h: Re-generate.
74 2019-07-01 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
78 * i386-tbl.h: Re-generate.
80 2019-07-01 Jan Beulich <jbeulich@suse.com>
82 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
83 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
84 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
85 * i386-tbl.h: Re-generate.
87 2019-07-01 Jan Beulich <jbeulich@suse.com>
89 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
90 Disp8MemShift from register only templates.
91 * i386-tbl.h: Re-generate.
93 2019-07-01 Jan Beulich <jbeulich@suse.com>
95 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
96 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
97 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
98 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
99 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
100 EVEX_W_0F11_P_3_M_1): Delete.
101 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
102 EVEX_W_0F11_P_3): New.
103 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
104 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
105 MOD_EVEX_0F11_PREFIX_3 table entries.
106 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
107 PREFIX_EVEX_0F11 table entries.
108 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
109 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
110 EVEX_W_0F11_P_3_M_{0,1} table entries.
112 2019-07-01 Jan Beulich <jbeulich@suse.com>
114 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
117 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
120 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
121 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
122 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
123 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
124 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
125 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
126 EVEX_LEN_0F38C7_R_6_P_2_W_1.
127 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
128 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
129 PREFIX_EVEX_0F38C6_REG_6 entries.
130 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
131 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
132 EVEX_W_0F38C7_R_6_P_2 entries.
133 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
134 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
135 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
136 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
137 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
138 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
139 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
141 2019-06-27 Jan Beulich <jbeulich@suse.com>
143 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
144 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
145 VEX_LEN_0F2D_P_3): Delete.
146 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
147 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
148 (prefix_table): ... here.
150 2019-06-27 Jan Beulich <jbeulich@suse.com>
152 * i386-dis.c (Iq): Delete.
154 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
156 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
157 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
158 (OP_E_memory): Also honor needindex when deciding whether an
159 address size prefix needs printing.
160 (OP_I): Remove handling of q_mode. Add handling of d_mode.
162 2019-06-26 Jim Wilson <jimw@sifive.com>
165 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
166 Set info->display_endian to info->endian_code.
168 2019-06-25 Jan Beulich <jbeulich@suse.com>
170 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
171 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
172 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
173 OPERAND_TYPE_ACC64 entries.
174 * i386-init.h: Re-generate.
176 2019-06-25 Jan Beulich <jbeulich@suse.com>
178 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
180 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
182 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
184 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
185 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
187 2019-06-25 Jan Beulich <jbeulich@suse.com>
189 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
192 2019-06-25 Jan Beulich <jbeulich@suse.com>
194 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
195 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
197 * i386-opc.tbl (movnti): Add IgnoreSize.
198 * i386-tbl.h: Re-generate.
200 2019-06-25 Jan Beulich <jbeulich@suse.com>
202 * i386-opc.tbl (and): Mark Imm8S form for optimization.
203 * i386-tbl.h: Re-generate.
205 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
207 * i386-dis-evex.h: Break into ...
208 * i386-dis-evex-len.h: New file.
209 * i386-dis-evex-mod.h: Likewise.
210 * i386-dis-evex-prefix.h: Likewise.
211 * i386-dis-evex-reg.h: Likewise.
212 * i386-dis-evex-w.h: Likewise.
213 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
214 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
217 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
220 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
221 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
223 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
224 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
225 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
226 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
227 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
228 EVEX_LEN_0F385B_P_2_W_1.
229 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
230 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
231 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
232 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
233 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
234 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
235 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
236 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
237 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
238 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
240 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
243 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
244 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
245 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
246 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
247 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
248 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
249 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
250 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
251 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
252 EVEX_LEN_0F3A43_P_2_W_1.
253 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
254 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
255 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
256 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
257 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
258 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
259 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
260 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
261 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
262 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
263 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
264 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
266 2019-06-14 Nick Clifton <nickc@redhat.com>
268 * po/fr.po; Updated French translation.
270 2019-06-13 Stafford Horne <shorne@gmail.com>
272 * or1k-asm.c: Regenerated.
273 * or1k-desc.c: Regenerated.
274 * or1k-desc.h: Regenerated.
275 * or1k-dis.c: Regenerated.
276 * or1k-ibld.c: Regenerated.
277 * or1k-opc.c: Regenerated.
278 * or1k-opc.h: Regenerated.
279 * or1k-opinst.c: Regenerated.
281 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
283 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
285 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
288 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
289 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
290 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
291 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
292 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
293 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
294 EVEX_LEN_0F3A1B_P_2_W_1.
295 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
296 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
297 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
298 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
299 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
300 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
301 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
302 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
304 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
307 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
308 EVEX.vvvv when disassembling VEX and EVEX instructions.
309 (OP_VEX): Set vex.register_specifier to 0 after readding
310 vex.register_specifier.
311 (OP_Vex_2src_1): Likewise.
312 (OP_Vex_2src_2): Likewise.
313 (OP_LWP_E): Likewise.
314 (OP_EX_Vex): Don't check vex.register_specifier.
315 (OP_XMM_Vex): Likewise.
317 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
318 Lili Cui <lili.cui@intel.com>
320 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
321 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
323 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
324 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
325 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
326 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
327 (i386_cpu_flags): Add cpuavx512_vp2intersect.
328 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
329 * i386-init.h: Regenerated.
330 * i386-tbl.h: Likewise.
332 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
333 Lili Cui <lili.cui@intel.com>
335 * doc/c-i386.texi: Document enqcmd.
336 * testsuite/gas/i386/enqcmd-intel.d: New file.
337 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
338 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
339 * testsuite/gas/i386/enqcmd.d: Likewise.
340 * testsuite/gas/i386/enqcmd.s: Likewise.
341 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
342 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
343 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
344 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
345 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
346 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
347 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
350 2019-06-04 Alan Hayward <alan.hayward@arm.com>
352 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
354 2019-06-03 Alan Modra <amodra@gmail.com>
356 * ppc-dis.c (prefix_opcd_indices): Correct size.
358 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
361 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
363 * i386-tbl.h: Regenerated.
365 2019-05-24 Alan Modra <amodra@gmail.com>
367 * po/POTFILES.in: Regenerate.
369 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
370 Alan Modra <amodra@gmail.com>
372 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
373 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
374 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
375 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
376 XTOP>): Define and add entries.
377 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
378 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
379 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
380 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
382 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
383 Alan Modra <amodra@gmail.com>
385 * ppc-dis.c (ppc_opts): Add "future" entry.
386 (PREFIX_OPCD_SEGS): Define.
387 (prefix_opcd_indices): New array.
388 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
389 (lookup_prefix): New function.
390 (print_insn_powerpc): Handle 64-bit prefix instructions.
391 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
392 (PMRR, POWERXX): Define.
393 (prefix_opcodes): New instruction table.
394 (prefix_num_opcodes): New constant.
396 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
398 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
399 * configure: Regenerated.
400 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
402 (HFILES): Add bpf-desc.h and bpf-opc.h.
403 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
404 bpf-ibld.c and bpf-opc.c.
406 * Makefile.in: Regenerated.
407 * disassemble.c (ARCH_bpf): Define.
408 (disassembler): Add case for bfd_arch_bpf.
409 (disassemble_init_for_target): Likewise.
410 (enum epbf_isa_attr): Define.
411 * disassemble.h: extern print_insn_bpf.
412 * bpf-asm.c: Generated.
413 * bpf-opc.h: Likewise.
414 * bpf-opc.c: Likewise.
415 * bpf-ibld.c: Likewise.
416 * bpf-dis.c: Likewise.
417 * bpf-desc.h: Likewise.
418 * bpf-desc.c: Likewise.
420 2019-05-21 Sudakshina Das <sudi.das@arm.com>
422 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
423 and VMSR with the new operands.
425 2019-05-21 Sudakshina Das <sudi.das@arm.com>
427 * arm-dis.c (enum mve_instructions): New enum
428 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
430 (mve_opcodes): New instructions as above.
431 (is_mve_encoding_conflict): Add cases for csinc, csinv,
433 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
435 2019-05-21 Sudakshina Das <sudi.das@arm.com>
437 * arm-dis.c (emun mve_instructions): Updated for new instructions.
438 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
439 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
440 uqshl, urshrl and urshr.
441 (is_mve_okay_in_it): Add new instructions to TRUE list.
442 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
443 (print_insn_mve): Updated to accept new %j,
444 %<bitfield>m and %<bitfield>n patterns.
446 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
448 * mips-opc.c (mips_builtin_opcodes): Change source register
451 2019-05-20 Nick Clifton <nickc@redhat.com>
453 * po/fr.po: Updated French translation.
455 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
456 Michael Collison <michael.collison@arm.com>
458 * arm-dis.c (thumb32_opcodes): Add new instructions.
459 (enum mve_instructions): Likewise.
460 (enum mve_undefined): Add new reasons.
461 (is_mve_encoding_conflict): Handle new instructions.
462 (is_mve_undefined): Likewise.
463 (is_mve_unpredictable): Likewise.
464 (print_mve_undefined): Likewise.
465 (print_mve_size): Likewise.
467 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
468 Michael Collison <michael.collison@arm.com>
470 * arm-dis.c (thumb32_opcodes): Add new instructions.
471 (enum mve_instructions): Likewise.
472 (is_mve_encoding_conflict): Handle new instructions.
473 (is_mve_undefined): Likewise.
474 (is_mve_unpredictable): Likewise.
475 (print_mve_size): Likewise.
477 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
478 Michael Collison <michael.collison@arm.com>
480 * arm-dis.c (thumb32_opcodes): Add new instructions.
481 (enum mve_instructions): Likewise.
482 (is_mve_encoding_conflict): Likewise.
483 (is_mve_unpredictable): Likewise.
484 (print_mve_size): Likewise.
486 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
487 Michael Collison <michael.collison@arm.com>
489 * arm-dis.c (thumb32_opcodes): Add new instructions.
490 (enum mve_instructions): Likewise.
491 (is_mve_encoding_conflict): Handle new instructions.
492 (is_mve_undefined): Likewise.
493 (is_mve_unpredictable): Likewise.
494 (print_mve_size): Likewise.
496 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
497 Michael Collison <michael.collison@arm.com>
499 * arm-dis.c (thumb32_opcodes): Add new instructions.
500 (enum mve_instructions): Likewise.
501 (is_mve_encoding_conflict): Handle new instructions.
502 (is_mve_undefined): Likewise.
503 (is_mve_unpredictable): Likewise.
504 (print_mve_size): Likewise.
505 (print_insn_mve): Likewise.
507 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
508 Michael Collison <michael.collison@arm.com>
510 * arm-dis.c (thumb32_opcodes): Add new instructions.
511 (print_insn_thumb32): Handle new instructions.
513 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
514 Michael Collison <michael.collison@arm.com>
516 * arm-dis.c (enum mve_instructions): Add new instructions.
517 (enum mve_undefined): Add new reasons.
518 (is_mve_encoding_conflict): Handle new instructions.
519 (is_mve_undefined): Likewise.
520 (is_mve_unpredictable): Likewise.
521 (print_mve_undefined): Likewise.
522 (print_mve_size): Likewise.
523 (print_mve_shift_n): Likewise.
524 (print_insn_mve): Likewise.
526 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
527 Michael Collison <michael.collison@arm.com>
529 * arm-dis.c (enum mve_instructions): Add new instructions.
530 (is_mve_encoding_conflict): Handle new instructions.
531 (is_mve_unpredictable): Likewise.
532 (print_mve_rotate): Likewise.
533 (print_mve_size): Likewise.
534 (print_insn_mve): Likewise.
536 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
537 Michael Collison <michael.collison@arm.com>
539 * arm-dis.c (enum mve_instructions): Add new instructions.
540 (is_mve_encoding_conflict): Handle new instructions.
541 (is_mve_unpredictable): Likewise.
542 (print_mve_size): Likewise.
543 (print_insn_mve): Likewise.
545 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
546 Michael Collison <michael.collison@arm.com>
548 * arm-dis.c (enum mve_instructions): Add new instructions.
549 (enum mve_undefined): Add new reasons.
550 (is_mve_encoding_conflict): Handle new instructions.
551 (is_mve_undefined): Likewise.
552 (is_mve_unpredictable): Likewise.
553 (print_mve_undefined): Likewise.
554 (print_mve_size): Likewise.
555 (print_insn_mve): Likewise.
557 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
558 Michael Collison <michael.collison@arm.com>
560 * arm-dis.c (enum mve_instructions): Add new instructions.
561 (is_mve_encoding_conflict): Handle new instructions.
562 (is_mve_undefined): Likewise.
563 (is_mve_unpredictable): Likewise.
564 (print_mve_size): Likewise.
565 (print_insn_mve): Likewise.
567 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
568 Michael Collison <michael.collison@arm.com>
570 * arm-dis.c (enum mve_instructions): Add new instructions.
571 (enum mve_unpredictable): Add new reasons.
572 (enum mve_undefined): Likewise.
573 (is_mve_okay_in_it): Handle new isntructions.
574 (is_mve_encoding_conflict): Likewise.
575 (is_mve_undefined): Likewise.
576 (is_mve_unpredictable): Likewise.
577 (print_mve_vmov_index): Likewise.
578 (print_simd_imm8): Likewise.
579 (print_mve_undefined): Likewise.
580 (print_mve_unpredictable): Likewise.
581 (print_mve_size): Likewise.
582 (print_insn_mve): Likewise.
584 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
585 Michael Collison <michael.collison@arm.com>
587 * arm-dis.c (enum mve_instructions): Add new instructions.
588 (enum mve_unpredictable): Add new reasons.
589 (enum mve_undefined): Likewise.
590 (is_mve_encoding_conflict): Handle new instructions.
591 (is_mve_undefined): Likewise.
592 (is_mve_unpredictable): Likewise.
593 (print_mve_undefined): Likewise.
594 (print_mve_unpredictable): Likewise.
595 (print_mve_rounding_mode): Likewise.
596 (print_mve_vcvt_size): Likewise.
597 (print_mve_size): Likewise.
598 (print_insn_mve): Likewise.
600 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
601 Michael Collison <michael.collison@arm.com>
603 * arm-dis.c (enum mve_instructions): Add new instructions.
604 (enum mve_unpredictable): Add new reasons.
605 (enum mve_undefined): Likewise.
606 (is_mve_undefined): Handle new instructions.
607 (is_mve_unpredictable): Likewise.
608 (print_mve_undefined): Likewise.
609 (print_mve_unpredictable): Likewise.
610 (print_mve_size): Likewise.
611 (print_insn_mve): Likewise.
613 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
614 Michael Collison <michael.collison@arm.com>
616 * arm-dis.c (enum mve_instructions): Add new instructions.
617 (enum mve_undefined): Add new reasons.
618 (insns): Add new instructions.
619 (is_mve_encoding_conflict):
620 (print_mve_vld_str_addr): New print function.
621 (is_mve_undefined): Handle new instructions.
622 (is_mve_unpredictable): Likewise.
623 (print_mve_undefined): Likewise.
624 (print_mve_size): Likewise.
625 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
626 (print_insn_mve): Handle new operands.
628 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
629 Michael Collison <michael.collison@arm.com>
631 * arm-dis.c (enum mve_instructions): Add new instructions.
632 (enum mve_unpredictable): Add new reasons.
633 (is_mve_encoding_conflict): Handle new instructions.
634 (is_mve_unpredictable): Likewise.
635 (mve_opcodes): Add new instructions.
636 (print_mve_unpredictable): Handle new reasons.
637 (print_mve_register_blocks): New print function.
638 (print_mve_size): Handle new instructions.
639 (print_insn_mve): Likewise.
641 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
642 Michael Collison <michael.collison@arm.com>
644 * arm-dis.c (enum mve_instructions): Add new instructions.
645 (enum mve_unpredictable): Add new reasons.
646 (enum mve_undefined): Likewise.
647 (is_mve_encoding_conflict): Handle new instructions.
648 (is_mve_undefined): Likewise.
649 (is_mve_unpredictable): Likewise.
650 (coprocessor_opcodes): Move NEON VDUP from here...
651 (neon_opcodes): ... to here.
652 (mve_opcodes): Add new instructions.
653 (print_mve_undefined): Handle new reasons.
654 (print_mve_unpredictable): Likewise.
655 (print_mve_size): Handle new instructions.
656 (print_insn_neon): Handle vdup.
657 (print_insn_mve): Handle new operands.
659 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
660 Michael Collison <michael.collison@arm.com>
662 * arm-dis.c (enum mve_instructions): Add new instructions.
663 (enum mve_unpredictable): Add new values.
664 (mve_opcodes): Add new instructions.
665 (vec_condnames): New array with vector conditions.
666 (mve_predicatenames): New array with predicate suffixes.
667 (mve_vec_sizename): New array with vector sizes.
668 (enum vpt_pred_state): New enum with vector predication states.
669 (struct vpt_block): New struct type for vpt blocks.
670 (vpt_block_state): Global struct to keep track of state.
671 (mve_extract_pred_mask): New helper function.
672 (num_instructions_vpt_block): Likewise.
673 (mark_outside_vpt_block): Likewise.
674 (mark_inside_vpt_block): Likewise.
675 (invert_next_predicate_state): Likewise.
676 (update_next_predicate_state): Likewise.
677 (update_vpt_block_state): Likewise.
678 (is_vpt_instruction): Likewise.
679 (is_mve_encoding_conflict): Add entries for new instructions.
680 (is_mve_unpredictable): Likewise.
681 (print_mve_unpredictable): Handle new cases.
682 (print_instruction_predicate): Likewise.
683 (print_mve_size): New function.
684 (print_vec_condition): New function.
685 (print_insn_mve): Handle vpt blocks and new print operands.
687 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
689 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
690 8, 14 and 15 for Armv8.1-M Mainline.
692 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
693 Michael Collison <michael.collison@arm.com>
695 * arm-dis.c (enum mve_instructions): New enum.
696 (enum mve_unpredictable): Likewise.
697 (enum mve_undefined): Likewise.
698 (struct mopcode32): New struct.
699 (is_mve_okay_in_it): New function.
700 (is_mve_architecture): Likewise.
701 (arm_decode_field): Likewise.
702 (arm_decode_field_multiple): Likewise.
703 (is_mve_encoding_conflict): Likewise.
704 (is_mve_undefined): Likewise.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_undefined): Likewise.
707 (print_mve_unpredictable): Likewise.
708 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
709 (print_insn_mve): New function.
710 (print_insn_thumb32): Handle MVE architecture.
711 (select_arm_features): Force thumb for Armv8.1-m Mainline.
713 2019-05-10 Nick Clifton <nickc@redhat.com>
716 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
717 end of the table prematurely.
719 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
721 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
724 2019-05-11 Alan Modra <amodra@gmail.com>
726 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
727 when -Mraw is in effect.
729 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
731 * aarch64-dis-2.c: Regenerate.
732 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
733 (OP_SVE_BBB): New variant set.
734 (OP_SVE_DDDD): New variant set.
735 (OP_SVE_HHH): New variant set.
736 (OP_SVE_HHHU): New variant set.
737 (OP_SVE_SSS): New variant set.
738 (OP_SVE_SSSU): New variant set.
739 (OP_SVE_SHH): New variant set.
740 (OP_SVE_SBBU): New variant set.
741 (OP_SVE_DSS): New variant set.
742 (OP_SVE_DHHU): New variant set.
743 (OP_SVE_VMV_HSD_BHS): New variant set.
744 (OP_SVE_VVU_HSD_BHS): New variant set.
745 (OP_SVE_VVVU_SD_BH): New variant set.
746 (OP_SVE_VVVU_BHSD): New variant set.
747 (OP_SVE_VVV_QHD_DBS): New variant set.
748 (OP_SVE_VVV_HSD_BHS): New variant set.
749 (OP_SVE_VVV_HSD_BHS2): New variant set.
750 (OP_SVE_VVV_BHS_HSD): New variant set.
751 (OP_SVE_VV_BHS_HSD): New variant set.
752 (OP_SVE_VVV_SD): New variant set.
753 (OP_SVE_VVU_BHS_HSD): New variant set.
754 (OP_SVE_VZVV_SD): New variant set.
755 (OP_SVE_VZVV_BH): New variant set.
756 (OP_SVE_VZV_SD): New variant set.
757 (aarch64_opcode_table): Add sve2 instructions.
759 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
761 * aarch64-asm-2.c: Regenerated.
762 * aarch64-dis-2.c: Regenerated.
763 * aarch64-opc-2.c: Regenerated.
764 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
765 for SVE_SHLIMM_UNPRED_22.
766 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
767 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
770 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
772 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
773 sve_size_tsz_bhs iclass encode.
774 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
775 sve_size_tsz_bhs iclass decode.
777 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
779 * aarch64-asm-2.c: Regenerated.
780 * aarch64-dis-2.c: Regenerated.
781 * aarch64-opc-2.c: Regenerated.
782 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
783 for SVE_Zm4_11_INDEX.
784 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
785 (fields): Handle SVE_i2h field.
786 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
787 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
789 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
791 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
792 sve_shift_tsz_bhsd iclass encode.
793 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
794 sve_shift_tsz_bhsd iclass decode.
796 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
798 * aarch64-asm-2.c: Regenerated.
799 * aarch64-dis-2.c: Regenerated.
800 * aarch64-opc-2.c: Regenerated.
801 * aarch64-asm.c (aarch64_ins_sve_shrimm):
802 (aarch64_encode_variant_using_iclass): Handle
803 sve_shift_tsz_hsd iclass encode.
804 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
805 sve_shift_tsz_hsd iclass decode.
806 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
807 for SVE_SHRIMM_UNPRED_22.
808 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
809 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
812 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
814 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
815 sve_size_013 iclass encode.
816 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
817 sve_size_013 iclass decode.
819 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
821 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
822 sve_size_bh iclass encode.
823 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
824 sve_size_bh iclass decode.
826 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
828 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
829 sve_size_sd2 iclass encode.
830 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
831 sve_size_sd2 iclass decode.
832 * aarch64-opc.c (fields): Handle SVE_sz2 field.
833 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
835 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
837 * aarch64-asm-2.c: Regenerated.
838 * aarch64-dis-2.c: Regenerated.
839 * aarch64-opc-2.c: Regenerated.
840 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
842 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
843 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
845 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
847 * aarch64-asm-2.c: Regenerated.
848 * aarch64-dis-2.c: Regenerated.
849 * aarch64-opc-2.c: Regenerated.
850 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
851 for SVE_Zm3_11_INDEX.
852 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
853 (fields): Handle SVE_i3l and SVE_i3h2 fields.
854 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
856 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
858 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
860 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
861 sve_size_hsd2 iclass encode.
862 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
863 sve_size_hsd2 iclass decode.
864 * aarch64-opc.c (fields): Handle SVE_size field.
865 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
867 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
869 * aarch64-asm-2.c: Regenerated.
870 * aarch64-dis-2.c: Regenerated.
871 * aarch64-opc-2.c: Regenerated.
872 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
874 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
875 (fields): Handle SVE_rot3 field.
876 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
877 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
879 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
881 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
884 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
887 (aarch64_feature_sve2, aarch64_feature_sve2aes,
888 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
889 aarch64_feature_sve2bitperm): New feature sets.
890 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
891 for feature set addresses.
892 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
893 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
895 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
896 Faraz Shahbazker <fshahbazker@wavecomp.com>
898 * mips-dis.c (mips_calculate_combination_ases): Add ISA
899 argument and set ASE_EVA_R6 appropriately.
900 (set_default_mips_dis_options): Pass ISA to above.
901 (parse_mips_dis_option): Likewise.
902 * mips-opc.c (EVAR6): New macro.
903 (mips_builtin_opcodes): Add llwpe, scwpe.
905 2019-05-01 Sudakshina Das <sudi.das@arm.com>
907 * aarch64-asm-2.c: Regenerated.
908 * aarch64-dis-2.c: Regenerated.
909 * aarch64-opc-2.c: Regenerated.
910 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
911 AARCH64_OPND_TME_UIMM16.
912 (aarch64_print_operand): Likewise.
913 * aarch64-tbl.h (QL_IMM_NIL): New.
916 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
918 2019-04-29 John Darrington <john@darrington.wattle.id.au>
920 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
922 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
923 Faraz Shahbazker <fshahbazker@wavecomp.com>
925 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
927 2019-04-24 John Darrington <john@darrington.wattle.id.au>
929 * s12z-opc.h: Add extern "C" bracketing to help
930 users who wish to use this interface in c++ code.
932 2019-04-24 John Darrington <john@darrington.wattle.id.au>
934 * s12z-opc.c (bm_decode): Handle bit map operations with the
937 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
939 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
940 specifier. Add entries for VLDR and VSTR of system registers.
941 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
942 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
943 of %J and %K format specifier.
945 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
947 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
948 Add new entries for VSCCLRM instruction.
949 (print_insn_coprocessor): Handle new %C format control code.
951 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
953 * arm-dis.c (enum isa): New enum.
954 (struct sopcode32): New structure.
955 (coprocessor_opcodes): change type of entries to struct sopcode32 and
956 set isa field of all current entries to ANY.
957 (print_insn_coprocessor): Change type of insn to struct sopcode32.
958 Only match an entry if its isa field allows the current mode.
960 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
962 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
964 (print_insn_thumb32): Add logic to print %n CLRM register list.
966 2019-04-15 Sudakshina Das <sudi.das@arm.com>
968 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
971 2019-04-15 Sudakshina Das <sudi.das@arm.com>
973 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
974 (print_insn_thumb32): Edit the switch case for %Z.
976 2019-04-15 Sudakshina Das <sudi.das@arm.com>
978 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
980 2019-04-15 Sudakshina Das <sudi.das@arm.com>
982 * arm-dis.c (thumb32_opcodes): New instruction bfl.
984 2019-04-15 Sudakshina Das <sudi.das@arm.com>
986 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
988 2019-04-15 Sudakshina Das <sudi.das@arm.com>
990 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
991 Arm register with r13 and r15 unpredictable.
992 (thumb32_opcodes): New instructions for bfx and bflx.
994 2019-04-15 Sudakshina Das <sudi.das@arm.com>
996 * arm-dis.c (thumb32_opcodes): New instructions for bf.
998 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1000 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1002 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1004 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1006 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1008 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1010 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1012 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1013 "optr". ("operator" is a reserved word in c++).
1015 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1017 * aarch64-opc.c (aarch64_print_operand): Add case for
1019 (verify_constraints): Likewise.
1020 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1021 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1022 to accept Rt|SP as first operand.
1023 (AARCH64_OPERANDS): Add new Rt_SP.
1024 * aarch64-asm-2.c: Regenerated.
1025 * aarch64-dis-2.c: Regenerated.
1026 * aarch64-opc-2.c: Regenerated.
1028 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1030 * aarch64-asm-2.c: Regenerated.
1031 * aarch64-dis-2.c: Likewise.
1032 * aarch64-opc-2.c: Likewise.
1033 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1035 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1037 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1039 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1041 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1042 * i386-init.h: Regenerated.
1044 2019-04-07 Alan Modra <amodra@gmail.com>
1046 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1047 op_separator to control printing of spaces, comma and parens
1048 rather than need_comma, need_paren and spaces vars.
1050 2019-04-07 Alan Modra <amodra@gmail.com>
1053 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1054 (print_insn_neon, print_insn_arm): Likewise.
1056 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1058 * i386-dis-evex.h (evex_table): Updated to support BF16
1060 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1061 and EVEX_W_0F3872_P_3.
1062 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1063 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1064 * i386-opc.h (enum): Add CpuAVX512_BF16.
1065 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1066 * i386-opc.tbl: Add AVX512 BF16 instructions.
1067 * i386-init.h: Regenerated.
1068 * i386-tbl.h: Likewise.
1070 2019-04-05 Alan Modra <amodra@gmail.com>
1072 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1073 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1074 to favour printing of "-" branch hint when using the "y" bit.
1075 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1077 2019-04-05 Alan Modra <amodra@gmail.com>
1079 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1080 opcode until first operand is output.
1082 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1085 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1086 (valid_bo_post_v2): Add support for 'at' branch hints.
1087 (insert_bo): Only error on branch on ctr.
1088 (get_bo_hint_mask): New function.
1089 (insert_boe): Add new 'branch_taken' formal argument. Add support
1090 for inserting 'at' branch hints.
1091 (extract_boe): Add new 'branch_taken' formal argument. Add support
1092 for extracting 'at' branch hints.
1093 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1094 (BOE): Delete operand.
1095 (BOM, BOP): New operands.
1097 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1098 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1099 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1100 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1101 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1102 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1103 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1104 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1105 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1106 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1107 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1108 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1109 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1110 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1111 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1112 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1113 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1114 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1115 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1116 bttarl+>: New extended mnemonics.
1118 2019-03-28 Alan Modra <amodra@gmail.com>
1121 * ppc-opc.c (BTF): Define.
1122 (powerpc_opcodes): Use for mtfsb*.
1123 * ppc-dis.c (print_insn_powerpc): Print fields with both
1124 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1126 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1128 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1129 (mapping_symbol_for_insn): Implement new algorithm.
1130 (print_insn): Remove duplicate code.
1132 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1134 * aarch64-dis.c (print_insn_aarch64):
1137 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1139 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1142 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1144 * aarch64-dis.c (last_stop_offset): New.
1145 (print_insn_aarch64): Use stop_offset.
1147 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1150 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1152 * i386-init.h: Regenerated.
1154 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1157 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1158 vmovdqu16, vmovdqu32 and vmovdqu64.
1159 * i386-tbl.h: Regenerated.
1161 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1163 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1164 from vstrszb, vstrszh, and vstrszf.
1166 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1168 * s390-opc.txt: Add instruction descriptions.
1170 2019-02-08 Jim Wilson <jimw@sifive.com>
1172 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1175 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1177 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1179 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1182 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1183 * aarch64-opc.c (verify_elem_sd): New.
1184 (fields): Add FLD_sz entr.
1185 * aarch64-tbl.h (_SIMD_INSN): New.
1186 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1187 fmulx scalar and vector by element isns.
1189 2019-02-07 Nick Clifton <nickc@redhat.com>
1191 * po/sv.po: Updated Swedish translation.
1193 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1195 * s390-mkopc.c (main): Accept arch13 as cpu string.
1196 * s390-opc.c: Add new instruction formats and instruction opcode
1198 * s390-opc.txt: Add new arch13 instructions.
1200 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1202 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1203 (aarch64_opcode): Change encoding for stg, stzg
1205 * aarch64-asm-2.c: Regenerated.
1206 * aarch64-dis-2.c: Regenerated.
1207 * aarch64-opc-2.c: Regenerated.
1209 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1211 * aarch64-asm-2.c: Regenerated.
1212 * aarch64-dis-2.c: Likewise.
1213 * aarch64-opc-2.c: Likewise.
1214 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1216 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1217 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1219 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1220 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1221 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1222 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1223 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1224 case for ldstgv_indexed.
1225 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1226 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1227 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1228 * aarch64-asm-2.c: Regenerated.
1229 * aarch64-dis-2.c: Regenerated.
1230 * aarch64-opc-2.c: Regenerated.
1232 2019-01-23 Nick Clifton <nickc@redhat.com>
1234 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1236 2019-01-21 Nick Clifton <nickc@redhat.com>
1238 * po/de.po: Updated German translation.
1239 * po/uk.po: Updated Ukranian translation.
1241 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1242 * mips-dis.c (mips_arch_choices): Fix typo in
1243 gs464, gs464e and gs264e descriptors.
1245 2019-01-19 Nick Clifton <nickc@redhat.com>
1247 * configure: Regenerate.
1248 * po/opcodes.pot: Regenerate.
1250 2018-06-24 Nick Clifton <nickc@redhat.com>
1252 2.32 branch created.
1254 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1256 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1258 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1261 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1263 * configure: Regenerate.
1265 2019-01-07 Alan Modra <amodra@gmail.com>
1267 * configure: Regenerate.
1268 * po/POTFILES.in: Regenerate.
1270 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1272 * s12z-opc.c: New file.
1273 * s12z-opc.h: New file.
1274 * s12z-dis.c: Removed all code not directly related to display
1275 of instructions. Used the interface provided by the new files
1277 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1278 * Makefile.in: Regenerate.
1279 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1280 * configure: Regenerate.
1282 2019-01-01 Alan Modra <amodra@gmail.com>
1284 Update year range in copyright notice of all files.
1286 For older changes see ChangeLog-2018
1288 Copyright (C) 2019 Free Software Foundation, Inc.
1290 Copying and distribution of this file, with or without modification,
1291 are permitted in any medium without royalty provided the copyright
1292 notice and this notice are preserved.
1298 version-control: never