1 2013-06-14 DJ Delorie <dj@redhat.com>
3 * rx-decode.opc (rx_decode_opcode): Bit operations on
4 registers are 32-bit operations, not 8-bit operations.
5 * rx-decode.c: Regenerate.
7 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
9 * micromips-opc.c (IVIRT): New define.
10 (IVIRT64): New define.
11 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
12 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
14 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
15 dmtgc0 to print cp0 names.
17 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
19 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
22 2013-06-08 Catherine Moore <clm@codesourcery.com>
23 Richard Sandiford <rdsandiford@googlemail.com>
25 * micromips-opc.c (D32, D33, MC): Update definitions.
26 (micromips_opcodes): Initialize ase field.
27 * mips-dis.c (mips_arch_choice): Add ase field.
28 (mips_arch_choices): Initialize ase field.
29 (set_default_mips_dis_options): Declare and setup mips_ase.
30 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
31 MT32, MC): Update definitions.
32 (mips_builtin_opcodes): Initialize ase field.
34 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
36 * s390-opc.txt (flogr): Require a register pair destination.
38 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
40 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
43 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
45 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
47 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
49 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
50 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
51 XLS_MASK, PPCVSX2): New defines.
52 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
53 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
54 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
55 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
56 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
57 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
58 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
59 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
60 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
61 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
62 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
63 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
64 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
65 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
66 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
67 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
68 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
69 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
70 <lxvx, stxvx>: New extended mnemonics.
72 2013-05-17 Alan Modra <amodra@gmail.com>
74 * ia64-raw.tbl: Replace non-ASCII char.
75 * ia64-waw.tbl: Likewise.
76 * ia64-asmtab.c: Regenerate.
78 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
80 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
81 * i386-init.h: Regenerated.
83 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
85 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
86 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
87 check from [0, 255] to [-128, 255].
89 2013-05-09 Andrew Pinski <apinski@cavium.com>
91 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
92 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
93 (parse_mips_dis_option): Handle the virt option.
94 (print_insn_args): Handle "+J".
95 (print_mips_disassembler_options): Print out message about virt64.
96 * mips-opc.c (IVIRT): New define.
97 (IVIRT64): New define.
98 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
99 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
100 Move rfe to the bottom as it conflicts with tlbgp.
102 2013-05-09 Alan Modra <amodra@gmail.com>
104 * ppc-opc.c (extract_vlesi): Properly sign extend.
105 (extract_vlensi): Likewise. Comment reason for setting invalid.
107 2013-05-02 Nick Clifton <nickc@redhat.com>
109 * msp430-dis.c: Add support for MSP430X instructions.
111 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
113 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
116 2013-04-17 Wei-chen Wang <cole945@gmail.com>
119 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
121 (hash_insns_list): Likewise.
123 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
125 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
128 2013-04-08 Jan Beulich <jbeulich@suse.com>
130 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
131 * i386-tbl.h: Re-generate.
133 2013-04-06 David S. Miller <davem@davemloft.net>
135 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
136 of an opcode, prefer the one with F_PREFERRED set.
137 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
138 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
139 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
140 mark existing mnenomics as aliases. Add "cc" suffix to edge
141 instructions generating condition codes, mark existing mnenomics
142 as aliases. Add "fp" prefix to VIS compare instructions, mark
143 existing mnenomics as aliases.
145 2013-04-03 Nick Clifton <nickc@redhat.com>
147 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
148 destination address by subtracting the operand from the current
150 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
151 a positive value in the insn.
152 (extract_u16_loop): Do not negate the returned value.
153 (D16_LOOP): Add V850_INVERSE_PCREL flag.
155 (ceilf.sw): Remove duplicate entry.
156 (cvtf.hs): New entry.
162 (maddf.s): Restrict to E3V5 architectures.
164 (nmaddf.s): Likewise.
165 (nmsubf.s): Likewise.
167 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
169 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
171 (print_insn): Pass sizeflag to get_sib.
173 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
176 * tic6x-dis.c: Add support for displaying 16-bit insns.
178 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
181 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
182 individual msb and lsb halves in src1 & src2 fields. Discard the
183 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
184 follow what Ti SDK does in that case as any value in the src1
185 field yields the same output with SDK disassembler.
187 2013-03-12 Michael Eager <eager@eagercon.com>
189 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
191 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
193 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
195 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
197 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
199 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
201 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
203 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
205 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
206 (thumb32_opcodes): Likewise.
207 (print_insn_thumb32): Handle 'S' control char.
209 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
211 * lm32-desc.c: Regenerate.
213 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
215 * i386-reg.tbl (riz): Add RegRex64.
216 * i386-tbl.h: Regenerated.
218 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
220 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
221 (aarch64_feature_crc): New static.
223 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
224 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
225 * aarch64-asm-2.c: Re-generate.
226 * aarch64-dis-2.c: Ditto.
227 * aarch64-opc-2.c: Ditto.
229 2013-02-27 Alan Modra <amodra@gmail.com>
231 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
232 * rl78-decode.c: Regenerate.
234 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
236 * rl78-decode.opc: Fix encoding of DIVWU insn.
237 * rl78-decode.c: Regenerate.
239 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
242 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
244 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
245 (cpu_flags): Add CpuSMAP.
247 * i386-opc.h (CpuSMAP): New.
248 (i386_cpu_flags): Add cpusmap.
250 * i386-opc.tbl: Add clac and stac.
252 * i386-init.h: Regenerated.
253 * i386-tbl.h: Likewise.
255 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
257 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
258 which also makes the disassembler output be in little
259 endian like it should be.
261 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
263 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
265 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
267 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
269 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
270 section disassembled.
272 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
274 * arm-dis.c: Update strht pattern.
276 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
278 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
279 single-float. Disable ll, lld, sc and scd for EE. Disable the
280 trunc.w.s macro for EE.
282 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
283 Andrew Jenner <andrew@codesourcery.com>
285 Based on patches from Altera Corporation.
287 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
289 * Makefile.in: Regenerated.
290 * configure.in: Add case for bfd_nios2_arch.
291 * configure: Regenerated.
292 * disassemble.c (ARCH_nios2): Define.
293 (disassembler): Add case for bfd_arch_nios2.
294 * nios2-dis.c: New file.
295 * nios2-opc.c: New file.
297 2013-02-04 Alan Modra <amodra@gmail.com>
299 * po/POTFILES.in: Regenerate.
300 * rl78-decode.c: Regenerate.
301 * rx-decode.c: Regenerate.
303 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
305 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
306 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
307 * aarch64-asm.c (convert_xtl_to_shll): New function.
308 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
309 calling convert_xtl_to_shll.
310 * aarch64-dis.c (convert_shll_to_xtl): New function.
311 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
312 calling convert_shll_to_xtl.
313 * aarch64-gen.c: Update copyright year.
314 * aarch64-asm-2.c: Re-generate.
315 * aarch64-dis-2.c: Re-generate.
316 * aarch64-opc-2.c: Re-generate.
318 2013-01-24 Nick Clifton <nickc@redhat.com>
320 * v850-dis.c: Add support for e3v5 architecture.
321 * v850-opc.c: Likewise.
323 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
325 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
326 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
327 * aarch64-opc.c (operand_general_constraint_met_p): For
328 AARCH64_MOD_LSL, move the range check on the shift amount before the
329 alignment check; change to call set_sft_amount_out_of_range_error
330 instead of set_imm_out_of_range_error.
331 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
332 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
333 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
336 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
338 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
340 * i386-init.h: Regenerated.
341 * i386-tbl.h: Likewise.
343 2013-01-15 Nick Clifton <nickc@redhat.com>
345 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
347 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
349 2013-01-14 Will Newton <will.newton@imgtec.com>
351 * metag-dis.c (REG_WIDTH): Increase to 64.
353 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
355 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
356 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
357 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
359 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
360 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
361 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
362 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
364 2013-01-10 Will Newton <will.newton@imgtec.com>
366 * Makefile.am: Add Meta.
367 * configure.in: Add Meta.
368 * disassemble.c: Add Meta support.
369 * metag-dis.c: New file.
370 * Makefile.in: Regenerate.
371 * configure: Regenerate.
373 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
375 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
376 (match_opcode): Rename to cr16_match_opcode.
378 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
380 * mips-dis.c: Add names for CP0 registers of r5900.
381 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
382 instructions sq and lq.
383 Add support for MIPS r5900 CPU.
384 Add support for 128 bit MMI (Multimedia Instructions).
385 Add support for EE instructions (Emotion Engine).
386 Disable unsupported floating point instructions (64 bit and
387 undefined compare operations).
388 Enable instructions of MIPS ISA IV which are supported by r5900.
389 Disable 64 bit co processor instructions.
390 Disable 64 bit multiplication and division instructions.
391 Disable instructions for co-processor 2 and 3, because these are
392 not supported (preparation for later VU0 support (Vector Unit)).
393 Disable cvt.w.s because this behaves like trunc.w.s and the
394 correct execution can't be ensured on r5900.
395 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
396 will confuse less developers and compilers.
398 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
400 * aarch64-opc.c (aarch64_print_operand): Change to print
401 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
403 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
404 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
407 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
409 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
410 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
412 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
414 * i386-gen.c (process_copyright): Update copyright year to 2013.
416 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
418 * cr16-dis.c (match_opcode,make_instruction): Remove static
420 (dwordU,wordU): Moved typedefs to opcode/cr16.h
421 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
423 For older changes see ChangeLog-2012
425 Copyright (C) 2013 Free Software Foundation, Inc.
427 Copying and distribution of this file, with or without modification,
428 are permitted in any medium without royalty provided the copyright
429 notice and this notice are preserved.
435 version-control: never