1 2008-08-04 Alan Modra <amodra@bigpond.net.au>
3 * Makefile.am (POTFILES.in): Set LC_ALL=C.
4 * Makefile.in: Regenerate.
5 * po/POTFILES.in: Regenerate.
7 2008-08-01 Peter Bergner <bergner@vnet.ibm.com>
9 * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options.
10 (print_insn_powerpc): Prepend 'vs' when printing VSX registers.
11 (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx.
12 * ppc-opc.c (insert_xt6): New static function.
13 (extract_xt6): Likewise.
14 (insert_xa6): Likewise.
15 (extract_xa6: Likewise.
16 (insert_xb6): Likewise.
17 (extract_xb6): Likewise.
18 (insert_xb6s): Likewise.
19 (extract_xb6s): Likewise.
20 (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK,
21 XX3DM_MASK, PPCVSX): New.
22 (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x",
23 "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".
25 2008-08-01 Pedro Alves <pedro@codesourcery.com>
27 * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation.
28 * Makefile.in: Regenerate.
30 2008-08-01 H.J. Lu <hongjiu.lu@intel.com>
32 * i386-reg.tbl: Use Dw2Inval on AVX registers.
33 * i386-tbl.h: Regenerated.
35 2008-07-30 Michael J. Eager <eager@eagercon.com>
37 * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields.
38 * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands.
39 (insert_sprg, PPC405): Use PPC_OPCODE_405.
40 (powerpc_opcodes): Add Xilinx APU related opcodes.
42 2008-07-30 Alan Modra <amodra@bigpond.net.au>
44 * bfin-dis.c, cris-dis.c, i386-dis.c, or32-opc.c: Silence gcc warnings.
46 2008-07-10 Richard Sandiford <rdsandiford@googlemail.com>
48 * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16.
50 2008-07-07 Adam Nemet <anemet@caviumnetworks.com>
52 * mips-opc.c (CP): New macro.
53 (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the
54 membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and
55 dmtc2 Octeon instructions.
57 2008-07-07 Stan Shebs <stan@codesourcery.com>
59 * dis-init.c (init_disassemble_info): Init endian_code field.
60 * arm-dis.c (print_insn): Disassemble code according to
61 setting of endian_code.
62 (print_insn_big_arm): Detect when BE8 extension flag has been set.
64 2008-06-30 Richard Sandiford <rdsandiford@googlemail.com>
66 * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check
69 2008-06-25 Peter Bergner <bergner@vnet.ibm.com>
71 * ppc-dis.c (powerpc_init_dialect): Handle -M464.
72 (print_ppc_disassembler_options): Likewise.
73 * ppc-opc.c (PPC464): Define.
74 (powerpc_opcodes): Add mfdcrux and mtdcrux.
76 2008-06-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
78 * configure: Regenerate.
80 2008-06-13 Peter Bergner <bergner@vnet.ibm.com>
82 * ppc-dis.c (print_insn_powerpc): Update prototye to use new
84 (struct dis_private): New.
85 (POWERPC_DIALECT): New define.
86 (powerpc_dialect): Renamed to...
87 (powerpc_init_dialect): This. Update to use ppc_cpu_t and
89 (print_insn_big_powerpc): Update for using structure in
91 (print_insn_little_powerpc): Likewise.
92 (operand_value_powerpc): Change type of dialect param to ppc_cpu_t.
93 (skip_optional_operands): Likewise.
94 (print_insn_powerpc): Likewise. Remove initialization of dialect.
95 * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp,
96 extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe,
97 extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr,
98 extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm,
99 insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe,
100 insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs,
101 insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect
102 param to be of type ppc_cpu_t. Update prototype.
104 2008-06-12 Adam Nemet <anemet@caviumnetworks.com>
106 * mips-dis.c (print_insn_args): Handle field descriptors +x, +p,
108 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions
109 baddu, bbit*, cins*, dmul, pop, dpop, exts*, mtm*, mtp*, syncs,
110 syncw, syncws, vm3mulu, vm0 and vmulu.
112 * mips-dis.c (print_insn_args): Handle field descriptor +Q.
113 * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq,
116 2008-05-30 H.J. Lu <hongjiu.lu@intel.com>
118 * i386-opc.tbl: Add vmovd with 64bit operand.
119 * i386-tbl.h: Regenerated.
121 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com>
123 * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format.
125 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi.
128 * i386-tbl.h: Regenerated.
130 2008-05-22 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss
134 into 32bit and 64bit. Remove Reg64|Qword and add
135 IgnoreSize|No_qSuf on 32bit version.
136 * i386-tbl.h: Regenerated.
138 2008-05-21 H.J. Lu <hongjiu.lu@intel.com>
140 * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq.
141 * i386-tbl.h: Regenerated.
143 2008-05-21 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
145 * cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.
147 2008-05-14 Alan Modra <amodra@bigpond.net.au>
149 * Makefile.am: Run "make dep-am".
150 * Makefile.in: Regenerate.
152 2008-05-02 H.J. Lu <hongjiu.lu@intel.com>
154 * i386-dis.c (MOVBE_Fixup): New.
156 (PREFIX_0F3880): Likewise.
157 (PREFIX_0F3881): Likewise.
158 (PREFIX_0F38F0): Updated.
159 (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update
160 PREFIX_0F38F0 and PREFIX_0F38F1 for movbe.
161 (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881.
163 * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and
165 (cpu_flags): Add CpuMovbe and CpuEPT.
167 * i386-opc.h (CpuMovbe): New.
170 (i386_cpu_flags): Add cpumovbe and cpuept.
172 * i386-opc.tbl: Add entries for movbe and EPT instructions.
173 * i386-init.h: Regenerated.
174 * i386-tbl.h: Likewise.
176 2008-04-29 Adam Nemet <anemet@caviumnetworks.com>
178 * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
179 the two drem and the two dremu macros.
181 2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
183 * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1
184 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and
185 cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros
186 INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.
188 2008-04-25 David S. Miller <davem@davemloft.net>
190 * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr
191 instead of %sys_tick_cmpr, as suggested in architecture manuals.
193 2008-04-23 Paolo Bonzini <bonzini@gnu.org>
195 * aclocal.m4: Regenerate.
196 * configure: Regenerate.
198 2008-04-23 David S. Miller <davem@davemloft.net>
200 * sparc-opc.c (asi_table): Add UltraSPARC and Niagara
202 (prefetch_table): Add missing values.
204 2008-04-22 H.J. Lu <hongjiu.lu@intel.com>
206 * i386-gen.c (opcode_modifiers): Add NoAVX.
208 * i386-opc.h (NoAVX): New.
210 (i386_opcode_modifier): Add noavx.
212 * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3
213 instructions which don't have AVX equivalent.
214 * i386-tbl.h: Regenerated.
216 2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
218 * i386-dis.c (OP_VEX_FMA): New.
219 (OP_EX_VexImmW): Likewise.
221 (Vex128FMA): Likewise.
222 (EXVexImmW): Likewise.
223 (get_vex_imm8): Likewise.
224 (OP_EX_VexReg): Likewise.
225 (vex_i4_done): Renamed to ...
227 (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
228 and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
230 (print_insn): Updated.
231 (OP_EX_VexW): Rewrite to swap register in VEX with EX.
232 (OP_REG_VexI4): Check invalid high registers.
234 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
235 Michael Meissner <michael.meissner@amd.com>
237 * i386-opc.tbl: Fix protX to allow memory in the middle operand.
238 * i386-tbl.h: Regenerate from i386-opc.tbl.
240 2008-04-14 Edmar Wienskoski <edmar@freescale.com>
242 * ppc-dis.c (powerpc_dialect): Handle "e500mc". Extend "e500" to
243 accept Power E500MC instructions.
244 (print_ppc_disassembler_options): Document -Me500mc.
245 * ppc-opc.c (DUIS, DUI, T): New.
246 (XRT, XRTRA): Likewise.
248 (powerpc_opcodes): Add new Power E500MC instructions.
250 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
252 * s390-dis.c (init_disasm): Evaluate disassembler_options.
253 (print_s390_disassembler_options): New function.
254 * disassemble.c (disassembler_usage): Invoke
255 print_s390_disassembler_options.
257 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
259 * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes
260 of local variables used for mnemonic parsing: prefix, suffix and
263 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com>
265 * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic
266 extensions for conditional jumps (o, p, m, nz, z, nm, np, no).
267 (s390_crb_extensions): New extensions table.
268 (insertExpandedMnemonic): Handle '$' tag.
269 * s390-opc.txt: Remove conditional jump variants which can now
270 be expanded automatically.
271 Replace '*' tag with '$' in the compare and branch instructions.
273 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
275 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
276 (PREFIX_VEX_3AXX): Likewis.
278 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
280 * i386-opc.tbl: Remove 4 extra blank lines.
282 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
284 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
285 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
286 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
287 * i386-opc.tbl: Likewise.
289 * i386-opc.h (CpuCLMUL): Renamed to ...
292 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
294 * i386-init.h: Regenerated.
296 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
298 * i386-dis.c (OP_E_register): New.
299 (OP_E_memory): Likewise.
301 (OP_EX_Vex): Likewise.
302 (OP_EX_VexW): Likewise.
303 (OP_XMM_Vex): Likewise.
304 (OP_XMM_VexW): Likewise.
305 (OP_REG_VexI4): Likewise.
306 (PCLMUL_Fixup): Likewise.
307 (VEXI4_Fixup): Likewise.
308 (VZERO_Fixup): Likewise.
309 (VCMP_Fixup): Likewise.
310 (VPERMIL2_Fixup): Likewise.
311 (rex_original): Likewise.
312 (rex_ignored): Likewise.
333 (VPERMIL2): Likewise.
334 (xmm_mode): Likewise.
335 (xmmq_mode): Likewise.
336 (ymmq_mode): Likewise.
337 (vex_mode): Likewise.
338 (vex128_mode): Likewise.
339 (vex256_mode): Likewise.
340 (USE_VEX_C4_TABLE): Likewise.
341 (USE_VEX_C5_TABLE): Likewise.
342 (USE_VEX_LEN_TABLE): Likewise.
343 (VEX_C4_TABLE): Likewise.
344 (VEX_C5_TABLE): Likewise.
345 (VEX_LEN_TABLE): Likewise.
346 (REG_VEX_XX): Likewise.
347 (MOD_VEX_XXX): Likewise.
348 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
349 (PREFIX_0F3A44): Likewise.
350 (PREFIX_0F3ADF): Likewise.
351 (PREFIX_VEX_XXX): Likewise.
353 (VEX_OF38): Likewise.
354 (VEX_OF3A): Likewise.
355 (VEX_LEN_XXX): Likewise.
357 (need_vex): Likewise.
358 (need_vex_reg): Likewise.
359 (vex_i4_done): Likewise.
360 (vex_table): Likewise.
361 (vex_len_table): Likewise.
362 (OP_REG_VexI4): Likewise.
363 (vex_cmp_op): Likewise.
364 (pclmul_op): Likewise.
365 (vpermil2_op): Likewise.
368 (PREFIX_0F38F0): Likewise.
369 (PREFIX_0F3A60): Likewise.
370 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
371 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
372 and PREFIX_VEX_XXX entries.
373 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
374 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
376 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
377 Add MOD_VEX_XXX entries.
378 (ckprefix): Initialize rex_original and rex_ignored. Store the
379 REX byte in rex_original.
380 (get_valid_dis386): Handle the implicit prefix in VEX prefix
381 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
382 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
383 calling get_valid_dis386. Use rex_original and rex_ignored when
385 (putop): Handle "XY".
386 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
388 (OP_E_extended): Updated to use OP_E_register and
390 (OP_XMM): Handle VEX.
392 (XMM_Fixup): Likewise.
393 (CMP_Fixup): Use ARRAY_SIZE.
395 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
396 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
397 (operand_type_init): Add OPERAND_TYPE_REGYMM and
398 OPERAND_TYPE_VEX_IMM4.
399 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
400 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
401 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
402 VexImmExt and SSE2AVX.
403 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
405 * i386-opc.h (CpuAVX): New.
407 (CpuCLMUL): Likewise.
418 (Vex3Sources): Likewise.
419 (VexImmExt): Likewise.
423 (Vex_Imm4): Likewise.
424 (Implicit1stXmm0): Likewise.
427 (ByteOkIntel): Likewise.
430 (Unspecified): Likewise.
432 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
433 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
434 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
435 vex3sources, veximmext and sse2avx.
436 (i386_operand_type): Add regymm, ymmword and vex_imm4.
438 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
440 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
442 * i386-init.h: Regenerated.
443 * i386-tbl.h: Likewise.
445 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
447 From Robin Getz <robin.getz@analog.com>
448 * bfin-dis.c (bu32): Typedef.
449 (enum const_forms_t): Add c_uimm32 and c_huimm32.
450 (constant_formats[]): Add uimm32 and huimm16.
455 (luimm16_val): Define.
456 (struct saved_state): Define.
457 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
458 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
459 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
461 (decode_LDIMMhalf_0): Print out the whole register value.
463 From Jie Zhang <jie.zhang@analog.com>
464 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
465 multiply and multiply-accumulate to data register instruction.
467 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
468 c_imm32, c_huimm32e): Define.
469 (constant_formats): Add flags for printing decimal, leading spaces, and
471 (comment, parallel): Add global flags in all disassembly.
472 (fmtconst): Take advantage of new flags, and print default in hex.
473 (fmtconst_val): Likewise.
474 (decode_macfunc): Be consistant with spaces, tabs, comments,
475 capitalization in disassembly, fix minor coding style issues.
476 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
477 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
478 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
479 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
480 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
481 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
482 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
483 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
484 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
485 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
486 _print_insn_bfin, print_insn_bfin): Likewise.
488 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
490 * aclocal.m4: Regenerate.
491 * configure: Likewise.
492 * Makefile.in: Likewise.
494 2008-03-13 Alan Modra <amodra@bigpond.net.au>
496 * Makefile.am: Run "make dep-am".
497 * Makefile.in: Regenerate.
498 * configure: Regenerate.
500 2008-03-07 Alan Modra <amodra@bigpond.net.au>
502 * ppc-opc.c (powerpc_opcodes): Order and format.
504 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
507 * i386-tbl.h: Regenerated.
509 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
511 * i386-opc.tbl: Disallow 16-bit near indirect branches for
513 * i386-tbl.h: Regenerated.
515 2008-02-21 Jan Beulich <jbeulich@novell.com>
517 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
518 and Fword for far indirect jmp. Allow Reg16 and Word for near
519 indirect jmp on x86-64. Disallow Fword for lcall.
520 * i386-tbl.h: Re-generate.
522 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
524 * cr16-opc.c (cr16_num_optab): Defined
526 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
528 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
529 * i386-init.h: Regenerated.
531 2008-02-14 Nick Clifton <nickc@redhat.com>
534 * configure.in (SHARED_LIBADD): Select the correct host specific
535 file extension for shared libraries.
536 * configure: Regenerate.
538 2008-02-13 Jan Beulich <jbeulich@novell.com>
540 * i386-opc.h (RegFlat): New.
541 * i386-reg.tbl (flat): Add.
542 * i386-tbl.h: Re-generate.
544 2008-02-13 Jan Beulich <jbeulich@novell.com>
546 * i386-dis.c (a_mode): New.
547 (cond_jump_mode): Adjust.
548 (Ma): Change to a_mode.
549 (intel_operand_size): Handle a_mode.
550 * i386-opc.tbl: Allow Dword and Qword for bound.
551 * i386-tbl.h: Re-generate.
553 2008-02-13 Jan Beulich <jbeulich@novell.com>
555 * i386-gen.c (process_i386_registers): Process new fields.
556 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
557 unsigned char. Add dw2_regnum and Dw2Inval.
558 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
560 * i386-tbl.h: Re-generate.
562 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
564 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
565 * i386-init.h: Updated.
567 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
569 * i386-gen.c (cpu_flags): Add CpuXsave.
571 * i386-opc.h (CpuXsave): New.
573 (i386_cpu_flags): Add cpuxsave.
575 * i386-dis.c (MOD_0FAE_REG_4): New.
576 (RM_0F01_REG_2): Likewise.
577 (MOD_0FAE_REG_5): Updated.
578 (RM_0F01_REG_3): Likewise.
579 (reg_table): Use MOD_0FAE_REG_4.
580 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
582 (rm_table): Add RM_0F01_REG_2.
584 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
585 * i386-init.h: Regenerated.
586 * i386-tbl.h: Likewise.
588 2008-02-11 Jan Beulich <jbeulich@novell.com>
590 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
591 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
592 * i386-tbl.h: Re-generate.
594 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
597 * configure: Regenerated.
599 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
601 * mips-dis.c: Update copyright.
602 (mips_arch_choices): Add Octeon.
603 * mips-opc.c: Update copyright.
605 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
607 2008-01-29 Alan Modra <amodra@bigpond.net.au>
609 * ppc-opc.c: Support optional L form mtmsr.
611 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
613 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
615 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
617 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
618 * i386-init.h: Regenerated.
620 2008-01-23 Tristan Gingold <gingold@adacore.com>
622 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
623 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
625 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
627 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
628 (cpu_flags): Likewise.
630 * i386-opc.h (CpuMMX2): Removed.
633 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
634 * i386-init.h: Regenerated.
635 * i386-tbl.h: Likewise.
637 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
639 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
641 * i386-init.h: Regenerated.
643 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
645 * i386-opc.tbl: Use Qword on movddup.
646 * i386-tbl.h: Regenerated.
648 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
650 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
651 * i386-tbl.h: Regenerated.
653 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
655 * i386-dis.c (Mx): New.
656 (PREFIX_0FC3): Likewise.
657 (PREFIX_0FC7_REG_6): Updated.
658 (dis386_twobyte): Use PREFIX_0FC3.
659 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
660 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
663 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
665 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
666 (operand_types): Add Mem.
668 * i386-opc.h (IntelSyntax): New.
669 * i386-opc.h (Mem): New.
671 (Opcode_Modifier_Max): Updated.
672 (i386_opcode_modifier): Add intelsyntax.
673 (i386_operand_type): Add mem.
675 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
678 * i386-reg.tbl: Add size for accumulator.
680 * i386-init.h: Regenerated.
681 * i386-tbl.h: Likewise.
683 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
685 * i386-opc.h (Byte): Fix a typo.
687 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
690 * i386-gen.c (operand_type_init): Add Dword to
691 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
692 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
694 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
695 Xmmword, Unspecified and Anysize.
696 (set_bitfield): Make Mmword an alias of Qword. Make Oword
699 * i386-opc.h (CheckSize): Removed.
707 (i386_opcode_modifier): Remove checksize, byte, word, dword,
711 (Unspecified): Likewise.
713 (i386_operand_type): Add byte, word, dword, fword, qword,
714 tbyte xmmword, unspecified and anysize.
716 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
717 Tbyte, Xmmword, Unspecified and Anysize.
719 * i386-reg.tbl: Add size for accumulator.
721 * i386-init.h: Regenerated.
722 * i386-tbl.h: Likewise.
724 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
726 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
728 (reg_table): Updated.
729 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
730 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
732 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
734 * i386-gen.c (set_bitfield): Use fail () on error.
736 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
738 * i386-gen.c (lineno): New.
739 (filename): Likewise.
740 (set_bitfield): Report filename and line numer on error.
741 (process_i386_opcodes): Set filename and update lineno.
742 (process_i386_registers): Likewise.
744 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
746 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
749 * i386-opc.h (IntelMnemonic): Renamed to ..
751 (Opcode_Modifier_Max): Updated.
752 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
755 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
756 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
757 * i386-tbl.h: Regenerated.
759 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
761 * i386-gen.c: Update copyright to 2008.
762 * i386-opc.h: Likewise.
763 * i386-opc.tbl: Likewise.
765 * i386-init.h: Regenerated.
766 * i386-tbl.h: Likewise.
768 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
770 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
771 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
772 * i386-tbl.h: Regenerated.
774 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
776 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
778 (cpu_flags): Likewise.
780 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
781 (CpuSSE4_2_Or_ABM): Likewise.
783 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
785 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
786 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
787 and CpuPadLock, respectively.
788 * i386-init.h: Regenerated.
789 * i386-tbl.h: Likewise.
791 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
793 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
795 * i386-opc.h (No_xSuf): Removed.
796 (CheckSize): Updated.
798 * i386-tbl.h: Regenerated.
800 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
802 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
803 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
805 (cpu_flags): Add CpuSSE4_2_Or_ABM.
807 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
809 (i386_cpu_flags): Add cpusse4_2_or_abm.
811 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
812 CpuABM|CpuSSE4_2 on popcnt.
813 * i386-init.h: Regenerated.
814 * i386-tbl.h: Likewise.
816 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
818 * i386-opc.h: Update comments.
820 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
822 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
823 * i386-opc.h: Likewise.
824 * i386-opc.tbl: Likewise.
826 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
829 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
830 Byte, Word, Dword, QWord and Xmmword.
832 * i386-opc.h (No_xSuf): New.
833 (CheckSize): Likewise.
840 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
841 Dword, QWord and Xmmword.
843 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
845 * i386-tbl.h: Regenerated.
847 2008-01-02 Mark Kettenis <kettenis@gnu.org>
849 * m88k-dis.c (instructions): Fix fcvt.* instructions.
852 For older changes see ChangeLog-2007
858 version-control: never