1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-asm-2.c: Regenerated.
4 * aarch64-dis-2.c: Regenerated.
5 * aarch64-opc-2.c: Regenerated.
6 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
7 for SVE_SHLIMM_UNPRED_22.
8 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
9 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
12 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
14 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
15 sve_size_tsz_bhs iclass encode.
16 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
17 sve_size_tsz_bhs iclass decode.
19 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
21 * aarch64-asm-2.c: Regenerated.
22 * aarch64-dis-2.c: Regenerated.
23 * aarch64-opc-2.c: Regenerated.
24 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
26 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
27 (fields): Handle SVE_i2h field.
28 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
29 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
31 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
33 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
34 sve_shift_tsz_bhsd iclass encode.
35 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
36 sve_shift_tsz_bhsd iclass decode.
38 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
40 * aarch64-asm-2.c: Regenerated.
41 * aarch64-dis-2.c: Regenerated.
42 * aarch64-opc-2.c: Regenerated.
43 * aarch64-asm.c (aarch64_ins_sve_shrimm):
44 (aarch64_encode_variant_using_iclass): Handle
45 sve_shift_tsz_hsd iclass encode.
46 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
47 sve_shift_tsz_hsd iclass decode.
48 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
49 for SVE_SHRIMM_UNPRED_22.
50 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
51 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
54 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
56 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
57 sve_size_013 iclass encode.
58 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
59 sve_size_013 iclass decode.
61 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
63 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
64 sve_size_bh iclass encode.
65 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
66 sve_size_bh iclass decode.
68 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
70 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
71 sve_size_sd2 iclass encode.
72 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
73 sve_size_sd2 iclass decode.
74 * aarch64-opc.c (fields): Handle SVE_sz2 field.
75 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
77 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
79 * aarch64-asm-2.c: Regenerated.
80 * aarch64-dis-2.c: Regenerated.
81 * aarch64-opc-2.c: Regenerated.
82 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
84 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
85 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
87 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
89 * aarch64-asm-2.c: Regenerated.
90 * aarch64-dis-2.c: Regenerated.
91 * aarch64-opc-2.c: Regenerated.
92 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
94 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
95 (fields): Handle SVE_i3l and SVE_i3h2 fields.
96 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
98 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
100 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
102 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
103 sve_size_hsd2 iclass encode.
104 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
105 sve_size_hsd2 iclass decode.
106 * aarch64-opc.c (fields): Handle SVE_size field.
107 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
109 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
111 * aarch64-asm-2.c: Regenerated.
112 * aarch64-dis-2.c: Regenerated.
113 * aarch64-opc-2.c: Regenerated.
114 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
116 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
117 (fields): Handle SVE_rot3 field.
118 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
119 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
121 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
123 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
126 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
129 (aarch64_feature_sve2, aarch64_feature_sve2aes,
130 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
131 aarch64_feature_sve2bitperm): New feature sets.
132 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
133 for feature set addresses.
134 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
135 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
137 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
138 Faraz Shahbazker <fshahbazker@wavecomp.com>
140 * mips-dis.c (mips_calculate_combination_ases): Add ISA
141 argument and set ASE_EVA_R6 appropriately.
142 (set_default_mips_dis_options): Pass ISA to above.
143 (parse_mips_dis_option): Likewise.
144 * mips-opc.c (EVAR6): New macro.
145 (mips_builtin_opcodes): Add llwpe, scwpe.
147 2019-05-01 Sudakshina Das <sudi.das@arm.com>
149 * aarch64-asm-2.c: Regenerated.
150 * aarch64-dis-2.c: Regenerated.
151 * aarch64-opc-2.c: Regenerated.
152 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
153 AARCH64_OPND_TME_UIMM16.
154 (aarch64_print_operand): Likewise.
155 * aarch64-tbl.h (QL_IMM_NIL): New.
158 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
160 2019-04-29 John Darrington <john@darrington.wattle.id.au>
162 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
164 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
165 Faraz Shahbazker <fshahbazker@wavecomp.com>
167 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
169 2019-04-24 John Darrington <john@darrington.wattle.id.au>
171 * s12z-opc.h: Add extern "C" bracketing to help
172 users who wish to use this interface in c++ code.
174 2019-04-24 John Darrington <john@darrington.wattle.id.au>
176 * s12z-opc.c (bm_decode): Handle bit map operations with the
179 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
181 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
182 specifier. Add entries for VLDR and VSTR of system registers.
183 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
184 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
185 of %J and %K format specifier.
187 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
189 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
190 Add new entries for VSCCLRM instruction.
191 (print_insn_coprocessor): Handle new %C format control code.
193 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
195 * arm-dis.c (enum isa): New enum.
196 (struct sopcode32): New structure.
197 (coprocessor_opcodes): change type of entries to struct sopcode32 and
198 set isa field of all current entries to ANY.
199 (print_insn_coprocessor): Change type of insn to struct sopcode32.
200 Only match an entry if its isa field allows the current mode.
202 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
204 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
206 (print_insn_thumb32): Add logic to print %n CLRM register list.
208 2019-04-15 Sudakshina Das <sudi.das@arm.com>
210 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
213 2019-04-15 Sudakshina Das <sudi.das@arm.com>
215 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
216 (print_insn_thumb32): Edit the switch case for %Z.
218 2019-04-15 Sudakshina Das <sudi.das@arm.com>
220 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
222 2019-04-15 Sudakshina Das <sudi.das@arm.com>
224 * arm-dis.c (thumb32_opcodes): New instruction bfl.
226 2019-04-15 Sudakshina Das <sudi.das@arm.com>
228 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
230 2019-04-15 Sudakshina Das <sudi.das@arm.com>
232 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
233 Arm register with r13 and r15 unpredictable.
234 (thumb32_opcodes): New instructions for bfx and bflx.
236 2019-04-15 Sudakshina Das <sudi.das@arm.com>
238 * arm-dis.c (thumb32_opcodes): New instructions for bf.
240 2019-04-15 Sudakshina Das <sudi.das@arm.com>
242 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
244 2019-04-15 Sudakshina Das <sudi.das@arm.com>
246 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
248 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
250 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
252 2019-04-12 John Darrington <john@darrington.wattle.id.au>
254 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
255 "optr". ("operator" is a reserved word in c++).
257 2019-04-11 Sudakshina Das <sudi.das@arm.com>
259 * aarch64-opc.c (aarch64_print_operand): Add case for
261 (verify_constraints): Likewise.
262 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
263 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
264 to accept Rt|SP as first operand.
265 (AARCH64_OPERANDS): Add new Rt_SP.
266 * aarch64-asm-2.c: Regenerated.
267 * aarch64-dis-2.c: Regenerated.
268 * aarch64-opc-2.c: Regenerated.
270 2019-04-11 Sudakshina Das <sudi.das@arm.com>
272 * aarch64-asm-2.c: Regenerated.
273 * aarch64-dis-2.c: Likewise.
274 * aarch64-opc-2.c: Likewise.
275 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
277 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
279 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
281 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
283 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
284 * i386-init.h: Regenerated.
286 2019-04-07 Alan Modra <amodra@gmail.com>
288 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
289 op_separator to control printing of spaces, comma and parens
290 rather than need_comma, need_paren and spaces vars.
292 2019-04-07 Alan Modra <amodra@gmail.com>
295 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
296 (print_insn_neon, print_insn_arm): Likewise.
298 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
300 * i386-dis-evex.h (evex_table): Updated to support BF16
302 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
303 and EVEX_W_0F3872_P_3.
304 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
305 (cpu_flags): Add bitfield for CpuAVX512_BF16.
306 * i386-opc.h (enum): Add CpuAVX512_BF16.
307 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
308 * i386-opc.tbl: Add AVX512 BF16 instructions.
309 * i386-init.h: Regenerated.
310 * i386-tbl.h: Likewise.
312 2019-04-05 Alan Modra <amodra@gmail.com>
314 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
315 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
316 to favour printing of "-" branch hint when using the "y" bit.
317 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
319 2019-04-05 Alan Modra <amodra@gmail.com>
321 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
322 opcode until first operand is output.
324 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
327 * ppc-opc.c (valid_bo_pre_v2): Add comments.
328 (valid_bo_post_v2): Add support for 'at' branch hints.
329 (insert_bo): Only error on branch on ctr.
330 (get_bo_hint_mask): New function.
331 (insert_boe): Add new 'branch_taken' formal argument. Add support
332 for inserting 'at' branch hints.
333 (extract_boe): Add new 'branch_taken' formal argument. Add support
334 for extracting 'at' branch hints.
335 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
336 (BOE): Delete operand.
337 (BOM, BOP): New operands.
339 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
340 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
341 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
342 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
343 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
344 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
345 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
346 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
347 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
348 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
349 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
350 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
351 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
352 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
353 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
354 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
355 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
356 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
357 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
358 bttarl+>: New extended mnemonics.
360 2019-03-28 Alan Modra <amodra@gmail.com>
363 * ppc-opc.c (BTF): Define.
364 (powerpc_opcodes): Use for mtfsb*.
365 * ppc-dis.c (print_insn_powerpc): Print fields with both
366 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
368 2019-03-25 Tamar Christina <tamar.christina@arm.com>
370 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
371 (mapping_symbol_for_insn): Implement new algorithm.
372 (print_insn): Remove duplicate code.
374 2019-03-25 Tamar Christina <tamar.christina@arm.com>
376 * aarch64-dis.c (print_insn_aarch64):
379 2019-03-25 Tamar Christina <tamar.christina@arm.com>
381 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
384 2019-03-25 Tamar Christina <tamar.christina@arm.com>
386 * aarch64-dis.c (last_stop_offset): New.
387 (print_insn_aarch64): Use stop_offset.
389 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
392 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
394 * i386-init.h: Regenerated.
396 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
399 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
400 vmovdqu16, vmovdqu32 and vmovdqu64.
401 * i386-tbl.h: Regenerated.
403 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
405 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
406 from vstrszb, vstrszh, and vstrszf.
408 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
410 * s390-opc.txt: Add instruction descriptions.
412 2019-02-08 Jim Wilson <jimw@sifive.com>
414 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
417 2019-02-07 Tamar Christina <tamar.christina@arm.com>
419 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
421 2019-02-07 Tamar Christina <tamar.christina@arm.com>
424 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
425 * aarch64-opc.c (verify_elem_sd): New.
426 (fields): Add FLD_sz entr.
427 * aarch64-tbl.h (_SIMD_INSN): New.
428 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
429 fmulx scalar and vector by element isns.
431 2019-02-07 Nick Clifton <nickc@redhat.com>
433 * po/sv.po: Updated Swedish translation.
435 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
437 * s390-mkopc.c (main): Accept arch13 as cpu string.
438 * s390-opc.c: Add new instruction formats and instruction opcode
440 * s390-opc.txt: Add new arch13 instructions.
442 2019-01-25 Sudakshina Das <sudi.das@arm.com>
444 * aarch64-tbl.h (QL_LDST_AT): Update macro.
445 (aarch64_opcode): Change encoding for stg, stzg
447 * aarch64-asm-2.c: Regenerated.
448 * aarch64-dis-2.c: Regenerated.
449 * aarch64-opc-2.c: Regenerated.
451 2019-01-25 Sudakshina Das <sudi.das@arm.com>
453 * aarch64-asm-2.c: Regenerated.
454 * aarch64-dis-2.c: Likewise.
455 * aarch64-opc-2.c: Likewise.
456 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
458 2019-01-25 Sudakshina Das <sudi.das@arm.com>
459 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
461 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
462 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
463 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
464 * aarch64-dis.h (ext_addr_simple_2): Likewise.
465 * aarch64-opc.c (operand_general_constraint_met_p): Remove
466 case for ldstgv_indexed.
467 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
468 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
469 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
470 * aarch64-asm-2.c: Regenerated.
471 * aarch64-dis-2.c: Regenerated.
472 * aarch64-opc-2.c: Regenerated.
474 2019-01-23 Nick Clifton <nickc@redhat.com>
476 * po/pt_BR.po: Updated Brazilian Portuguese translation.
478 2019-01-21 Nick Clifton <nickc@redhat.com>
480 * po/de.po: Updated German translation.
481 * po/uk.po: Updated Ukranian translation.
483 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
484 * mips-dis.c (mips_arch_choices): Fix typo in
485 gs464, gs464e and gs264e descriptors.
487 2019-01-19 Nick Clifton <nickc@redhat.com>
489 * configure: Regenerate.
490 * po/opcodes.pot: Regenerate.
492 2018-06-24 Nick Clifton <nickc@redhat.com>
496 2019-01-09 John Darrington <john@darrington.wattle.id.au>
498 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
500 -dis.c (opr_emit_disassembly): Do not omit an index if it is
503 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
505 * configure: Regenerate.
507 2019-01-07 Alan Modra <amodra@gmail.com>
509 * configure: Regenerate.
510 * po/POTFILES.in: Regenerate.
512 2019-01-03 John Darrington <john@darrington.wattle.id.au>
514 * s12z-opc.c: New file.
515 * s12z-opc.h: New file.
516 * s12z-dis.c: Removed all code not directly related to display
517 of instructions. Used the interface provided by the new files
519 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
520 * Makefile.in: Regenerate.
521 * configure.ac (bfd_s12z_arch): Correct the dependencies.
522 * configure: Regenerate.
524 2019-01-01 Alan Modra <amodra@gmail.com>
526 Update year range in copyright notice of all files.
528 For older changes see ChangeLog-2018
530 Copyright (C) 2019 Free Software Foundation, Inc.
532 Copying and distribution of this file, with or without modification,
533 are permitted in any medium without royalty provided the copyright
534 notice and this notice are preserved.
540 version-control: never