1 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
5 * mips16-opc.c (mips16_opcodes): Likewise.
6 * micromips-opc.c (micromips_opcodes): Likewise.
7 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
8 (print_insn_mips16): Handle "+i".
9 (print_insn_micromips): Likewise. Conditionally preserve the
10 ISA bit for "a" but not for "+i".
12 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
14 * micromips-opc.c (WR_mhi): Rename to..
16 (micromips_opcodes): Update "movep" entry accordingly. Replace
18 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
19 (micromips_to_32_reg_h_map1): ...this.
20 (micromips_to_32_reg_i_map): Rename to...
21 (micromips_to_32_reg_h_map2): ...this.
22 (print_micromips_insn): Remove "mi" case. Print both registers
25 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
27 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
28 * micromips-opc.c (micromips_opcodes): Likewise.
29 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
30 and "+T" handling. Check for a "0" suffix when deciding whether to
31 use coprocessor 0 names. In that case, also check for ",H" selectors.
33 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
35 * s390-opc.c (J12_12, J24_24): New macros.
36 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
37 (MASK_MII_UPI): Rename to MASK_MII_UPP.
38 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
40 2013-07-04 Alan Modra <amodra@gmail.com>
42 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
44 2013-06-26 Nick Clifton <nickc@redhat.com>
46 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
47 field when checking for type 2 nop.
48 * rx-decode.c: Regenerate.
50 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
52 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
55 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
57 * mips-dis.c (is_mips16_plt_tail): New function.
58 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
60 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
62 2013-06-21 DJ Delorie <dj@redhat.com>
64 * msp430-decode.opc: New.
65 * msp430-decode.c: New/generated.
66 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
67 (MAINTAINER_CLEANFILES): Likewise.
68 Add rule to build msp430-decode.c frommsp430decode.opc
69 using the opc2c program.
70 * Makefile.in: Regenerate.
71 * configure.in: Add msp430-decode.lo to msp430 architecture files.
72 * configure: Regenerate.
74 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
76 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
77 (SYMTAB_AVAILABLE): Removed.
78 (#include "elf/aarch64.h): Ditto.
80 2013-06-17 Catherine Moore <clm@codesourcery.com>
81 Maciej W. Rozycki <macro@codesourcery.com>
82 Chao-Ying Fu <fu@mips.com>
84 * micromips-opc.c (EVA): Define.
86 (micromips_opcodes): Add EVA opcodes.
87 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
88 (print_insn_args): Handle EVA offsets.
89 (print_insn_micromips): Likewise.
90 * mips-opc.c (EVA): Define.
92 (mips_builtin_opcodes): Add EVA opcodes.
94 2013-06-17 Alan Modra <amodra@gmail.com>
96 * Makefile.am (mips-opc.lo): Add rules to create automatic
97 dependency files. Pass archdefs.
98 (micromips-opc.lo, mips16-opc.lo): Likewise.
99 * Makefile.in: Regenerate.
101 2013-06-14 DJ Delorie <dj@redhat.com>
103 * rx-decode.opc (rx_decode_opcode): Bit operations on
104 registers are 32-bit operations, not 8-bit operations.
105 * rx-decode.c: Regenerate.
107 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
109 * micromips-opc.c (IVIRT): New define.
110 (IVIRT64): New define.
111 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
112 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
114 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
115 dmtgc0 to print cp0 names.
117 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
119 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
122 2013-06-08 Catherine Moore <clm@codesourcery.com>
123 Richard Sandiford <rdsandiford@googlemail.com>
125 * micromips-opc.c (D32, D33, MC): Update definitions.
126 (micromips_opcodes): Initialize ase field.
127 * mips-dis.c (mips_arch_choice): Add ase field.
128 (mips_arch_choices): Initialize ase field.
129 (set_default_mips_dis_options): Declare and setup mips_ase.
130 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
131 MT32, MC): Update definitions.
132 (mips_builtin_opcodes): Initialize ase field.
134 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
136 * s390-opc.txt (flogr): Require a register pair destination.
138 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
140 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
143 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
145 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
147 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
149 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
150 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
151 XLS_MASK, PPCVSX2): New defines.
152 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
153 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
154 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
155 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
156 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
157 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
158 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
159 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
160 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
161 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
162 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
163 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
164 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
165 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
166 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
167 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
168 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
169 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
170 <lxvx, stxvx>: New extended mnemonics.
172 2013-05-17 Alan Modra <amodra@gmail.com>
174 * ia64-raw.tbl: Replace non-ASCII char.
175 * ia64-waw.tbl: Likewise.
176 * ia64-asmtab.c: Regenerate.
178 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
180 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
181 * i386-init.h: Regenerated.
183 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
185 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
186 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
187 check from [0, 255] to [-128, 255].
189 2013-05-09 Andrew Pinski <apinski@cavium.com>
191 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
192 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
193 (parse_mips_dis_option): Handle the virt option.
194 (print_insn_args): Handle "+J".
195 (print_mips_disassembler_options): Print out message about virt64.
196 * mips-opc.c (IVIRT): New define.
197 (IVIRT64): New define.
198 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
199 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
200 Move rfe to the bottom as it conflicts with tlbgp.
202 2013-05-09 Alan Modra <amodra@gmail.com>
204 * ppc-opc.c (extract_vlesi): Properly sign extend.
205 (extract_vlensi): Likewise. Comment reason for setting invalid.
207 2013-05-02 Nick Clifton <nickc@redhat.com>
209 * msp430-dis.c: Add support for MSP430X instructions.
211 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
213 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
216 2013-04-17 Wei-chen Wang <cole945@gmail.com>
219 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
221 (hash_insns_list): Likewise.
223 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
225 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
228 2013-04-08 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
231 * i386-tbl.h: Re-generate.
233 2013-04-06 David S. Miller <davem@davemloft.net>
235 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
236 of an opcode, prefer the one with F_PREFERRED set.
237 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
238 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
239 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
240 mark existing mnenomics as aliases. Add "cc" suffix to edge
241 instructions generating condition codes, mark existing mnenomics
242 as aliases. Add "fp" prefix to VIS compare instructions, mark
243 existing mnenomics as aliases.
245 2013-04-03 Nick Clifton <nickc@redhat.com>
247 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
248 destination address by subtracting the operand from the current
250 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
251 a positive value in the insn.
252 (extract_u16_loop): Do not negate the returned value.
253 (D16_LOOP): Add V850_INVERSE_PCREL flag.
255 (ceilf.sw): Remove duplicate entry.
256 (cvtf.hs): New entry.
262 (maddf.s): Restrict to E3V5 architectures.
264 (nmaddf.s): Likewise.
265 (nmsubf.s): Likewise.
267 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
269 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
271 (print_insn): Pass sizeflag to get_sib.
273 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
276 * tic6x-dis.c: Add support for displaying 16-bit insns.
278 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
281 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
282 individual msb and lsb halves in src1 & src2 fields. Discard the
283 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
284 follow what Ti SDK does in that case as any value in the src1
285 field yields the same output with SDK disassembler.
287 2013-03-12 Michael Eager <eager@eagercon.com>
289 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
291 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
293 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
295 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
297 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
299 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
301 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
303 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
305 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
306 (thumb32_opcodes): Likewise.
307 (print_insn_thumb32): Handle 'S' control char.
309 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
311 * lm32-desc.c: Regenerate.
313 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
315 * i386-reg.tbl (riz): Add RegRex64.
316 * i386-tbl.h: Regenerated.
318 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
320 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
321 (aarch64_feature_crc): New static.
323 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
324 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
325 * aarch64-asm-2.c: Re-generate.
326 * aarch64-dis-2.c: Ditto.
327 * aarch64-opc-2.c: Ditto.
329 2013-02-27 Alan Modra <amodra@gmail.com>
331 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
332 * rl78-decode.c: Regenerate.
334 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
336 * rl78-decode.opc: Fix encoding of DIVWU insn.
337 * rl78-decode.c: Regenerate.
339 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
342 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
344 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
345 (cpu_flags): Add CpuSMAP.
347 * i386-opc.h (CpuSMAP): New.
348 (i386_cpu_flags): Add cpusmap.
350 * i386-opc.tbl: Add clac and stac.
352 * i386-init.h: Regenerated.
353 * i386-tbl.h: Likewise.
355 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
357 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
358 which also makes the disassembler output be in little
359 endian like it should be.
361 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
363 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
365 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
367 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
369 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
370 section disassembled.
372 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
374 * arm-dis.c: Update strht pattern.
376 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
378 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
379 single-float. Disable ll, lld, sc and scd for EE. Disable the
380 trunc.w.s macro for EE.
382 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
383 Andrew Jenner <andrew@codesourcery.com>
385 Based on patches from Altera Corporation.
387 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
389 * Makefile.in: Regenerated.
390 * configure.in: Add case for bfd_nios2_arch.
391 * configure: Regenerated.
392 * disassemble.c (ARCH_nios2): Define.
393 (disassembler): Add case for bfd_arch_nios2.
394 * nios2-dis.c: New file.
395 * nios2-opc.c: New file.
397 2013-02-04 Alan Modra <amodra@gmail.com>
399 * po/POTFILES.in: Regenerate.
400 * rl78-decode.c: Regenerate.
401 * rx-decode.c: Regenerate.
403 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
405 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
406 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
407 * aarch64-asm.c (convert_xtl_to_shll): New function.
408 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
409 calling convert_xtl_to_shll.
410 * aarch64-dis.c (convert_shll_to_xtl): New function.
411 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
412 calling convert_shll_to_xtl.
413 * aarch64-gen.c: Update copyright year.
414 * aarch64-asm-2.c: Re-generate.
415 * aarch64-dis-2.c: Re-generate.
416 * aarch64-opc-2.c: Re-generate.
418 2013-01-24 Nick Clifton <nickc@redhat.com>
420 * v850-dis.c: Add support for e3v5 architecture.
421 * v850-opc.c: Likewise.
423 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
425 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
426 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
427 * aarch64-opc.c (operand_general_constraint_met_p): For
428 AARCH64_MOD_LSL, move the range check on the shift amount before the
429 alignment check; change to call set_sft_amount_out_of_range_error
430 instead of set_imm_out_of_range_error.
431 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
432 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
433 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
436 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
438 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
440 * i386-init.h: Regenerated.
441 * i386-tbl.h: Likewise.
443 2013-01-15 Nick Clifton <nickc@redhat.com>
445 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
447 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
449 2013-01-14 Will Newton <will.newton@imgtec.com>
451 * metag-dis.c (REG_WIDTH): Increase to 64.
453 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
455 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
456 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
457 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
459 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
460 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
461 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
462 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
464 2013-01-10 Will Newton <will.newton@imgtec.com>
466 * Makefile.am: Add Meta.
467 * configure.in: Add Meta.
468 * disassemble.c: Add Meta support.
469 * metag-dis.c: New file.
470 * Makefile.in: Regenerate.
471 * configure: Regenerate.
473 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
475 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
476 (match_opcode): Rename to cr16_match_opcode.
478 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
480 * mips-dis.c: Add names for CP0 registers of r5900.
481 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
482 instructions sq and lq.
483 Add support for MIPS r5900 CPU.
484 Add support for 128 bit MMI (Multimedia Instructions).
485 Add support for EE instructions (Emotion Engine).
486 Disable unsupported floating point instructions (64 bit and
487 undefined compare operations).
488 Enable instructions of MIPS ISA IV which are supported by r5900.
489 Disable 64 bit co processor instructions.
490 Disable 64 bit multiplication and division instructions.
491 Disable instructions for co-processor 2 and 3, because these are
492 not supported (preparation for later VU0 support (Vector Unit)).
493 Disable cvt.w.s because this behaves like trunc.w.s and the
494 correct execution can't be ensured on r5900.
495 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
496 will confuse less developers and compilers.
498 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
500 * aarch64-opc.c (aarch64_print_operand): Change to print
501 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
503 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
504 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
507 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
509 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
510 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
512 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
514 * i386-gen.c (process_copyright): Update copyright year to 2013.
516 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
518 * cr16-dis.c (match_opcode,make_instruction): Remove static
520 (dwordU,wordU): Moved typedefs to opcode/cr16.h
521 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
523 For older changes see ChangeLog-2012
525 Copyright (C) 2013 Free Software Foundation, Inc.
527 Copying and distribution of this file, with or without modification,
528 are permitted in any medium without royalty provided the copyright
529 notice and this notice are preserved.
535 version-control: never