1 2018-05-25 Alan Modra <amodra@gmail.com>
3 * Makefile.in: Regenerate.
4 * po/POTFILES.in: Regenerate.
6 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
8 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
9 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
10 (insert_bab, extract_bab, insert_btab, extract_btab,
11 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
12 (BAT, BBA VBA RBS XB6S): Delete macros.
13 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
14 (BB, BD, RBX, XC6): Update for new macros.
15 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
16 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
17 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
18 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
20 2018-05-18 John Darrington <john@darrington.wattle.id.au>
22 * Makefile.am: Add support for s12z architecture.
23 * configure.ac: Likewise.
24 * disassemble.c: Likewise.
25 * disassemble.h: Likewise.
26 * Makefile.in: Regenerate.
27 * configure: Regenerate.
28 * s12z-dis.c: New file.
31 2018-05-18 Alan Modra <amodra@gmail.com>
33 * nfp-dis.c: Don't #include libbfd.h.
34 (init_nfp3200_priv): Use bfd_get_section_contents.
35 (nit_nfp6000_mecsr_sec): Likewise.
37 2018-05-17 Nick Clifton <nickc@redhat.com>
39 * po/zh_CN.po: Updated simplified Chinese translation.
41 2018-05-16 Tamar Christina <tamar.christina@arm.com>
44 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
45 * aarch64-dis-2.c: Regenerate.
47 2018-05-15 Tamar Christina <tamar.christina@arm.com>
50 * aarch64-asm.c (opintl.h): Include.
51 (aarch64_ins_sysreg): Enforce read/write constraints.
52 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
53 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
54 (F_REG_READ, F_REG_WRITE): New.
55 * aarch64-opc.c (aarch64_print_operand): Generate notes for
57 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
58 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
59 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
60 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
61 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
62 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
63 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
64 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
65 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
66 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
67 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
68 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
69 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
70 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
71 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
72 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
73 msr (F_SYS_WRITE), mrs (F_SYS_READ).
75 2018-05-15 Tamar Christina <tamar.christina@arm.com>
78 * aarch64-dis.c (no_notes: New.
79 (parse_aarch64_dis_option): Support notes.
80 (aarch64_decode_insn, print_operands): Likewise.
81 (print_aarch64_disassembler_options): Document notes.
82 * aarch64-opc.c (aarch64_print_operand): Support notes.
84 2018-05-15 Tamar Christina <tamar.christina@arm.com>
87 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
88 and take error struct.
89 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
90 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
91 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
92 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
93 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
94 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
95 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
96 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
97 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
98 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
99 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
100 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
101 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
102 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
103 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
104 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
105 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
106 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
107 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
108 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
109 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
110 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
111 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
112 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
113 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
114 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
115 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
116 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
117 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
118 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
119 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
120 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
121 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
122 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
123 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
124 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
125 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
126 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
127 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
128 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
129 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
130 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
131 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
132 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
133 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
134 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
135 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
136 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
137 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
138 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
139 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
140 (determine_disassembling_preference, aarch64_decode_insn,
141 print_insn_aarch64_word, print_insn_data): Take errors struct.
142 (print_insn_aarch64): Use errors.
143 * aarch64-asm-2.c: Regenerate.
144 * aarch64-dis-2.c: Regenerate.
145 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
146 boolean in aarch64_insert_operan.
147 (print_operand_extractor): Likewise.
148 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
150 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
152 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
154 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
156 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
158 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
160 * cr16-opc.c (cr16_instruction): Comment typo fix.
161 * hppa-dis.c (print_insn_hppa): Likewise.
163 2018-05-08 Jim Wilson <jimw@sifive.com>
165 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
166 (match_c_slli64, match_srxi_as_c_srxi): New.
167 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
168 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
169 <c.slli, c.srli, c.srai>: Use match_s_slli.
170 <c.slli64, c.srli64, c.srai64>: New.
172 2018-05-08 Alan Modra <amodra@gmail.com>
174 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
175 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
176 partition opcode space for index lookup.
178 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
180 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
181 <insn_length>: ...with this. Update usage.
182 Remove duplicate call to *info->memory_error_func.
184 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
185 H.J. Lu <hongjiu.lu@intel.com>
187 * i386-dis.c (Gva): New.
188 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
189 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
190 (prefix_table): New instructions (see prefix above).
191 (mod_table): New instructions (see prefix above).
192 (OP_G): Handle va_mode.
193 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
195 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
196 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
197 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
198 * i386-opc.tbl: Add movidir{i,64b}.
199 * i386-init.h: Regenerated.
200 * i386-tbl.h: Likewise.
202 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
204 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
206 * i386-opc.h (AddrPrefixOp0): Renamed to ...
207 (AddrPrefixOpReg): This.
208 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
209 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
211 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
213 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
214 (vle_num_opcodes): Likewise.
215 (spe2_num_opcodes): Likewise.
216 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
218 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
219 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
222 2018-05-01 Tamar Christina <tamar.christina@arm.com>
224 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
226 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
228 Makefile.am: Added nfp-dis.c.
229 configure.ac: Added bfd_nfp_arch.
230 disassemble.h: Added print_insn_nfp prototype.
231 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
232 nfp-dis.c: New, for NFP support.
233 po/POTFILES.in: Added nfp-dis.c to the list.
234 Makefile.in: Regenerate.
235 configure: Regenerate.
237 2018-04-26 Jan Beulich <jbeulich@suse.com>
239 * i386-opc.tbl: Fold various non-memory operand AVX512VL
240 templates into their base ones.
241 * i386-tlb.h: Re-generate.
243 2018-04-26 Jan Beulich <jbeulich@suse.com>
245 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
246 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
247 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
248 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
249 * i386-init.h: Re-generate.
251 2018-04-26 Jan Beulich <jbeulich@suse.com>
253 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
254 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
255 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
256 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
258 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
260 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
262 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
263 cpuregzmm, and cpuregmask.
264 * i386-init.h: Re-generate.
265 * i386-tbl.h: Re-generate.
267 2018-04-26 Jan Beulich <jbeulich@suse.com>
269 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
270 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
271 * i386-init.h: Re-generate.
273 2018-04-26 Jan Beulich <jbeulich@suse.com>
275 * i386-gen.c (VexImmExt): Delete.
276 * i386-opc.h (VexImmExt, veximmext): Delete.
277 * i386-opc.tbl: Drop all VexImmExt uses.
278 * i386-tlb.h: Re-generate.
280 2018-04-25 Jan Beulich <jbeulich@suse.com>
282 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
284 * i386-tlb.h: Re-generate.
286 2018-04-25 Tamar Christina <tamar.christina@arm.com>
288 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
290 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
292 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
294 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
295 (cpu_flags): Add CpuCLDEMOTE.
296 * i386-init.h: Regenerate.
297 * i386-opc.h (enum): Add CpuCLDEMOTE,
298 (i386_cpu_flags): Add cpucldemote.
299 * i386-opc.tbl: Add cldemote.
300 * i386-tbl.h: Regenerate.
302 2018-04-16 Alan Modra <amodra@gmail.com>
304 * Makefile.am: Remove sh5 and sh64 support.
305 * configure.ac: Likewise.
306 * disassemble.c: Likewise.
307 * disassemble.h: Likewise.
308 * sh-dis.c: Likewise.
309 * sh64-dis.c: Delete.
310 * sh64-opc.c: Delete.
311 * sh64-opc.h: Delete.
312 * Makefile.in: Regenerate.
313 * configure: Regenerate.
314 * po/POTFILES.in: Regenerate.
316 2018-04-16 Alan Modra <amodra@gmail.com>
318 * Makefile.am: Remove w65 support.
319 * configure.ac: Likewise.
320 * disassemble.c: Likewise.
321 * disassemble.h: Likewise.
324 * Makefile.in: Regenerate.
325 * configure: Regenerate.
326 * po/POTFILES.in: Regenerate.
328 2018-04-16 Alan Modra <amodra@gmail.com>
330 * configure.ac: Remove we32k support.
331 * configure: Regenerate.
333 2018-04-16 Alan Modra <amodra@gmail.com>
335 * Makefile.am: Remove m88k support.
336 * configure.ac: Likewise.
337 * disassemble.c: Likewise.
338 * disassemble.h: Likewise.
339 * m88k-dis.c: Delete.
340 * Makefile.in: Regenerate.
341 * configure: Regenerate.
342 * po/POTFILES.in: Regenerate.
344 2018-04-16 Alan Modra <amodra@gmail.com>
346 * Makefile.am: Remove i370 support.
347 * configure.ac: Likewise.
348 * disassemble.c: Likewise.
349 * disassemble.h: Likewise.
350 * i370-dis.c: Delete.
351 * i370-opc.c: Delete.
352 * Makefile.in: Regenerate.
353 * configure: Regenerate.
354 * po/POTFILES.in: Regenerate.
356 2018-04-16 Alan Modra <amodra@gmail.com>
358 * Makefile.am: Remove h8500 support.
359 * configure.ac: Likewise.
360 * disassemble.c: Likewise.
361 * disassemble.h: Likewise.
362 * h8500-dis.c: Delete.
363 * h8500-opc.h: Delete.
364 * Makefile.in: Regenerate.
365 * configure: Regenerate.
366 * po/POTFILES.in: Regenerate.
368 2018-04-16 Alan Modra <amodra@gmail.com>
370 * configure.ac: Remove tahoe support.
371 * configure: Regenerate.
373 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
375 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
377 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
379 * i386-tbl.h: Regenerated.
381 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
383 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
384 PREFIX_MOD_1_0FAE_REG_6.
386 (OP_E_register): Use va_mode.
387 * i386-dis-evex.h (prefix_table):
388 New instructions (see prefixes above).
389 * i386-gen.c (cpu_flag_init): Add WAITPKG.
390 (cpu_flags): Likewise.
391 * i386-opc.h (enum): Likewise.
392 (i386_cpu_flags): Likewise.
393 * i386-opc.tbl: Add umonitor, umwait, tpause.
394 * i386-init.h: Regenerate.
395 * i386-tbl.h: Likewise.
397 2018-04-11 Alan Modra <amodra@gmail.com>
399 * opcodes/i860-dis.c: Delete.
400 * opcodes/i960-dis.c: Delete.
401 * Makefile.am: Remove i860 and i960 support.
402 * configure.ac: Likewise.
403 * disassemble.c: Likewise.
404 * disassemble.h: Likewise.
405 * Makefile.in: Regenerate.
406 * configure: Regenerate.
407 * po/POTFILES.in: Regenerate.
409 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
412 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
414 (print_insn): Clear vex instead of vex.evex.
416 2018-04-04 Nick Clifton <nickc@redhat.com>
418 * po/es.po: Updated Spanish translation.
420 2018-03-28 Jan Beulich <jbeulich@suse.com>
422 * i386-gen.c (opcode_modifiers): Delete VecESize.
423 * i386-opc.h (VecESize): Delete.
424 (struct i386_opcode_modifier): Delete vecesize.
425 * i386-opc.tbl: Drop VecESize.
426 * i386-tlb.h: Re-generate.
428 2018-03-28 Jan Beulich <jbeulich@suse.com>
430 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
431 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
432 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
433 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
434 * i386-tlb.h: Re-generate.
436 2018-03-28 Jan Beulich <jbeulich@suse.com>
438 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
440 * i386-tlb.h: Re-generate.
442 2018-03-28 Jan Beulich <jbeulich@suse.com>
444 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
445 (vex_len_table): Drop Y for vcvt*2si.
446 (putop): Replace plain 'Y' handling by abort().
448 2018-03-28 Nick Clifton <nickc@redhat.com>
451 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
452 instructions with only a base address register.
453 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
454 handle AARHC64_OPND_SVE_ADDR_R.
455 (aarch64_print_operand): Likewise.
456 * aarch64-asm-2.c: Regenerate.
457 * aarch64_dis-2.c: Regenerate.
458 * aarch64-opc-2.c: Regenerate.
460 2018-03-22 Jan Beulich <jbeulich@suse.com>
462 * i386-opc.tbl: Drop VecESize from register only insn forms and
463 memory forms not allowing broadcast.
464 * i386-tlb.h: Re-generate.
466 2018-03-22 Jan Beulich <jbeulich@suse.com>
468 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
469 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
470 sha256*): Drop Disp<N>.
472 2018-03-22 Jan Beulich <jbeulich@suse.com>
474 * i386-dis.c (EbndS, bnd_swap_mode): New.
475 (prefix_table): Use EbndS.
476 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
477 * i386-opc.tbl (bndmov): Move misplaced Load.
478 * i386-tlb.h: Re-generate.
480 2018-03-22 Jan Beulich <jbeulich@suse.com>
482 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
483 templates allowing memory operands and folded ones for register
485 * i386-tlb.h: Re-generate.
487 2018-03-22 Jan Beulich <jbeulich@suse.com>
489 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
490 256-bit templates. Drop redundant leftover Disp<N>.
491 * i386-tlb.h: Re-generate.
493 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
495 * riscv-opc.c (riscv_insn_types): New.
497 2018-03-13 Nick Clifton <nickc@redhat.com>
499 * po/pt_BR.po: Updated Brazilian Portuguese translation.
501 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-opc.tbl: Add Optimize to clr.
504 * i386-tbl.h: Regenerated.
506 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
508 * i386-gen.c (opcode_modifiers): Remove OldGcc.
509 * i386-opc.h (OldGcc): Removed.
510 (i386_opcode_modifier): Remove oldgcc.
511 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
512 instructions for old (<= 2.8.1) versions of gcc.
513 * i386-tbl.h: Regenerated.
515 2018-03-08 Jan Beulich <jbeulich@suse.com>
517 * i386-opc.h (EVEXDYN): New.
518 * i386-opc.tbl: Fold various AVX512VL templates.
519 * i386-tlb.h: Re-generate.
521 2018-03-08 Jan Beulich <jbeulich@suse.com>
523 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
524 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
525 vpexpandd, vpexpandq): Fold AFX512VF templates.
526 * i386-tlb.h: Re-generate.
528 2018-03-08 Jan Beulich <jbeulich@suse.com>
530 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
531 Fold 128- and 256-bit VEX-encoded templates.
532 * i386-tlb.h: Re-generate.
534 2018-03-08 Jan Beulich <jbeulich@suse.com>
536 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
537 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
538 vpexpandd, vpexpandq): Fold AVX512F templates.
539 * i386-tlb.h: Re-generate.
541 2018-03-08 Jan Beulich <jbeulich@suse.com>
543 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
544 64-bit templates. Drop Disp<N>.
545 * i386-tlb.h: Re-generate.
547 2018-03-08 Jan Beulich <jbeulich@suse.com>
549 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
550 and 256-bit templates.
551 * i386-tlb.h: Re-generate.
553 2018-03-08 Jan Beulich <jbeulich@suse.com>
555 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
556 * i386-tlb.h: Re-generate.
558 2018-03-08 Jan Beulich <jbeulich@suse.com>
560 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
562 * i386-tlb.h: Re-generate.
564 2018-03-08 Jan Beulich <jbeulich@suse.com>
566 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
567 * i386-tlb.h: Re-generate.
569 2018-03-08 Jan Beulich <jbeulich@suse.com>
571 * i386-gen.c (opcode_modifiers): Delete FloatD.
572 * i386-opc.h (FloatD): Delete.
573 (struct i386_opcode_modifier): Delete floatd.
574 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
576 * i386-tlb.h: Re-generate.
578 2018-03-08 Jan Beulich <jbeulich@suse.com>
580 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
582 2018-03-08 Jan Beulich <jbeulich@suse.com>
584 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
585 * i386-tlb.h: Re-generate.
587 2018-03-08 Jan Beulich <jbeulich@suse.com>
589 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
591 * i386-tlb.h: Re-generate.
593 2018-03-07 Alan Modra <amodra@gmail.com>
595 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
597 * disassemble.h (print_insn_rs6000): Delete.
598 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
599 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
600 (print_insn_rs6000): Delete.
602 2018-03-03 Alan Modra <amodra@gmail.com>
604 * sysdep.h (opcodes_error_handler): Define.
605 (_bfd_error_handler): Declare.
606 * Makefile.am: Remove stray #.
607 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
609 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
610 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
611 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
612 opcodes_error_handler to print errors. Standardize error messages.
613 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
614 and include opintl.h.
615 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
616 * i386-gen.c: Standardize error messages.
617 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
618 * Makefile.in: Regenerate.
619 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
620 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
621 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
622 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
623 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
624 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
625 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
626 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
627 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
628 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
629 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
630 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
631 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
633 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
635 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
636 vpsub[bwdq] instructions.
637 * i386-tbl.h: Regenerated.
639 2018-03-01 Alan Modra <amodra@gmail.com>
641 * configure.ac (ALL_LINGUAS): Sort.
642 * configure: Regenerate.
644 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
646 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
647 macro by assignements.
649 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
652 * i386-gen.c (opcode_modifiers): Add Optimize.
653 * i386-opc.h (Optimize): New enum.
654 (i386_opcode_modifier): Add optimize.
655 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
656 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
657 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
658 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
659 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
661 * i386-tbl.h: Regenerated.
663 2018-02-26 Alan Modra <amodra@gmail.com>
665 * crx-dis.c (getregliststring): Allocate a large enough buffer
666 to silence false positive gcc8 warning.
668 2018-02-22 Shea Levy <shea@shealevy.com>
670 * disassemble.c (ARCH_riscv): Define if ARCH_all.
672 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
674 * i386-opc.tbl: Add {rex},
675 * i386-tbl.h: Regenerated.
677 2018-02-20 Maciej W. Rozycki <macro@mips.com>
679 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
680 (mips16_opcodes): Replace `M' with `m' for "restore".
682 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
684 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
686 2018-02-13 Maciej W. Rozycki <macro@mips.com>
688 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
689 variable to `function_index'.
691 2018-02-13 Nick Clifton <nickc@redhat.com>
694 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
695 about truncation of printing.
697 2018-02-12 Henry Wong <henry@stuffedcow.net>
699 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
701 2018-02-05 Nick Clifton <nickc@redhat.com>
703 * po/pt_BR.po: Updated Brazilian Portuguese translation.
705 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
707 * i386-dis.c (enum): Add pconfig.
708 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
709 (cpu_flags): Add CpuPCONFIG.
710 * i386-opc.h (enum): Add CpuPCONFIG.
711 (i386_cpu_flags): Add cpupconfig.
712 * i386-opc.tbl: Add PCONFIG instruction.
713 * i386-init.h: Regenerate.
714 * i386-tbl.h: Likewise.
716 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
718 * i386-dis.c (enum): Add PREFIX_0F09.
719 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
720 (cpu_flags): Add CpuWBNOINVD.
721 * i386-opc.h (enum): Add CpuWBNOINVD.
722 (i386_cpu_flags): Add cpuwbnoinvd.
723 * i386-opc.tbl: Add WBNOINVD instruction.
724 * i386-init.h: Regenerate.
725 * i386-tbl.h: Likewise.
727 2018-01-17 Jim Wilson <jimw@sifive.com>
729 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
731 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
733 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
734 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
735 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
736 (cpu_flags): Add CpuIBT, CpuSHSTK.
737 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
738 (i386_cpu_flags): Add cpuibt, cpushstk.
739 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
740 * i386-init.h: Regenerate.
741 * i386-tbl.h: Likewise.
743 2018-01-16 Nick Clifton <nickc@redhat.com>
745 * po/pt_BR.po: Updated Brazilian Portugese translation.
746 * po/de.po: Updated German translation.
748 2018-01-15 Jim Wilson <jimw@sifive.com>
750 * riscv-opc.c (match_c_nop): New.
751 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
753 2018-01-15 Nick Clifton <nickc@redhat.com>
755 * po/uk.po: Updated Ukranian translation.
757 2018-01-13 Nick Clifton <nickc@redhat.com>
759 * po/opcodes.pot: Regenerated.
761 2018-01-13 Nick Clifton <nickc@redhat.com>
763 * configure: Regenerate.
765 2018-01-13 Nick Clifton <nickc@redhat.com>
769 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
771 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
772 * i386-tbl.h: Regenerate.
774 2018-01-10 Jan Beulich <jbeulich@suse.com>
776 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
777 * i386-tbl.h: Re-generate.
779 2018-01-10 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
782 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
783 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
784 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
785 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
786 Disp8MemShift of AVX512VL forms.
787 * i386-tbl.h: Re-generate.
789 2018-01-09 Jim Wilson <jimw@sifive.com>
791 * riscv-dis.c (maybe_print_address): If base_reg is zero,
792 then the hi_addr value is zero.
794 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
796 * arm-dis.c (arm_opcodes): Add csdb.
797 (thumb32_opcodes): Add csdb.
799 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
801 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
802 * aarch64-asm-2.c: Regenerate.
803 * aarch64-dis-2.c: Regenerate.
804 * aarch64-opc-2.c: Regenerate.
806 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
809 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
810 Remove AVX512 vmovd with 64-bit operands.
811 * i386-tbl.h: Regenerated.
813 2018-01-05 Jim Wilson <jimw@sifive.com>
815 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
818 2018-01-03 Alan Modra <amodra@gmail.com>
820 Update year range in copyright notice of all files.
822 2018-01-02 Jan Beulich <jbeulich@suse.com>
824 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
825 and OPERAND_TYPE_REGZMM entries.
827 For older changes see ChangeLog-2017
829 Copyright (C) 2018 Free Software Foundation, Inc.
831 Copying and distribution of this file, with or without modification,
832 are permitted in any medium without royalty provided the copyright
833 notice and this notice are preserved.
839 version-control: never