1 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
3 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
4 (WR_SP): Replace with...
6 (mips16_opcodes): Update accordingly.
7 * mips-dis.c (print_insn_mips16): Likewise.
9 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
11 * mips16-opc.c (mips16_opcodes): Reformat.
13 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
15 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
16 for operands that are hard-coded to $0.
17 * micromips-opc.c (micromips_opcodes): Likewise.
19 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
21 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
22 for the single-operand forms of JALR and JALR.HB.
23 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
26 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
28 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
29 instructions. Fix them to use WR_MACC instead of WR_CC and
32 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
34 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
36 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
38 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
40 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
41 Alexander Ivchenko <alexander.ivchenko@intel.com>
42 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
43 Sergey Lega <sergey.s.lega@intel.com>
44 Anna Tikhonova <anna.tikhonova@intel.com>
45 Ilya Tocar <ilya.tocar@intel.com>
46 Andrey Turetskiy <andrey.turetskiy@intel.com>
47 Ilya Verbin <ilya.verbin@intel.com>
48 Kirill Yukhin <kirill.yukhin@intel.com>
49 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
51 * i386-dis-evex.h: New.
52 * i386-dis.c (OP_Rounding): New.
59 (EXEvexHalfBcstXmmq): New.
71 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
72 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
73 evex_rounding_mode, evex_sae_mode, mask_mode.
74 (USE_EVEX_TABLE): New.
77 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
79 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
80 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
81 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
82 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
83 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
84 MOD_EVEX_0F38C7_REG_6.
85 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
86 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
87 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
88 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
89 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
90 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
91 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
92 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
93 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
94 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
95 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
96 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
97 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
98 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
99 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
100 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
101 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
102 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
103 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
104 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
105 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
106 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
107 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
108 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
109 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
110 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
111 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
112 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
113 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
114 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
115 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
116 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
117 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
118 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
119 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
120 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
121 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
122 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
123 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
124 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
125 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
126 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
127 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
128 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
129 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
130 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
131 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
132 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
133 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
134 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
135 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
136 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
137 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
138 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
139 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
140 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
141 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
142 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
143 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
144 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
145 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
146 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
147 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
148 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
149 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
150 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
151 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
152 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
153 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
154 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
155 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
156 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
157 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
158 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
159 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
160 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
162 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
163 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
164 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
165 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
166 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
167 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
168 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
169 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
170 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
171 VEX_W_0F3A32_P_2_LEN_0.
172 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
173 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
174 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
175 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
176 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
177 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
178 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
179 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
180 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
181 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
182 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
183 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
184 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
185 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
186 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
187 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
188 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
189 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
190 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
191 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
192 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
193 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
194 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
195 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
196 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
197 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
198 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
199 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
200 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
201 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
202 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
203 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
204 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
205 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
206 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
207 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
208 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
209 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
210 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
211 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
212 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
213 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
214 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
215 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
216 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
217 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
218 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
219 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
220 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
221 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
222 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
223 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
224 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
225 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
226 (struct vex): Add fields evex, r, v, mask_register_specifier,
228 (intel_names_xmm): Add upper 16 registers.
229 (att_names_xmm): Ditto.
230 (intel_names_ymm): Ditto.
231 (att_names_ymm): Ditto.
233 (intel_names_zmm): Ditto.
234 (att_names_zmm): Ditto.
236 (intel_names_mask): Ditto.
237 (att_names_mask): Ditto.
238 (names_rounding): Ditto.
239 (names_broadcast): Ditto.
240 (x86_64_table): Add escape to evex-table.
241 (reg_table): Include reg_table evex-entries from
242 i386-dis-evex.h. Fix prefetchwt1 instruction.
243 (prefix_table): Add entries for new instructions.
245 (vex_len_table): Ditto.
246 (vex_w_table): Ditto.
248 (get_valid_dis386): Properly handle new instructions.
249 (print_insn): Handle zmm and mask registers, print mask operand.
250 (intel_operand_size): Support EVEX, new modes and sizes.
251 (OP_E_register): Handle new modes.
252 (OP_E_memory): Ditto.
257 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
258 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
259 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
260 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
261 CpuAVX512PF and CpuVREX.
262 (operand_type_init): Add OPERAND_TYPE_REGZMM,
263 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
264 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
265 StaticRounding, SAE, Disp8MemShift, NoDefMask.
266 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
267 * i386-init.h: Regenerate.
268 * i386-opc.h (CpuAVX512F): New.
273 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
274 cpuavx512pf and cpuvrex fields.
275 (VecSIB): Add VecSIB512.
280 (StaticRounding): New.
282 (Disp8MemShift): New.
284 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
285 staticrounding, sae, disp8memshift and nodefmask.
289 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
292 * i386-opc.tbl: Add AVX512 instructions.
293 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
294 registers, mask registers.
295 * i386-tbl.h: Regenerate.
297 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
300 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
301 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
303 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
305 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
306 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
308 (prefix_table): Updated.
309 (three_byte_table): Likewise.
310 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
311 (cpu_flags): Add CpuSHA.
312 (i386_cpu_flags): Add cpusha.
313 * i386-init.h: Regenerate.
314 * i386-opc.h (CpuSHA): New.
315 (CpuUnused): Restored.
316 (i386_cpu_flags): Add cpusha.
317 * i386-opc.tbl: Add SHA instructions.
318 * i386-tbl.h: Regenerate.
320 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
321 Kirill Yukhin <kirill.yukhin@intel.com>
322 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
324 * i386-dis.c (BND_Fixup): New.
331 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
333 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
334 (dis tables): Replace XX with BND for near branch and call
336 (prefix_table): Add new entries.
337 (mod_table): Likewise.
339 (intel_names_bnd): New.
340 (att_names_bnd): New.
342 (prefix_name): Handle BND_PREFIX.
343 (print_insn): Initialize names_bnd.
344 (intel_operand_size): Handle new modes.
345 (OP_E_register): Likewise.
346 (OP_E_memory): Likewise.
348 * i386-gen.c (cpu_flag_init): Add CpuMPX.
349 (cpu_flags): Add CpuMPX.
350 (operand_type_init): Add RegBND.
351 (opcode_modifiers): Add BNDPrefixOk.
352 (operand_types): Add RegBND.
353 * i386-init.h: Regenerate.
354 * i386-opc.h (CpuMPX): New.
355 (CpuUnused): Comment out.
356 (i386_cpu_flags): Add cpumpx.
358 (i386_opcode_modifier): Add bndprefixok.
360 (i386_operand_type): Add regbnd.
361 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
362 Add MPX instructions and bnd prefix.
363 * i386-reg.tbl: Add bnd0-bnd3 registers.
364 * i386-tbl.h: Regenerate.
366 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
368 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
371 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
373 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
375 * Makefile.in: Regenerate.
376 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
377 all fields. Reformat.
379 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
381 * mips16-opc.c: Include mips-formats.h.
382 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
384 (decode_mips16_operand): New function.
385 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
386 (print_insn_arg): Handle OP_ENTRY_EXIT list.
387 Abort for OP_SAVE_RESTORE_LIST.
388 (print_mips16_insn_arg): Change interface. Use mips_operand
389 structures. Delete GET_OP_S. Move GET_OP definition to...
390 (print_insn_mips16): ...here. Call init_print_arg_state.
391 Update the call to print_mips16_insn_arg.
393 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
395 * mips-formats.h: New file.
396 * mips-opc.c: Include mips-formats.h.
397 (reg_0_map): New static array.
398 (decode_mips_operand): New function.
399 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
400 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
401 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
402 (int_c_map): New static arrays.
403 (decode_micromips_operand): New function.
404 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
405 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
406 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
407 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
408 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
409 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
410 (micromips_imm_b_map, micromips_imm_c_map): Delete.
411 (print_reg): New function.
412 (mips_print_arg_state): New structure.
413 (init_print_arg_state, print_insn_arg): New functions.
414 (print_insn_args): Change interface and use mips_operand structures.
415 Delete GET_OP_S. Move GET_OP definition to...
416 (print_insn_mips): ...here. Update the call to print_insn_args.
417 (print_insn_micromips): Use print_insn_args.
419 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
421 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
424 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
426 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
427 ADDA.S, MULA.S and SUBA.S.
429 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
432 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
433 * i386-tbl.h: Regenerated.
435 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
437 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
438 and SD A(B) macros up.
439 * micromips-opc.c (micromips_opcodes): Likewise.
441 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
443 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
446 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
448 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
449 MDMX-like instructions.
450 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
451 printing "Q" operands for INSN_5400 instructions.
453 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
455 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
457 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
460 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
462 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
464 * mips16-opc.c (mips16_opcodes): Likewise.
465 * micromips-opc.c (micromips_opcodes): Likewise.
466 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
467 (print_insn_mips16): Handle "+i".
468 (print_insn_micromips): Likewise. Conditionally preserve the
469 ISA bit for "a" but not for "+i".
471 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
473 * micromips-opc.c (WR_mhi): Rename to..
475 (micromips_opcodes): Update "movep" entry accordingly. Replace
477 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
478 (micromips_to_32_reg_h_map1): ...this.
479 (micromips_to_32_reg_i_map): Rename to...
480 (micromips_to_32_reg_h_map2): ...this.
481 (print_micromips_insn): Remove "mi" case. Print both registers
482 in the pair for "mh".
484 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
486 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
487 * micromips-opc.c (micromips_opcodes): Likewise.
488 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
489 and "+T" handling. Check for a "0" suffix when deciding whether to
490 use coprocessor 0 names. In that case, also check for ",H" selectors.
492 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
494 * s390-opc.c (J12_12, J24_24): New macros.
495 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
496 (MASK_MII_UPI): Rename to MASK_MII_UPP.
497 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
499 2013-07-04 Alan Modra <amodra@gmail.com>
501 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
503 2013-06-26 Nick Clifton <nickc@redhat.com>
505 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
506 field when checking for type 2 nop.
507 * rx-decode.c: Regenerate.
509 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
511 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
514 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
516 * mips-dis.c (is_mips16_plt_tail): New function.
517 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
519 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
521 2013-06-21 DJ Delorie <dj@redhat.com>
523 * msp430-decode.opc: New.
524 * msp430-decode.c: New/generated.
525 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
526 (MAINTAINER_CLEANFILES): Likewise.
527 Add rule to build msp430-decode.c frommsp430decode.opc
528 using the opc2c program.
529 * Makefile.in: Regenerate.
530 * configure.in: Add msp430-decode.lo to msp430 architecture files.
531 * configure: Regenerate.
533 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
535 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
536 (SYMTAB_AVAILABLE): Removed.
537 (#include "elf/aarch64.h): Ditto.
539 2013-06-17 Catherine Moore <clm@codesourcery.com>
540 Maciej W. Rozycki <macro@codesourcery.com>
541 Chao-Ying Fu <fu@mips.com>
543 * micromips-opc.c (EVA): Define.
545 (micromips_opcodes): Add EVA opcodes.
546 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
547 (print_insn_args): Handle EVA offsets.
548 (print_insn_micromips): Likewise.
549 * mips-opc.c (EVA): Define.
551 (mips_builtin_opcodes): Add EVA opcodes.
553 2013-06-17 Alan Modra <amodra@gmail.com>
555 * Makefile.am (mips-opc.lo): Add rules to create automatic
556 dependency files. Pass archdefs.
557 (micromips-opc.lo, mips16-opc.lo): Likewise.
558 * Makefile.in: Regenerate.
560 2013-06-14 DJ Delorie <dj@redhat.com>
562 * rx-decode.opc (rx_decode_opcode): Bit operations on
563 registers are 32-bit operations, not 8-bit operations.
564 * rx-decode.c: Regenerate.
566 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
568 * micromips-opc.c (IVIRT): New define.
569 (IVIRT64): New define.
570 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
571 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
573 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
574 dmtgc0 to print cp0 names.
576 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
578 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
581 2013-06-08 Catherine Moore <clm@codesourcery.com>
582 Richard Sandiford <rdsandiford@googlemail.com>
584 * micromips-opc.c (D32, D33, MC): Update definitions.
585 (micromips_opcodes): Initialize ase field.
586 * mips-dis.c (mips_arch_choice): Add ase field.
587 (mips_arch_choices): Initialize ase field.
588 (set_default_mips_dis_options): Declare and setup mips_ase.
589 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
590 MT32, MC): Update definitions.
591 (mips_builtin_opcodes): Initialize ase field.
593 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
595 * s390-opc.txt (flogr): Require a register pair destination.
597 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
599 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
602 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
604 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
606 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
608 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
609 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
610 XLS_MASK, PPCVSX2): New defines.
611 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
612 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
613 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
614 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
615 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
616 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
617 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
618 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
619 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
620 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
621 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
622 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
623 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
624 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
625 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
626 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
627 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
628 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
629 <lxvx, stxvx>: New extended mnemonics.
631 2013-05-17 Alan Modra <amodra@gmail.com>
633 * ia64-raw.tbl: Replace non-ASCII char.
634 * ia64-waw.tbl: Likewise.
635 * ia64-asmtab.c: Regenerate.
637 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
639 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
640 * i386-init.h: Regenerated.
642 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
644 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
645 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
646 check from [0, 255] to [-128, 255].
648 2013-05-09 Andrew Pinski <apinski@cavium.com>
650 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
651 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
652 (parse_mips_dis_option): Handle the virt option.
653 (print_insn_args): Handle "+J".
654 (print_mips_disassembler_options): Print out message about virt64.
655 * mips-opc.c (IVIRT): New define.
656 (IVIRT64): New define.
657 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
658 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
659 Move rfe to the bottom as it conflicts with tlbgp.
661 2013-05-09 Alan Modra <amodra@gmail.com>
663 * ppc-opc.c (extract_vlesi): Properly sign extend.
664 (extract_vlensi): Likewise. Comment reason for setting invalid.
666 2013-05-02 Nick Clifton <nickc@redhat.com>
668 * msp430-dis.c: Add support for MSP430X instructions.
670 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
672 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
675 2013-04-17 Wei-chen Wang <cole945@gmail.com>
678 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
680 (hash_insns_list): Likewise.
682 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
684 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
687 2013-04-08 Jan Beulich <jbeulich@suse.com>
689 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
690 * i386-tbl.h: Re-generate.
692 2013-04-06 David S. Miller <davem@davemloft.net>
694 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
695 of an opcode, prefer the one with F_PREFERRED set.
696 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
697 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
698 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
699 mark existing mnenomics as aliases. Add "cc" suffix to edge
700 instructions generating condition codes, mark existing mnenomics
701 as aliases. Add "fp" prefix to VIS compare instructions, mark
702 existing mnenomics as aliases.
704 2013-04-03 Nick Clifton <nickc@redhat.com>
706 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
707 destination address by subtracting the operand from the current
709 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
710 a positive value in the insn.
711 (extract_u16_loop): Do not negate the returned value.
712 (D16_LOOP): Add V850_INVERSE_PCREL flag.
714 (ceilf.sw): Remove duplicate entry.
715 (cvtf.hs): New entry.
721 (maddf.s): Restrict to E3V5 architectures.
723 (nmaddf.s): Likewise.
724 (nmsubf.s): Likewise.
726 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
728 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
730 (print_insn): Pass sizeflag to get_sib.
732 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
735 * tic6x-dis.c: Add support for displaying 16-bit insns.
737 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
740 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
741 individual msb and lsb halves in src1 & src2 fields. Discard the
742 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
743 follow what Ti SDK does in that case as any value in the src1
744 field yields the same output with SDK disassembler.
746 2013-03-12 Michael Eager <eager@eagercon.com>
748 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
750 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
752 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
754 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
756 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
758 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
760 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
762 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
764 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
765 (thumb32_opcodes): Likewise.
766 (print_insn_thumb32): Handle 'S' control char.
768 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
770 * lm32-desc.c: Regenerate.
772 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
774 * i386-reg.tbl (riz): Add RegRex64.
775 * i386-tbl.h: Regenerated.
777 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
779 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
780 (aarch64_feature_crc): New static.
782 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
783 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
784 * aarch64-asm-2.c: Re-generate.
785 * aarch64-dis-2.c: Ditto.
786 * aarch64-opc-2.c: Ditto.
788 2013-02-27 Alan Modra <amodra@gmail.com>
790 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
791 * rl78-decode.c: Regenerate.
793 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
795 * rl78-decode.opc: Fix encoding of DIVWU insn.
796 * rl78-decode.c: Regenerate.
798 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
801 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
803 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
804 (cpu_flags): Add CpuSMAP.
806 * i386-opc.h (CpuSMAP): New.
807 (i386_cpu_flags): Add cpusmap.
809 * i386-opc.tbl: Add clac and stac.
811 * i386-init.h: Regenerated.
812 * i386-tbl.h: Likewise.
814 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
816 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
817 which also makes the disassembler output be in little
818 endian like it should be.
820 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
822 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
824 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
826 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
828 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
829 section disassembled.
831 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
833 * arm-dis.c: Update strht pattern.
835 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
837 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
838 single-float. Disable ll, lld, sc and scd for EE. Disable the
839 trunc.w.s macro for EE.
841 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
842 Andrew Jenner <andrew@codesourcery.com>
844 Based on patches from Altera Corporation.
846 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
848 * Makefile.in: Regenerated.
849 * configure.in: Add case for bfd_nios2_arch.
850 * configure: Regenerated.
851 * disassemble.c (ARCH_nios2): Define.
852 (disassembler): Add case for bfd_arch_nios2.
853 * nios2-dis.c: New file.
854 * nios2-opc.c: New file.
856 2013-02-04 Alan Modra <amodra@gmail.com>
858 * po/POTFILES.in: Regenerate.
859 * rl78-decode.c: Regenerate.
860 * rx-decode.c: Regenerate.
862 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
864 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
865 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
866 * aarch64-asm.c (convert_xtl_to_shll): New function.
867 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
868 calling convert_xtl_to_shll.
869 * aarch64-dis.c (convert_shll_to_xtl): New function.
870 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
871 calling convert_shll_to_xtl.
872 * aarch64-gen.c: Update copyright year.
873 * aarch64-asm-2.c: Re-generate.
874 * aarch64-dis-2.c: Re-generate.
875 * aarch64-opc-2.c: Re-generate.
877 2013-01-24 Nick Clifton <nickc@redhat.com>
879 * v850-dis.c: Add support for e3v5 architecture.
880 * v850-opc.c: Likewise.
882 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
884 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
885 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
886 * aarch64-opc.c (operand_general_constraint_met_p): For
887 AARCH64_MOD_LSL, move the range check on the shift amount before the
888 alignment check; change to call set_sft_amount_out_of_range_error
889 instead of set_imm_out_of_range_error.
890 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
891 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
892 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
895 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
897 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
899 * i386-init.h: Regenerated.
900 * i386-tbl.h: Likewise.
902 2013-01-15 Nick Clifton <nickc@redhat.com>
904 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
906 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
908 2013-01-14 Will Newton <will.newton@imgtec.com>
910 * metag-dis.c (REG_WIDTH): Increase to 64.
912 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
914 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
915 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
916 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
918 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
919 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
920 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
921 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
923 2013-01-10 Will Newton <will.newton@imgtec.com>
925 * Makefile.am: Add Meta.
926 * configure.in: Add Meta.
927 * disassemble.c: Add Meta support.
928 * metag-dis.c: New file.
929 * Makefile.in: Regenerate.
930 * configure: Regenerate.
932 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
934 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
935 (match_opcode): Rename to cr16_match_opcode.
937 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
939 * mips-dis.c: Add names for CP0 registers of r5900.
940 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
941 instructions sq and lq.
942 Add support for MIPS r5900 CPU.
943 Add support for 128 bit MMI (Multimedia Instructions).
944 Add support for EE instructions (Emotion Engine).
945 Disable unsupported floating point instructions (64 bit and
946 undefined compare operations).
947 Enable instructions of MIPS ISA IV which are supported by r5900.
948 Disable 64 bit co processor instructions.
949 Disable 64 bit multiplication and division instructions.
950 Disable instructions for co-processor 2 and 3, because these are
951 not supported (preparation for later VU0 support (Vector Unit)).
952 Disable cvt.w.s because this behaves like trunc.w.s and the
953 correct execution can't be ensured on r5900.
954 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
955 will confuse less developers and compilers.
957 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
959 * aarch64-opc.c (aarch64_print_operand): Change to print
960 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
962 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
963 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
966 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
968 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
969 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
971 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
973 * i386-gen.c (process_copyright): Update copyright year to 2013.
975 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
977 * cr16-dis.c (match_opcode,make_instruction): Remove static
979 (dwordU,wordU): Moved typedefs to opcode/cr16.h
980 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
982 For older changes see ChangeLog-2012
984 Copyright (C) 2013 Free Software Foundation, Inc.
986 Copying and distribution of this file, with or without modification,
987 are permitted in any medium without royalty provided the copyright
988 notice and this notice are preserved.
994 version-control: never