1 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
3 * mips-dis.c (is_mips16_plt_tail): New function.
4 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
6 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
8 2013-06-21 DJ Delorie <dj@redhat.com>
10 * msp430-decode.opc: New.
11 * msp430-decode.c: New/generated.
12 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
13 (MAINTAINER_CLEANFILES): Likewise.
14 Add rule to build msp430-decode.c frommsp430decode.opc
15 using the opc2c program.
16 * Makefile.in: Regenerate.
17 * configure.in: Add msp430-decode.lo to msp430 architecture files.
18 * configure: Regenerate.
20 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
22 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
23 (SYMTAB_AVAILABLE): Removed.
24 (#include "elf/aarch64.h): Ditto.
26 2013-06-17 Catherine Moore <clm@codesourcery.com>
27 Maciej W. Rozycki <macro@codesourcery.com>
28 Chao-Ying Fu <fu@mips.com>
30 * micromips-opc.c (EVA): Define.
32 (micromips_opcodes): Add EVA opcodes.
33 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
34 (print_insn_args): Handle EVA offsets.
35 (print_insn_micromips): Likewise.
36 * mips-opc.c (EVA): Define.
38 (mips_builtin_opcodes): Add EVA opcodes.
40 2013-06-17 Alan Modra <amodra@gmail.com>
42 * Makefile.am (mips-opc.lo): Add rules to create automatic
43 dependency files. Pass archdefs.
44 (micromips-opc.lo, mips16-opc.lo): Likewise.
45 * Makefile.in: Regenerate.
47 2013-06-14 DJ Delorie <dj@redhat.com>
49 * rx-decode.opc (rx_decode_opcode): Bit operations on
50 registers are 32-bit operations, not 8-bit operations.
51 * rx-decode.c: Regenerate.
53 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
55 * micromips-opc.c (IVIRT): New define.
56 (IVIRT64): New define.
57 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
58 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
60 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
61 dmtgc0 to print cp0 names.
63 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
65 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
68 2013-06-08 Catherine Moore <clm@codesourcery.com>
69 Richard Sandiford <rdsandiford@googlemail.com>
71 * micromips-opc.c (D32, D33, MC): Update definitions.
72 (micromips_opcodes): Initialize ase field.
73 * mips-dis.c (mips_arch_choice): Add ase field.
74 (mips_arch_choices): Initialize ase field.
75 (set_default_mips_dis_options): Declare and setup mips_ase.
76 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
77 MT32, MC): Update definitions.
78 (mips_builtin_opcodes): Initialize ase field.
80 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
82 * s390-opc.txt (flogr): Require a register pair destination.
84 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
86 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
89 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
91 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
93 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
95 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
96 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
97 XLS_MASK, PPCVSX2): New defines.
98 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
99 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
100 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
101 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
102 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
103 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
104 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
105 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
106 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
107 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
108 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
109 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
110 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
111 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
112 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
113 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
114 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
115 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
116 <lxvx, stxvx>: New extended mnemonics.
118 2013-05-17 Alan Modra <amodra@gmail.com>
120 * ia64-raw.tbl: Replace non-ASCII char.
121 * ia64-waw.tbl: Likewise.
122 * ia64-asmtab.c: Regenerate.
124 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
126 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
127 * i386-init.h: Regenerated.
129 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
131 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
132 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
133 check from [0, 255] to [-128, 255].
135 2013-05-09 Andrew Pinski <apinski@cavium.com>
137 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
138 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
139 (parse_mips_dis_option): Handle the virt option.
140 (print_insn_args): Handle "+J".
141 (print_mips_disassembler_options): Print out message about virt64.
142 * mips-opc.c (IVIRT): New define.
143 (IVIRT64): New define.
144 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
145 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
146 Move rfe to the bottom as it conflicts with tlbgp.
148 2013-05-09 Alan Modra <amodra@gmail.com>
150 * ppc-opc.c (extract_vlesi): Properly sign extend.
151 (extract_vlensi): Likewise. Comment reason for setting invalid.
153 2013-05-02 Nick Clifton <nickc@redhat.com>
155 * msp430-dis.c: Add support for MSP430X instructions.
157 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
159 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
162 2013-04-17 Wei-chen Wang <cole945@gmail.com>
165 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
167 (hash_insns_list): Likewise.
169 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
171 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
174 2013-04-08 Jan Beulich <jbeulich@suse.com>
176 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
177 * i386-tbl.h: Re-generate.
179 2013-04-06 David S. Miller <davem@davemloft.net>
181 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
182 of an opcode, prefer the one with F_PREFERRED set.
183 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
184 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
185 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
186 mark existing mnenomics as aliases. Add "cc" suffix to edge
187 instructions generating condition codes, mark existing mnenomics
188 as aliases. Add "fp" prefix to VIS compare instructions, mark
189 existing mnenomics as aliases.
191 2013-04-03 Nick Clifton <nickc@redhat.com>
193 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
194 destination address by subtracting the operand from the current
196 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
197 a positive value in the insn.
198 (extract_u16_loop): Do not negate the returned value.
199 (D16_LOOP): Add V850_INVERSE_PCREL flag.
201 (ceilf.sw): Remove duplicate entry.
202 (cvtf.hs): New entry.
208 (maddf.s): Restrict to E3V5 architectures.
210 (nmaddf.s): Likewise.
211 (nmsubf.s): Likewise.
213 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
215 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
217 (print_insn): Pass sizeflag to get_sib.
219 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
222 * tic6x-dis.c: Add support for displaying 16-bit insns.
224 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
227 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
228 individual msb and lsb halves in src1 & src2 fields. Discard the
229 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
230 follow what Ti SDK does in that case as any value in the src1
231 field yields the same output with SDK disassembler.
233 2013-03-12 Michael Eager <eager@eagercon.com>
235 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
237 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
239 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
241 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
243 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
245 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
247 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
249 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
251 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
252 (thumb32_opcodes): Likewise.
253 (print_insn_thumb32): Handle 'S' control char.
255 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
257 * lm32-desc.c: Regenerate.
259 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
261 * i386-reg.tbl (riz): Add RegRex64.
262 * i386-tbl.h: Regenerated.
264 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
266 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
267 (aarch64_feature_crc): New static.
269 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
270 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
271 * aarch64-asm-2.c: Re-generate.
272 * aarch64-dis-2.c: Ditto.
273 * aarch64-opc-2.c: Ditto.
275 2013-02-27 Alan Modra <amodra@gmail.com>
277 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
278 * rl78-decode.c: Regenerate.
280 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
282 * rl78-decode.opc: Fix encoding of DIVWU insn.
283 * rl78-decode.c: Regenerate.
285 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
288 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
290 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
291 (cpu_flags): Add CpuSMAP.
293 * i386-opc.h (CpuSMAP): New.
294 (i386_cpu_flags): Add cpusmap.
296 * i386-opc.tbl: Add clac and stac.
298 * i386-init.h: Regenerated.
299 * i386-tbl.h: Likewise.
301 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
303 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
304 which also makes the disassembler output be in little
305 endian like it should be.
307 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
309 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
311 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
313 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
315 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
316 section disassembled.
318 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
320 * arm-dis.c: Update strht pattern.
322 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
324 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
325 single-float. Disable ll, lld, sc and scd for EE. Disable the
326 trunc.w.s macro for EE.
328 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
329 Andrew Jenner <andrew@codesourcery.com>
331 Based on patches from Altera Corporation.
333 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
335 * Makefile.in: Regenerated.
336 * configure.in: Add case for bfd_nios2_arch.
337 * configure: Regenerated.
338 * disassemble.c (ARCH_nios2): Define.
339 (disassembler): Add case for bfd_arch_nios2.
340 * nios2-dis.c: New file.
341 * nios2-opc.c: New file.
343 2013-02-04 Alan Modra <amodra@gmail.com>
345 * po/POTFILES.in: Regenerate.
346 * rl78-decode.c: Regenerate.
347 * rx-decode.c: Regenerate.
349 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
351 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
352 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
353 * aarch64-asm.c (convert_xtl_to_shll): New function.
354 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
355 calling convert_xtl_to_shll.
356 * aarch64-dis.c (convert_shll_to_xtl): New function.
357 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
358 calling convert_shll_to_xtl.
359 * aarch64-gen.c: Update copyright year.
360 * aarch64-asm-2.c: Re-generate.
361 * aarch64-dis-2.c: Re-generate.
362 * aarch64-opc-2.c: Re-generate.
364 2013-01-24 Nick Clifton <nickc@redhat.com>
366 * v850-dis.c: Add support for e3v5 architecture.
367 * v850-opc.c: Likewise.
369 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
371 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
372 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
373 * aarch64-opc.c (operand_general_constraint_met_p): For
374 AARCH64_MOD_LSL, move the range check on the shift amount before the
375 alignment check; change to call set_sft_amount_out_of_range_error
376 instead of set_imm_out_of_range_error.
377 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
378 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
379 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
382 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
384 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
386 * i386-init.h: Regenerated.
387 * i386-tbl.h: Likewise.
389 2013-01-15 Nick Clifton <nickc@redhat.com>
391 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
393 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
395 2013-01-14 Will Newton <will.newton@imgtec.com>
397 * metag-dis.c (REG_WIDTH): Increase to 64.
399 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
401 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
402 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
403 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
405 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
406 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
407 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
408 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
410 2013-01-10 Will Newton <will.newton@imgtec.com>
412 * Makefile.am: Add Meta.
413 * configure.in: Add Meta.
414 * disassemble.c: Add Meta support.
415 * metag-dis.c: New file.
416 * Makefile.in: Regenerate.
417 * configure: Regenerate.
419 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
421 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
422 (match_opcode): Rename to cr16_match_opcode.
424 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
426 * mips-dis.c: Add names for CP0 registers of r5900.
427 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
428 instructions sq and lq.
429 Add support for MIPS r5900 CPU.
430 Add support for 128 bit MMI (Multimedia Instructions).
431 Add support for EE instructions (Emotion Engine).
432 Disable unsupported floating point instructions (64 bit and
433 undefined compare operations).
434 Enable instructions of MIPS ISA IV which are supported by r5900.
435 Disable 64 bit co processor instructions.
436 Disable 64 bit multiplication and division instructions.
437 Disable instructions for co-processor 2 and 3, because these are
438 not supported (preparation for later VU0 support (Vector Unit)).
439 Disable cvt.w.s because this behaves like trunc.w.s and the
440 correct execution can't be ensured on r5900.
441 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
442 will confuse less developers and compilers.
444 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
446 * aarch64-opc.c (aarch64_print_operand): Change to print
447 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
449 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
450 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
453 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
455 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
456 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
458 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
460 * i386-gen.c (process_copyright): Update copyright year to 2013.
462 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
464 * cr16-dis.c (match_opcode,make_instruction): Remove static
466 (dwordU,wordU): Moved typedefs to opcode/cr16.h
467 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
469 For older changes see ChangeLog-2012
471 Copyright (C) 2013 Free Software Foundation, Inc.
473 Copying and distribution of this file, with or without modification,
474 are permitted in any medium without royalty provided the copyright
475 notice and this notice are preserved.
481 version-control: never