1 2018-07-27 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (insert_sprbat): Correct function parameter and
5 (extract_sprbat): Likewise, variable too.
7 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
8 Alan Modra <amodra@gmail.com>
10 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
11 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
12 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
13 support disjointed BAT.
14 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
15 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
16 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
18 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
19 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
21 * i386-gen.c (adjust_broadcast_modifier): New function.
22 (process_i386_opcode_modifier): Add an argument for operands.
23 Adjust the Broadcast value based on operands.
24 (output_i386_opcode): Pass operand_types to
25 process_i386_opcode_modifier.
26 (process_i386_opcodes): Pass NULL as operands to
27 process_i386_opcode_modifier.
28 * i386-opc.h (BYTE_BROADCAST): New.
29 (WORD_BROADCAST): Likewise.
30 (DWORD_BROADCAST): Likewise.
31 (QWORD_BROADCAST): Likewise.
32 (i386_opcode_modifier): Expand broadcast to 3 bits.
33 * i386-tbl.h: Regenerated.
35 2018-07-24 Alan Modra <amodra@gmail.com>
38 * or1k-desc.h: Regenerate.
40 2018-07-24 Jan Beulich <jbeulich@suse.com>
42 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
43 vcvtusi2ss, and vcvtusi2sd.
44 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
45 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
46 * i386-tbl.h: Re-generate.
48 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
50 * arc-opc.c (extract_w6): Fix extending the sign.
52 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
54 * arc-tbl.h (vewt): Allow it for ARC EM family.
56 2018-07-23 Alan Modra <amodra@gmail.com>
59 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
60 opcode variants for mtspr/mfspr encodings.
62 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
63 Maciej W. Rozycki <macro@mips.com>
65 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
66 loongson3a descriptors.
67 (parse_mips_ase_option): Handle -M loongson-mmi option.
68 (print_mips_disassembler_options): Document -M loongson-mmi.
69 * mips-opc.c (LMMI): New macro.
70 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
73 2018-07-19 Jan Beulich <jbeulich@suse.com>
75 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
76 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
77 IgnoreSize and [XYZ]MMword where applicable.
78 * i386-tbl.h: Re-generate.
80 2018-07-19 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
83 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
84 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
85 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
86 * i386-tbl.h: Re-generate.
88 2018-07-19 Jan Beulich <jbeulich@suse.com>
90 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
91 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
92 VPCLMULQDQ templates into their respective AVX512VL counterparts
93 where possible, using Disp8ShiftVL and CheckRegSize instead of
94 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
95 * i386-tbl.h: Re-generate.
97 2018-07-19 Jan Beulich <jbeulich@suse.com>
99 * i386-opc.tbl: Fold AVX512DQ templates into their respective
100 AVX512VL counterparts where possible, using Disp8ShiftVL and
101 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
102 IgnoreSize) as appropriate.
103 * i386-tbl.h: Re-generate.
105 2018-07-19 Jan Beulich <jbeulich@suse.com>
107 * i386-opc.tbl: Fold AVX512BW templates into their respective
108 AVX512VL counterparts where possible, using Disp8ShiftVL and
109 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
110 IgnoreSize) as appropriate.
111 * i386-tbl.h: Re-generate.
113 2018-07-19 Jan Beulich <jbeulich@suse.com>
115 * i386-opc.tbl: Fold AVX512CD templates into their respective
116 AVX512VL counterparts where possible, using Disp8ShiftVL and
117 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
118 IgnoreSize) as appropriate.
119 * i386-tbl.h: Re-generate.
121 2018-07-19 Jan Beulich <jbeulich@suse.com>
123 * i386-opc.h (DISP8_SHIFT_VL): New.
124 * i386-opc.tbl (Disp8ShiftVL): Define.
125 (various): Fold AVX512VL templates into their respective
126 AVX512F counterparts where possible, using Disp8ShiftVL and
127 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
128 IgnoreSize) as appropriate.
129 * i386-tbl.h: Re-generate.
131 2018-07-19 Jan Beulich <jbeulich@suse.com>
133 * Makefile.am: Change dependencies and rule for
134 $(srcdir)/i386-init.h.
135 * Makefile.in: Re-generate.
136 * i386-gen.c (process_i386_opcodes): New local variable
137 "marker". Drop opening of input file. Recognize marker and line
139 * i386-opc.tbl (OPCODE_I386_H): Define.
140 (i386-opc.h): Include it.
143 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
146 * i386-opc.h (Byte): Update comments.
155 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
157 * i386-tbl.h: Regenerated.
159 2018-07-12 Sudakshina Das <sudi.das@arm.com>
161 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
162 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
163 * aarch64-asm-2.c: Regenerate.
164 * aarch64-dis-2.c: Regenerate.
165 * aarch64-opc-2.c: Regenerate.
167 2018-07-12 Tamar Christina <tamar.christina@arm.com>
170 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
171 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
172 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
173 sqdmulh, sqrdmulh): Use Em16.
175 2018-07-11 Sudakshina Das <sudi.das@arm.com>
177 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
178 csdb together with them.
179 (thumb32_opcodes): Likewise.
181 2018-07-11 Jan Beulich <jbeulich@suse.com>
183 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
184 requiring 32-bit registers as operands 2 and 3. Improve
186 (mwait, mwaitx): Fold templates. Improve comments.
187 OPERAND_TYPE_INOUTPORTREG.
188 * i386-tbl.h: Re-generate.
190 2018-07-11 Jan Beulich <jbeulich@suse.com>
192 * i386-gen.c (operand_type_init): Remove
193 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
194 OPERAND_TYPE_INOUTPORTREG.
195 * i386-init.h: Re-generate.
197 2018-07-11 Jan Beulich <jbeulich@suse.com>
199 * i386-opc.tbl (wrssd, wrussd): Add Dword.
200 (wrssq, wrussq): Add Qword.
201 * i386-tbl.h: Re-generate.
203 2018-07-11 Jan Beulich <jbeulich@suse.com>
205 * i386-opc.h: Rename OTMax to OTNum.
206 (OTNumOfUints): Adjust calculation.
207 (OTUnused): Directly alias to OTNum.
209 2018-07-09 Maciej W. Rozycki <macro@mips.com>
211 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
213 (lea_reg_xys): Likewise.
214 (print_insn_loop_primitive): Rename `reg' local variable to
217 2018-07-06 Tamar Christina <tamar.christina@arm.com>
220 * aarch64-tbl.h (ldarh): Fix disassembly mask.
222 2018-07-06 Tamar Christina <tamar.christina@arm.com>
225 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
226 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
228 2018-07-02 Maciej W. Rozycki <macro@mips.com>
231 * mips-dis.c (mips_option_arg_t): New enumeration.
232 (mips_options): New variable.
233 (disassembler_options_mips): New function.
234 (print_mips_disassembler_options): Reimplement in terms of
235 `disassembler_options_mips'.
236 * arm-dis.c (disassembler_options_arm): Adapt to using the
237 `disasm_options_and_args_t' structure.
238 * ppc-dis.c (disassembler_options_powerpc): Likewise.
239 * s390-dis.c (disassembler_options_s390): Likewise.
241 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
243 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
245 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
246 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
247 * testsuite/ld-arm/tls-longplt.d: Likewise.
249 2018-06-29 Tamar Christina <tamar.christina@arm.com>
252 * aarch64-asm-2.c: Regenerate.
253 * aarch64-dis-2.c: Likewise.
254 * aarch64-opc-2.c: Likewise.
255 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
256 * aarch64-opc.c (operand_general_constraint_met_p,
257 aarch64_print_operand): Likewise.
258 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
259 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
261 (AARCH64_OPERANDS): Add Em2.
263 2018-06-26 Nick Clifton <nickc@redhat.com>
265 * po/uk.po: Updated Ukranian translation.
266 * po/de.po: Updated German translation.
267 * po/pt_BR.po: Updated Brazilian Portuguese translation.
269 2018-06-26 Nick Clifton <nickc@redhat.com>
271 * nfp-dis.c: Fix spelling mistake.
273 2018-06-24 Nick Clifton <nickc@redhat.com>
275 * configure: Regenerate.
276 * po/opcodes.pot: Regenerate.
278 2018-06-24 Nick Clifton <nickc@redhat.com>
282 2018-06-19 Tamar Christina <tamar.christina@arm.com>
284 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
285 * aarch64-asm-2.c: Regenerate.
286 * aarch64-dis-2.c: Likewise.
288 2018-06-21 Maciej W. Rozycki <macro@mips.com>
290 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
291 `-M ginv' option description.
293 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
296 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
299 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
301 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
302 * configure.ac: Remove AC_PREREQ.
303 * Makefile.in: Re-generate.
304 * aclocal.m4: Re-generate.
305 * configure: Re-generate.
307 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
309 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
310 mips64r6 descriptors.
311 (parse_mips_ase_option): Handle -Mginv option.
312 (print_mips_disassembler_options): Document -Mginv.
313 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
315 (mips_opcodes): Define ginvi and ginvt.
317 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
318 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
320 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
321 * mips-opc.c (CRC, CRC64): New macros.
322 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
323 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
326 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
329 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
330 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
332 2018-06-06 Alan Modra <amodra@gmail.com>
334 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
335 setjmp. Move init for some other vars later too.
337 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
339 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
340 (dis_private): Add new fields for property section tracking.
341 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
342 (xtensa_instruction_fits): New functions.
343 (fetch_data): Bump minimal fetch size to 4.
344 (print_insn_xtensa): Make struct dis_private static.
345 Load and prepare property table on section change.
346 Don't disassemble literals. Don't disassemble instructions that
347 cross property table boundaries.
349 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
351 * configure: Regenerated.
353 2018-06-01 Jan Beulich <jbeulich@suse.com>
355 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
356 * i386-tbl.h: Re-generate.
358 2018-06-01 Jan Beulich <jbeulich@suse.com>
360 * i386-opc.tbl (sldt, str): Add NoRex64.
361 * i386-tbl.h: Re-generate.
363 2018-06-01 Jan Beulich <jbeulich@suse.com>
365 * i386-opc.tbl (invpcid): Add Oword.
366 * i386-tbl.h: Re-generate.
368 2018-06-01 Alan Modra <amodra@gmail.com>
370 * sysdep.h (_bfd_error_handler): Don't declare.
371 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
372 * rl78-decode.opc: Likewise.
373 * msp430-decode.c: Regenerate.
374 * rl78-decode.c: Regenerate.
376 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
378 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
379 * i386-init.h : Regenerated.
381 2018-05-25 Alan Modra <amodra@gmail.com>
383 * Makefile.in: Regenerate.
384 * po/POTFILES.in: Regenerate.
386 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
388 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
389 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
390 (insert_bab, extract_bab, insert_btab, extract_btab,
391 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
392 (BAT, BBA VBA RBS XB6S): Delete macros.
393 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
394 (BB, BD, RBX, XC6): Update for new macros.
395 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
396 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
397 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
398 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
400 2018-05-18 John Darrington <john@darrington.wattle.id.au>
402 * Makefile.am: Add support for s12z architecture.
403 * configure.ac: Likewise.
404 * disassemble.c: Likewise.
405 * disassemble.h: Likewise.
406 * Makefile.in: Regenerate.
407 * configure: Regenerate.
408 * s12z-dis.c: New file.
411 2018-05-18 Alan Modra <amodra@gmail.com>
413 * nfp-dis.c: Don't #include libbfd.h.
414 (init_nfp3200_priv): Use bfd_get_section_contents.
415 (nit_nfp6000_mecsr_sec): Likewise.
417 2018-05-17 Nick Clifton <nickc@redhat.com>
419 * po/zh_CN.po: Updated simplified Chinese translation.
421 2018-05-16 Tamar Christina <tamar.christina@arm.com>
424 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
425 * aarch64-dis-2.c: Regenerate.
427 2018-05-15 Tamar Christina <tamar.christina@arm.com>
430 * aarch64-asm.c (opintl.h): Include.
431 (aarch64_ins_sysreg): Enforce read/write constraints.
432 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
433 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
434 (F_REG_READ, F_REG_WRITE): New.
435 * aarch64-opc.c (aarch64_print_operand): Generate notes for
437 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
438 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
439 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
440 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
441 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
442 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
443 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
444 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
445 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
446 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
447 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
448 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
449 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
450 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
451 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
452 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
453 msr (F_SYS_WRITE), mrs (F_SYS_READ).
455 2018-05-15 Tamar Christina <tamar.christina@arm.com>
458 * aarch64-dis.c (no_notes: New.
459 (parse_aarch64_dis_option): Support notes.
460 (aarch64_decode_insn, print_operands): Likewise.
461 (print_aarch64_disassembler_options): Document notes.
462 * aarch64-opc.c (aarch64_print_operand): Support notes.
464 2018-05-15 Tamar Christina <tamar.christina@arm.com>
467 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
468 and take error struct.
469 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
470 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
471 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
472 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
473 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
474 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
475 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
476 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
477 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
478 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
479 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
480 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
481 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
482 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
483 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
484 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
485 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
486 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
487 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
488 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
489 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
490 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
491 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
492 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
493 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
494 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
495 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
496 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
497 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
498 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
499 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
500 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
501 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
502 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
503 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
504 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
505 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
506 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
507 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
508 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
509 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
510 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
511 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
512 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
513 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
514 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
515 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
516 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
517 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
518 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
519 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
520 (determine_disassembling_preference, aarch64_decode_insn,
521 print_insn_aarch64_word, print_insn_data): Take errors struct.
522 (print_insn_aarch64): Use errors.
523 * aarch64-asm-2.c: Regenerate.
524 * aarch64-dis-2.c: Regenerate.
525 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
526 boolean in aarch64_insert_operan.
527 (print_operand_extractor): Likewise.
528 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
530 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
532 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
534 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
536 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
538 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
540 * cr16-opc.c (cr16_instruction): Comment typo fix.
541 * hppa-dis.c (print_insn_hppa): Likewise.
543 2018-05-08 Jim Wilson <jimw@sifive.com>
545 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
546 (match_c_slli64, match_srxi_as_c_srxi): New.
547 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
548 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
549 <c.slli, c.srli, c.srai>: Use match_s_slli.
550 <c.slli64, c.srli64, c.srai64>: New.
552 2018-05-08 Alan Modra <amodra@gmail.com>
554 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
555 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
556 partition opcode space for index lookup.
558 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
560 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
561 <insn_length>: ...with this. Update usage.
562 Remove duplicate call to *info->memory_error_func.
564 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
565 H.J. Lu <hongjiu.lu@intel.com>
567 * i386-dis.c (Gva): New.
568 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
569 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
570 (prefix_table): New instructions (see prefix above).
571 (mod_table): New instructions (see prefix above).
572 (OP_G): Handle va_mode.
573 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
575 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
576 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
577 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
578 * i386-opc.tbl: Add movidir{i,64b}.
579 * i386-init.h: Regenerated.
580 * i386-tbl.h: Likewise.
582 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
584 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
586 * i386-opc.h (AddrPrefixOp0): Renamed to ...
587 (AddrPrefixOpReg): This.
588 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
589 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
591 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
593 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
594 (vle_num_opcodes): Likewise.
595 (spe2_num_opcodes): Likewise.
596 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
598 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
599 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
602 2018-05-01 Tamar Christina <tamar.christina@arm.com>
604 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
606 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
608 Makefile.am: Added nfp-dis.c.
609 configure.ac: Added bfd_nfp_arch.
610 disassemble.h: Added print_insn_nfp prototype.
611 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
612 nfp-dis.c: New, for NFP support.
613 po/POTFILES.in: Added nfp-dis.c to the list.
614 Makefile.in: Regenerate.
615 configure: Regenerate.
617 2018-04-26 Jan Beulich <jbeulich@suse.com>
619 * i386-opc.tbl: Fold various non-memory operand AVX512VL
620 templates into their base ones.
621 * i386-tlb.h: Re-generate.
623 2018-04-26 Jan Beulich <jbeulich@suse.com>
625 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
626 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
627 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
628 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
629 * i386-init.h: Re-generate.
631 2018-04-26 Jan Beulich <jbeulich@suse.com>
633 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
634 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
635 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
636 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
638 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
640 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
642 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
643 cpuregzmm, and cpuregmask.
644 * i386-init.h: Re-generate.
645 * i386-tbl.h: Re-generate.
647 2018-04-26 Jan Beulich <jbeulich@suse.com>
649 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
650 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
651 * i386-init.h: Re-generate.
653 2018-04-26 Jan Beulich <jbeulich@suse.com>
655 * i386-gen.c (VexImmExt): Delete.
656 * i386-opc.h (VexImmExt, veximmext): Delete.
657 * i386-opc.tbl: Drop all VexImmExt uses.
658 * i386-tlb.h: Re-generate.
660 2018-04-25 Jan Beulich <jbeulich@suse.com>
662 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
664 * i386-tlb.h: Re-generate.
666 2018-04-25 Tamar Christina <tamar.christina@arm.com>
668 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
670 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
672 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
674 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
675 (cpu_flags): Add CpuCLDEMOTE.
676 * i386-init.h: Regenerate.
677 * i386-opc.h (enum): Add CpuCLDEMOTE,
678 (i386_cpu_flags): Add cpucldemote.
679 * i386-opc.tbl: Add cldemote.
680 * i386-tbl.h: Regenerate.
682 2018-04-16 Alan Modra <amodra@gmail.com>
684 * Makefile.am: Remove sh5 and sh64 support.
685 * configure.ac: Likewise.
686 * disassemble.c: Likewise.
687 * disassemble.h: Likewise.
688 * sh-dis.c: Likewise.
689 * sh64-dis.c: Delete.
690 * sh64-opc.c: Delete.
691 * sh64-opc.h: Delete.
692 * Makefile.in: Regenerate.
693 * configure: Regenerate.
694 * po/POTFILES.in: Regenerate.
696 2018-04-16 Alan Modra <amodra@gmail.com>
698 * Makefile.am: Remove w65 support.
699 * configure.ac: Likewise.
700 * disassemble.c: Likewise.
701 * disassemble.h: Likewise.
704 * Makefile.in: Regenerate.
705 * configure: Regenerate.
706 * po/POTFILES.in: Regenerate.
708 2018-04-16 Alan Modra <amodra@gmail.com>
710 * configure.ac: Remove we32k support.
711 * configure: Regenerate.
713 2018-04-16 Alan Modra <amodra@gmail.com>
715 * Makefile.am: Remove m88k support.
716 * configure.ac: Likewise.
717 * disassemble.c: Likewise.
718 * disassemble.h: Likewise.
719 * m88k-dis.c: Delete.
720 * Makefile.in: Regenerate.
721 * configure: Regenerate.
722 * po/POTFILES.in: Regenerate.
724 2018-04-16 Alan Modra <amodra@gmail.com>
726 * Makefile.am: Remove i370 support.
727 * configure.ac: Likewise.
728 * disassemble.c: Likewise.
729 * disassemble.h: Likewise.
730 * i370-dis.c: Delete.
731 * i370-opc.c: Delete.
732 * Makefile.in: Regenerate.
733 * configure: Regenerate.
734 * po/POTFILES.in: Regenerate.
736 2018-04-16 Alan Modra <amodra@gmail.com>
738 * Makefile.am: Remove h8500 support.
739 * configure.ac: Likewise.
740 * disassemble.c: Likewise.
741 * disassemble.h: Likewise.
742 * h8500-dis.c: Delete.
743 * h8500-opc.h: Delete.
744 * Makefile.in: Regenerate.
745 * configure: Regenerate.
746 * po/POTFILES.in: Regenerate.
748 2018-04-16 Alan Modra <amodra@gmail.com>
750 * configure.ac: Remove tahoe support.
751 * configure: Regenerate.
753 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
755 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
757 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
759 * i386-tbl.h: Regenerated.
761 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
763 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
764 PREFIX_MOD_1_0FAE_REG_6.
766 (OP_E_register): Use va_mode.
767 * i386-dis-evex.h (prefix_table):
768 New instructions (see prefixes above).
769 * i386-gen.c (cpu_flag_init): Add WAITPKG.
770 (cpu_flags): Likewise.
771 * i386-opc.h (enum): Likewise.
772 (i386_cpu_flags): Likewise.
773 * i386-opc.tbl: Add umonitor, umwait, tpause.
774 * i386-init.h: Regenerate.
775 * i386-tbl.h: Likewise.
777 2018-04-11 Alan Modra <amodra@gmail.com>
779 * opcodes/i860-dis.c: Delete.
780 * opcodes/i960-dis.c: Delete.
781 * Makefile.am: Remove i860 and i960 support.
782 * configure.ac: Likewise.
783 * disassemble.c: Likewise.
784 * disassemble.h: Likewise.
785 * Makefile.in: Regenerate.
786 * configure: Regenerate.
787 * po/POTFILES.in: Regenerate.
789 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
794 (print_insn): Clear vex instead of vex.evex.
796 2018-04-04 Nick Clifton <nickc@redhat.com>
798 * po/es.po: Updated Spanish translation.
800 2018-03-28 Jan Beulich <jbeulich@suse.com>
802 * i386-gen.c (opcode_modifiers): Delete VecESize.
803 * i386-opc.h (VecESize): Delete.
804 (struct i386_opcode_modifier): Delete vecesize.
805 * i386-opc.tbl: Drop VecESize.
806 * i386-tlb.h: Re-generate.
808 2018-03-28 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
811 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
812 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
813 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
814 * i386-tlb.h: Re-generate.
816 2018-03-28 Jan Beulich <jbeulich@suse.com>
818 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
820 * i386-tlb.h: Re-generate.
822 2018-03-28 Jan Beulich <jbeulich@suse.com>
824 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
825 (vex_len_table): Drop Y for vcvt*2si.
826 (putop): Replace plain 'Y' handling by abort().
828 2018-03-28 Nick Clifton <nickc@redhat.com>
831 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
832 instructions with only a base address register.
833 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
834 handle AARHC64_OPND_SVE_ADDR_R.
835 (aarch64_print_operand): Likewise.
836 * aarch64-asm-2.c: Regenerate.
837 * aarch64_dis-2.c: Regenerate.
838 * aarch64-opc-2.c: Regenerate.
840 2018-03-22 Jan Beulich <jbeulich@suse.com>
842 * i386-opc.tbl: Drop VecESize from register only insn forms and
843 memory forms not allowing broadcast.
844 * i386-tlb.h: Re-generate.
846 2018-03-22 Jan Beulich <jbeulich@suse.com>
848 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
849 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
850 sha256*): Drop Disp<N>.
852 2018-03-22 Jan Beulich <jbeulich@suse.com>
854 * i386-dis.c (EbndS, bnd_swap_mode): New.
855 (prefix_table): Use EbndS.
856 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
857 * i386-opc.tbl (bndmov): Move misplaced Load.
858 * i386-tlb.h: Re-generate.
860 2018-03-22 Jan Beulich <jbeulich@suse.com>
862 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
863 templates allowing memory operands and folded ones for register
865 * i386-tlb.h: Re-generate.
867 2018-03-22 Jan Beulich <jbeulich@suse.com>
869 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
870 256-bit templates. Drop redundant leftover Disp<N>.
871 * i386-tlb.h: Re-generate.
873 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
875 * riscv-opc.c (riscv_insn_types): New.
877 2018-03-13 Nick Clifton <nickc@redhat.com>
879 * po/pt_BR.po: Updated Brazilian Portuguese translation.
881 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
883 * i386-opc.tbl: Add Optimize to clr.
884 * i386-tbl.h: Regenerated.
886 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
888 * i386-gen.c (opcode_modifiers): Remove OldGcc.
889 * i386-opc.h (OldGcc): Removed.
890 (i386_opcode_modifier): Remove oldgcc.
891 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
892 instructions for old (<= 2.8.1) versions of gcc.
893 * i386-tbl.h: Regenerated.
895 2018-03-08 Jan Beulich <jbeulich@suse.com>
897 * i386-opc.h (EVEXDYN): New.
898 * i386-opc.tbl: Fold various AVX512VL templates.
899 * i386-tlb.h: Re-generate.
901 2018-03-08 Jan Beulich <jbeulich@suse.com>
903 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
904 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
905 vpexpandd, vpexpandq): Fold AFX512VF templates.
906 * i386-tlb.h: Re-generate.
908 2018-03-08 Jan Beulich <jbeulich@suse.com>
910 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
911 Fold 128- and 256-bit VEX-encoded templates.
912 * i386-tlb.h: Re-generate.
914 2018-03-08 Jan Beulich <jbeulich@suse.com>
916 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
917 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
918 vpexpandd, vpexpandq): Fold AVX512F templates.
919 * i386-tlb.h: Re-generate.
921 2018-03-08 Jan Beulich <jbeulich@suse.com>
923 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
924 64-bit templates. Drop Disp<N>.
925 * i386-tlb.h: Re-generate.
927 2018-03-08 Jan Beulich <jbeulich@suse.com>
929 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
930 and 256-bit templates.
931 * i386-tlb.h: Re-generate.
933 2018-03-08 Jan Beulich <jbeulich@suse.com>
935 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
936 * i386-tlb.h: Re-generate.
938 2018-03-08 Jan Beulich <jbeulich@suse.com>
940 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
942 * i386-tlb.h: Re-generate.
944 2018-03-08 Jan Beulich <jbeulich@suse.com>
946 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
947 * i386-tlb.h: Re-generate.
949 2018-03-08 Jan Beulich <jbeulich@suse.com>
951 * i386-gen.c (opcode_modifiers): Delete FloatD.
952 * i386-opc.h (FloatD): Delete.
953 (struct i386_opcode_modifier): Delete floatd.
954 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
956 * i386-tlb.h: Re-generate.
958 2018-03-08 Jan Beulich <jbeulich@suse.com>
960 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
962 2018-03-08 Jan Beulich <jbeulich@suse.com>
964 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
965 * i386-tlb.h: Re-generate.
967 2018-03-08 Jan Beulich <jbeulich@suse.com>
969 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
971 * i386-tlb.h: Re-generate.
973 2018-03-07 Alan Modra <amodra@gmail.com>
975 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
977 * disassemble.h (print_insn_rs6000): Delete.
978 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
979 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
980 (print_insn_rs6000): Delete.
982 2018-03-03 Alan Modra <amodra@gmail.com>
984 * sysdep.h (opcodes_error_handler): Define.
985 (_bfd_error_handler): Declare.
986 * Makefile.am: Remove stray #.
987 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
989 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
990 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
991 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
992 opcodes_error_handler to print errors. Standardize error messages.
993 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
994 and include opintl.h.
995 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
996 * i386-gen.c: Standardize error messages.
997 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
998 * Makefile.in: Regenerate.
999 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1000 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1001 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1002 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1003 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1004 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1005 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1006 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1007 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1008 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1009 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1010 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1011 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1013 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1015 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1016 vpsub[bwdq] instructions.
1017 * i386-tbl.h: Regenerated.
1019 2018-03-01 Alan Modra <amodra@gmail.com>
1021 * configure.ac (ALL_LINGUAS): Sort.
1022 * configure: Regenerate.
1024 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1026 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1027 macro by assignements.
1029 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1032 * i386-gen.c (opcode_modifiers): Add Optimize.
1033 * i386-opc.h (Optimize): New enum.
1034 (i386_opcode_modifier): Add optimize.
1035 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1036 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1037 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1038 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1039 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1041 * i386-tbl.h: Regenerated.
1043 2018-02-26 Alan Modra <amodra@gmail.com>
1045 * crx-dis.c (getregliststring): Allocate a large enough buffer
1046 to silence false positive gcc8 warning.
1048 2018-02-22 Shea Levy <shea@shealevy.com>
1050 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1052 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386-opc.tbl: Add {rex},
1055 * i386-tbl.h: Regenerated.
1057 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1059 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1060 (mips16_opcodes): Replace `M' with `m' for "restore".
1062 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1064 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1066 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1068 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1069 variable to `function_index'.
1071 2018-02-13 Nick Clifton <nickc@redhat.com>
1074 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1075 about truncation of printing.
1077 2018-02-12 Henry Wong <henry@stuffedcow.net>
1079 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1081 2018-02-05 Nick Clifton <nickc@redhat.com>
1083 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1085 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1087 * i386-dis.c (enum): Add pconfig.
1088 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1089 (cpu_flags): Add CpuPCONFIG.
1090 * i386-opc.h (enum): Add CpuPCONFIG.
1091 (i386_cpu_flags): Add cpupconfig.
1092 * i386-opc.tbl: Add PCONFIG instruction.
1093 * i386-init.h: Regenerate.
1094 * i386-tbl.h: Likewise.
1096 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1098 * i386-dis.c (enum): Add PREFIX_0F09.
1099 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1100 (cpu_flags): Add CpuWBNOINVD.
1101 * i386-opc.h (enum): Add CpuWBNOINVD.
1102 (i386_cpu_flags): Add cpuwbnoinvd.
1103 * i386-opc.tbl: Add WBNOINVD instruction.
1104 * i386-init.h: Regenerate.
1105 * i386-tbl.h: Likewise.
1107 2018-01-17 Jim Wilson <jimw@sifive.com>
1109 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1111 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1113 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1114 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1115 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1116 (cpu_flags): Add CpuIBT, CpuSHSTK.
1117 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1118 (i386_cpu_flags): Add cpuibt, cpushstk.
1119 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1120 * i386-init.h: Regenerate.
1121 * i386-tbl.h: Likewise.
1123 2018-01-16 Nick Clifton <nickc@redhat.com>
1125 * po/pt_BR.po: Updated Brazilian Portugese translation.
1126 * po/de.po: Updated German translation.
1128 2018-01-15 Jim Wilson <jimw@sifive.com>
1130 * riscv-opc.c (match_c_nop): New.
1131 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1133 2018-01-15 Nick Clifton <nickc@redhat.com>
1135 * po/uk.po: Updated Ukranian translation.
1137 2018-01-13 Nick Clifton <nickc@redhat.com>
1139 * po/opcodes.pot: Regenerated.
1141 2018-01-13 Nick Clifton <nickc@redhat.com>
1143 * configure: Regenerate.
1145 2018-01-13 Nick Clifton <nickc@redhat.com>
1147 2.30 branch created.
1149 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1151 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1152 * i386-tbl.h: Regenerate.
1154 2018-01-10 Jan Beulich <jbeulich@suse.com>
1156 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1157 * i386-tbl.h: Re-generate.
1159 2018-01-10 Jan Beulich <jbeulich@suse.com>
1161 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1162 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1163 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1164 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1165 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1166 Disp8MemShift of AVX512VL forms.
1167 * i386-tbl.h: Re-generate.
1169 2018-01-09 Jim Wilson <jimw@sifive.com>
1171 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1172 then the hi_addr value is zero.
1174 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1176 * arm-dis.c (arm_opcodes): Add csdb.
1177 (thumb32_opcodes): Add csdb.
1179 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1181 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1182 * aarch64-asm-2.c: Regenerate.
1183 * aarch64-dis-2.c: Regenerate.
1184 * aarch64-opc-2.c: Regenerate.
1186 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1189 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1190 Remove AVX512 vmovd with 64-bit operands.
1191 * i386-tbl.h: Regenerated.
1193 2018-01-05 Jim Wilson <jimw@sifive.com>
1195 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1198 2018-01-03 Alan Modra <amodra@gmail.com>
1200 Update year range in copyright notice of all files.
1202 2018-01-02 Jan Beulich <jbeulich@suse.com>
1204 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1205 and OPERAND_TYPE_REGZMM entries.
1207 For older changes see ChangeLog-2017
1209 Copyright (C) 2018 Free Software Foundation, Inc.
1211 Copying and distribution of this file, with or without modification,
1212 are permitted in any medium without royalty provided the copyright
1213 notice and this notice are preserved.
1219 version-control: never