1 2017-02-28 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (PCMPESTR_Fixup): New.
4 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
5 (prefix_table): Use PCMPESTR_Fixup.
6 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
8 (vex_w_table): Delete VPCMPESTR{I,M} entries.
9 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
10 Split 64-bit and non-64-bit variants.
11 * opcodes/i386-tbl.h: Re-generate.
13 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
15 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
16 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
17 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
18 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
19 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
20 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
21 (OP_SVE_V_HSD): New macros.
22 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
23 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
24 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
25 (aarch64_opcode_table): Add new SVE instructions.
26 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
27 for rotation operands. Add new SVE operands.
28 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
29 (ins_sve_quad_index): Likewise.
30 (ins_imm_rotate): Split into...
31 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
32 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
33 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
35 (aarch64_ins_sve_addr_ri_s4): New function.
36 (aarch64_ins_sve_quad_index): Likewise.
37 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
38 * aarch64-asm-2.c: Regenerate.
39 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
40 (ext_sve_quad_index): Likewise.
41 (ext_imm_rotate): Split into...
42 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
43 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
44 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
46 (aarch64_ext_sve_addr_ri_s4): New function.
47 (aarch64_ext_sve_quad_index): Likewise.
48 (aarch64_ext_sve_index): Allow quad indices.
49 (do_misc_decoding): Likewise.
50 * aarch64-dis-2.c: Regenerate.
51 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
53 (OPD_F_OD_MASK): Widen by one bit.
54 (OPD_F_NO_ZR): Bump accordingly.
55 (get_operand_field_width): New function.
56 * aarch64-opc.c (fields): Add new SVE fields.
57 (operand_general_constraint_met_p): Handle new SVE operands.
58 (aarch64_print_operand): Likewise.
59 * aarch64-opc-2.c: Regenerate.
61 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
63 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
64 (aarch64_feature_compnum): ...this.
65 (SIMD_V8_3): Replace with...
67 (CNUM_INSN): New macro.
68 (aarch64_opcode_table): Use it for the complex number instructions.
70 2017-02-24 Jan Beulich <jbeulich@suse.com>
72 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
74 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
76 Add support for associating SPARC ASIs with an architecture level.
77 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
78 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
79 decoding of SPARC ASIs.
81 2017-02-23 Jan Beulich <jbeulich@suse.com>
83 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
84 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
86 2017-02-21 Jan Beulich <jbeulich@suse.com>
88 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
89 1 (instead of to itself). Correct typo.
91 2017-02-14 Andrew Waterman <andrew@sifive.com>
93 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
96 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
98 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
99 (aarch64_sys_reg_supported_p): Handle them.
101 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
103 * arc-opc.c (UIMM6_20R): Define.
104 (SIMM12_20): Use above.
105 (SIMM12_20R): Define.
106 (SIMM3_5_S): Use above.
107 (UIMM7_A32_11R_S): Define.
108 (UIMM7_9_S): Use above.
109 (UIMM3_13R_S): Define.
110 (SIMM11_A32_7_S): Use above.
112 (UIMM10_A32_8_S): Use above.
113 (UIMM8_8R_S): Define.
115 (arc_relax_opcodes): Use all above defines.
117 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
119 * arc-regs.h: Distinguish some of the registers different on
120 ARC700 and HS38 cpus.
122 2017-02-14 Alan Modra <amodra@gmail.com>
125 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
126 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
128 2017-02-11 Stafford Horne <shorne@gmail.com>
129 Alan Modra <amodra@gmail.com>
131 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
132 Use insn_bytes_value and insn_int_value directly instead. Don't
133 free allocated memory until function exit.
135 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
137 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
139 2017-02-03 Nick Clifton <nickc@redhat.com>
142 * aarch64-opc.c (print_register_list): Ensure that the register
143 list index will fir into the tb buffer.
144 (print_register_offset_address): Likewise.
145 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
147 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
150 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
151 instructions when the previous fetch packet ends with a 32-bit
154 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
156 * pru-opc.c: Remove vague reference to a future GDB port.
158 2017-01-20 Nick Clifton <nickc@redhat.com>
160 * po/ga.po: Updated Irish translation.
162 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
164 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
166 2017-01-13 Yao Qi <yao.qi@linaro.org>
168 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
169 if FETCH_DATA returns 0.
170 (m68k_scan_mask): Likewise.
171 (print_insn_m68k): Update code to handle -1 return value.
173 2017-01-13 Yao Qi <yao.qi@linaro.org>
175 * m68k-dis.c (enum print_insn_arg_error): New.
176 (NEXTBYTE): Replace -3 with
177 PRINT_INSN_ARG_MEMORY_ERROR.
178 (NEXTULONG): Likewise.
179 (NEXTSINGLE): Likewise.
180 (NEXTDOUBLE): Likewise.
181 (NEXTDOUBLE): Likewise.
182 (NEXTPACKED): Likewise.
183 (FETCH_ARG): Likewise.
184 (FETCH_DATA): Update comments.
185 (print_insn_arg): Update comments. Replace magic numbers with
187 (match_insn_m68k): Likewise.
189 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
191 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
192 * i386-dis-evex.h (evex_table): Updated.
193 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
194 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
195 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
196 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
197 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
198 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
199 * i386-init.h: Regenerate.
202 2017-01-12 Yao Qi <yao.qi@linaro.org>
204 * msp430-dis.c (msp430_singleoperand): Return -1 if
205 msp430dis_opcode_signed returns false.
206 (msp430_doubleoperand): Likewise.
207 (msp430_branchinstr): Return -1 if
208 msp430dis_opcode_unsigned returns false.
209 (msp430x_calla_instr): Likewise.
210 (print_insn_msp430): Likewise.
212 2017-01-05 Nick Clifton <nickc@redhat.com>
215 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
216 could not be matched.
217 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
220 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
222 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
223 (aarch64_opcode_table): Use RCPC_INSN.
225 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
227 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
229 * riscv-opcodes/all-opcodes: Likewise.
231 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
233 * riscv-dis.c (print_insn_args): Add fall through comment.
235 2017-01-03 Nick Clifton <nickc@redhat.com>
237 * po/sr.po: New Serbian translation.
238 * configure.ac (ALL_LINGUAS): Add sr.
239 * configure: Regenerate.
241 2017-01-02 Alan Modra <amodra@gmail.com>
243 * epiphany-desc.h: Regenerate.
244 * epiphany-opc.h: Regenerate.
245 * fr30-desc.h: Regenerate.
246 * fr30-opc.h: Regenerate.
247 * frv-desc.h: Regenerate.
248 * frv-opc.h: Regenerate.
249 * ip2k-desc.h: Regenerate.
250 * ip2k-opc.h: Regenerate.
251 * iq2000-desc.h: Regenerate.
252 * iq2000-opc.h: Regenerate.
253 * lm32-desc.h: Regenerate.
254 * lm32-opc.h: Regenerate.
255 * m32c-desc.h: Regenerate.
256 * m32c-opc.h: Regenerate.
257 * m32r-desc.h: Regenerate.
258 * m32r-opc.h: Regenerate.
259 * mep-desc.h: Regenerate.
260 * mep-opc.h: Regenerate.
261 * mt-desc.h: Regenerate.
262 * mt-opc.h: Regenerate.
263 * or1k-desc.h: Regenerate.
264 * or1k-opc.h: Regenerate.
265 * xc16x-desc.h: Regenerate.
266 * xc16x-opc.h: Regenerate.
267 * xstormy16-desc.h: Regenerate.
268 * xstormy16-opc.h: Regenerate.
270 2017-01-02 Alan Modra <amodra@gmail.com>
272 Update year range in copyright notice of all files.
274 For older changes see ChangeLog-2016
276 Copyright (C) 2017 Free Software Foundation, Inc.
278 Copying and distribution of this file, with or without modification,
279 are permitted in any medium without royalty provided the copyright
280 notice and this notice are preserved.
286 version-control: never