1 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2 Michael Collison <michael.collison@arm.com>
4 * arm-dis.c (enum mve_instructions): Add new instructions.
5 (enum mve_unpredictable): Add new values.
6 (mve_opcodes): Add new instructions.
7 (vec_condnames): New array with vector conditions.
8 (mve_predicatenames): New array with predicate suffixes.
9 (mve_vec_sizename): New array with vector sizes.
10 (enum vpt_pred_state): New enum with vector predication states.
11 (struct vpt_block): New struct type for vpt blocks.
12 (vpt_block_state): Global struct to keep track of state.
13 (mve_extract_pred_mask): New helper function.
14 (num_instructions_vpt_block): Likewise.
15 (mark_outside_vpt_block): Likewise.
16 (mark_inside_vpt_block): Likewise.
17 (invert_next_predicate_state): Likewise.
18 (update_next_predicate_state): Likewise.
19 (update_vpt_block_state): Likewise.
20 (is_vpt_instruction): Likewise.
21 (is_mve_encoding_conflict): Add entries for new instructions.
22 (is_mve_unpredictable): Likewise.
23 (print_mve_unpredictable): Handle new cases.
24 (print_instruction_predicate): Likewise.
25 (print_mve_size): New function.
26 (print_vec_condition): New function.
27 (print_insn_mve): Handle vpt blocks and new print operands.
29 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
31 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
32 8, 14 and 15 for Armv8.1-M Mainline.
34 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
35 Michael Collison <michael.collison@arm.com>
37 * arm-dis.c (enum mve_instructions): New enum.
38 (enum mve_unpredictable): Likewise.
39 (enum mve_undefined): Likewise.
40 (struct mopcode32): New struct.
41 (is_mve_okay_in_it): New function.
42 (is_mve_architecture): Likewise.
43 (arm_decode_field): Likewise.
44 (arm_decode_field_multiple): Likewise.
45 (is_mve_encoding_conflict): Likewise.
46 (is_mve_undefined): Likewise.
47 (is_mve_unpredictable): Likewise.
48 (print_mve_undefined): Likewise.
49 (print_mve_unpredictable): Likewise.
50 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
51 (print_insn_mve): New function.
52 (print_insn_thumb32): Handle MVE architecture.
53 (select_arm_features): Force thumb for Armv8.1-m Mainline.
55 2019-05-10 Nick Clifton <nickc@redhat.com>
58 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
59 end of the table prematurely.
61 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
63 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
66 2019-05-11 Alan Modra <amodra@gmail.com>
68 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
69 when -Mraw is in effect.
71 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
73 * aarch64-dis-2.c: Regenerate.
74 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
75 (OP_SVE_BBB): New variant set.
76 (OP_SVE_DDDD): New variant set.
77 (OP_SVE_HHH): New variant set.
78 (OP_SVE_HHHU): New variant set.
79 (OP_SVE_SSS): New variant set.
80 (OP_SVE_SSSU): New variant set.
81 (OP_SVE_SHH): New variant set.
82 (OP_SVE_SBBU): New variant set.
83 (OP_SVE_DSS): New variant set.
84 (OP_SVE_DHHU): New variant set.
85 (OP_SVE_VMV_HSD_BHS): New variant set.
86 (OP_SVE_VVU_HSD_BHS): New variant set.
87 (OP_SVE_VVVU_SD_BH): New variant set.
88 (OP_SVE_VVVU_BHSD): New variant set.
89 (OP_SVE_VVV_QHD_DBS): New variant set.
90 (OP_SVE_VVV_HSD_BHS): New variant set.
91 (OP_SVE_VVV_HSD_BHS2): New variant set.
92 (OP_SVE_VVV_BHS_HSD): New variant set.
93 (OP_SVE_VV_BHS_HSD): New variant set.
94 (OP_SVE_VVV_SD): New variant set.
95 (OP_SVE_VVU_BHS_HSD): New variant set.
96 (OP_SVE_VZVV_SD): New variant set.
97 (OP_SVE_VZVV_BH): New variant set.
98 (OP_SVE_VZV_SD): New variant set.
99 (aarch64_opcode_table): Add sve2 instructions.
101 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
103 * aarch64-asm-2.c: Regenerated.
104 * aarch64-dis-2.c: Regenerated.
105 * aarch64-opc-2.c: Regenerated.
106 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
107 for SVE_SHLIMM_UNPRED_22.
108 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
109 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
112 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
114 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
115 sve_size_tsz_bhs iclass encode.
116 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
117 sve_size_tsz_bhs iclass decode.
119 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
121 * aarch64-asm-2.c: Regenerated.
122 * aarch64-dis-2.c: Regenerated.
123 * aarch64-opc-2.c: Regenerated.
124 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
125 for SVE_Zm4_11_INDEX.
126 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
127 (fields): Handle SVE_i2h field.
128 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
129 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
131 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
133 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
134 sve_shift_tsz_bhsd iclass encode.
135 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
136 sve_shift_tsz_bhsd iclass decode.
138 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
140 * aarch64-asm-2.c: Regenerated.
141 * aarch64-dis-2.c: Regenerated.
142 * aarch64-opc-2.c: Regenerated.
143 * aarch64-asm.c (aarch64_ins_sve_shrimm):
144 (aarch64_encode_variant_using_iclass): Handle
145 sve_shift_tsz_hsd iclass encode.
146 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
147 sve_shift_tsz_hsd iclass decode.
148 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
149 for SVE_SHRIMM_UNPRED_22.
150 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
151 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
154 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
156 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
157 sve_size_013 iclass encode.
158 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
159 sve_size_013 iclass decode.
161 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
163 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
164 sve_size_bh iclass encode.
165 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
166 sve_size_bh iclass decode.
168 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
170 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
171 sve_size_sd2 iclass encode.
172 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
173 sve_size_sd2 iclass decode.
174 * aarch64-opc.c (fields): Handle SVE_sz2 field.
175 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
177 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
179 * aarch64-asm-2.c: Regenerated.
180 * aarch64-dis-2.c: Regenerated.
181 * aarch64-opc-2.c: Regenerated.
182 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
184 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
185 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
187 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
189 * aarch64-asm-2.c: Regenerated.
190 * aarch64-dis-2.c: Regenerated.
191 * aarch64-opc-2.c: Regenerated.
192 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
193 for SVE_Zm3_11_INDEX.
194 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
195 (fields): Handle SVE_i3l and SVE_i3h2 fields.
196 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
198 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
200 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
202 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
203 sve_size_hsd2 iclass encode.
204 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
205 sve_size_hsd2 iclass decode.
206 * aarch64-opc.c (fields): Handle SVE_size field.
207 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
209 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
211 * aarch64-asm-2.c: Regenerated.
212 * aarch64-dis-2.c: Regenerated.
213 * aarch64-opc-2.c: Regenerated.
214 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
216 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
217 (fields): Handle SVE_rot3 field.
218 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
219 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
221 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
223 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
226 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
229 (aarch64_feature_sve2, aarch64_feature_sve2aes,
230 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
231 aarch64_feature_sve2bitperm): New feature sets.
232 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
233 for feature set addresses.
234 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
235 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
237 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
238 Faraz Shahbazker <fshahbazker@wavecomp.com>
240 * mips-dis.c (mips_calculate_combination_ases): Add ISA
241 argument and set ASE_EVA_R6 appropriately.
242 (set_default_mips_dis_options): Pass ISA to above.
243 (parse_mips_dis_option): Likewise.
244 * mips-opc.c (EVAR6): New macro.
245 (mips_builtin_opcodes): Add llwpe, scwpe.
247 2019-05-01 Sudakshina Das <sudi.das@arm.com>
249 * aarch64-asm-2.c: Regenerated.
250 * aarch64-dis-2.c: Regenerated.
251 * aarch64-opc-2.c: Regenerated.
252 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
253 AARCH64_OPND_TME_UIMM16.
254 (aarch64_print_operand): Likewise.
255 * aarch64-tbl.h (QL_IMM_NIL): New.
258 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
260 2019-04-29 John Darrington <john@darrington.wattle.id.au>
262 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
264 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
265 Faraz Shahbazker <fshahbazker@wavecomp.com>
267 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
269 2019-04-24 John Darrington <john@darrington.wattle.id.au>
271 * s12z-opc.h: Add extern "C" bracketing to help
272 users who wish to use this interface in c++ code.
274 2019-04-24 John Darrington <john@darrington.wattle.id.au>
276 * s12z-opc.c (bm_decode): Handle bit map operations with the
279 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
281 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
282 specifier. Add entries for VLDR and VSTR of system registers.
283 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
284 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
285 of %J and %K format specifier.
287 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
289 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
290 Add new entries for VSCCLRM instruction.
291 (print_insn_coprocessor): Handle new %C format control code.
293 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
295 * arm-dis.c (enum isa): New enum.
296 (struct sopcode32): New structure.
297 (coprocessor_opcodes): change type of entries to struct sopcode32 and
298 set isa field of all current entries to ANY.
299 (print_insn_coprocessor): Change type of insn to struct sopcode32.
300 Only match an entry if its isa field allows the current mode.
302 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
304 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
306 (print_insn_thumb32): Add logic to print %n CLRM register list.
308 2019-04-15 Sudakshina Das <sudi.das@arm.com>
310 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
313 2019-04-15 Sudakshina Das <sudi.das@arm.com>
315 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
316 (print_insn_thumb32): Edit the switch case for %Z.
318 2019-04-15 Sudakshina Das <sudi.das@arm.com>
320 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
322 2019-04-15 Sudakshina Das <sudi.das@arm.com>
324 * arm-dis.c (thumb32_opcodes): New instruction bfl.
326 2019-04-15 Sudakshina Das <sudi.das@arm.com>
328 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
330 2019-04-15 Sudakshina Das <sudi.das@arm.com>
332 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
333 Arm register with r13 and r15 unpredictable.
334 (thumb32_opcodes): New instructions for bfx and bflx.
336 2019-04-15 Sudakshina Das <sudi.das@arm.com>
338 * arm-dis.c (thumb32_opcodes): New instructions for bf.
340 2019-04-15 Sudakshina Das <sudi.das@arm.com>
342 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
344 2019-04-15 Sudakshina Das <sudi.das@arm.com>
346 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
348 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
350 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
352 2019-04-12 John Darrington <john@darrington.wattle.id.au>
354 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
355 "optr". ("operator" is a reserved word in c++).
357 2019-04-11 Sudakshina Das <sudi.das@arm.com>
359 * aarch64-opc.c (aarch64_print_operand): Add case for
361 (verify_constraints): Likewise.
362 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
363 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
364 to accept Rt|SP as first operand.
365 (AARCH64_OPERANDS): Add new Rt_SP.
366 * aarch64-asm-2.c: Regenerated.
367 * aarch64-dis-2.c: Regenerated.
368 * aarch64-opc-2.c: Regenerated.
370 2019-04-11 Sudakshina Das <sudi.das@arm.com>
372 * aarch64-asm-2.c: Regenerated.
373 * aarch64-dis-2.c: Likewise.
374 * aarch64-opc-2.c: Likewise.
375 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
377 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
379 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
381 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
384 * i386-init.h: Regenerated.
386 2019-04-07 Alan Modra <amodra@gmail.com>
388 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
389 op_separator to control printing of spaces, comma and parens
390 rather than need_comma, need_paren and spaces vars.
392 2019-04-07 Alan Modra <amodra@gmail.com>
395 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
396 (print_insn_neon, print_insn_arm): Likewise.
398 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
400 * i386-dis-evex.h (evex_table): Updated to support BF16
402 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
403 and EVEX_W_0F3872_P_3.
404 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
405 (cpu_flags): Add bitfield for CpuAVX512_BF16.
406 * i386-opc.h (enum): Add CpuAVX512_BF16.
407 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
408 * i386-opc.tbl: Add AVX512 BF16 instructions.
409 * i386-init.h: Regenerated.
410 * i386-tbl.h: Likewise.
412 2019-04-05 Alan Modra <amodra@gmail.com>
414 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
415 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
416 to favour printing of "-" branch hint when using the "y" bit.
417 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
419 2019-04-05 Alan Modra <amodra@gmail.com>
421 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
422 opcode until first operand is output.
424 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
427 * ppc-opc.c (valid_bo_pre_v2): Add comments.
428 (valid_bo_post_v2): Add support for 'at' branch hints.
429 (insert_bo): Only error on branch on ctr.
430 (get_bo_hint_mask): New function.
431 (insert_boe): Add new 'branch_taken' formal argument. Add support
432 for inserting 'at' branch hints.
433 (extract_boe): Add new 'branch_taken' formal argument. Add support
434 for extracting 'at' branch hints.
435 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
436 (BOE): Delete operand.
437 (BOM, BOP): New operands.
439 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
440 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
441 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
442 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
443 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
444 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
445 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
446 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
447 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
448 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
449 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
450 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
451 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
452 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
453 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
454 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
455 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
456 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
457 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
458 bttarl+>: New extended mnemonics.
460 2019-03-28 Alan Modra <amodra@gmail.com>
463 * ppc-opc.c (BTF): Define.
464 (powerpc_opcodes): Use for mtfsb*.
465 * ppc-dis.c (print_insn_powerpc): Print fields with both
466 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
468 2019-03-25 Tamar Christina <tamar.christina@arm.com>
470 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
471 (mapping_symbol_for_insn): Implement new algorithm.
472 (print_insn): Remove duplicate code.
474 2019-03-25 Tamar Christina <tamar.christina@arm.com>
476 * aarch64-dis.c (print_insn_aarch64):
479 2019-03-25 Tamar Christina <tamar.christina@arm.com>
481 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
484 2019-03-25 Tamar Christina <tamar.christina@arm.com>
486 * aarch64-dis.c (last_stop_offset): New.
487 (print_insn_aarch64): Use stop_offset.
489 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
492 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
494 * i386-init.h: Regenerated.
496 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
499 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
500 vmovdqu16, vmovdqu32 and vmovdqu64.
501 * i386-tbl.h: Regenerated.
503 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
505 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
506 from vstrszb, vstrszh, and vstrszf.
508 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
510 * s390-opc.txt: Add instruction descriptions.
512 2019-02-08 Jim Wilson <jimw@sifive.com>
514 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
517 2019-02-07 Tamar Christina <tamar.christina@arm.com>
519 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
521 2019-02-07 Tamar Christina <tamar.christina@arm.com>
524 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
525 * aarch64-opc.c (verify_elem_sd): New.
526 (fields): Add FLD_sz entr.
527 * aarch64-tbl.h (_SIMD_INSN): New.
528 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
529 fmulx scalar and vector by element isns.
531 2019-02-07 Nick Clifton <nickc@redhat.com>
533 * po/sv.po: Updated Swedish translation.
535 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
537 * s390-mkopc.c (main): Accept arch13 as cpu string.
538 * s390-opc.c: Add new instruction formats and instruction opcode
540 * s390-opc.txt: Add new arch13 instructions.
542 2019-01-25 Sudakshina Das <sudi.das@arm.com>
544 * aarch64-tbl.h (QL_LDST_AT): Update macro.
545 (aarch64_opcode): Change encoding for stg, stzg
547 * aarch64-asm-2.c: Regenerated.
548 * aarch64-dis-2.c: Regenerated.
549 * aarch64-opc-2.c: Regenerated.
551 2019-01-25 Sudakshina Das <sudi.das@arm.com>
553 * aarch64-asm-2.c: Regenerated.
554 * aarch64-dis-2.c: Likewise.
555 * aarch64-opc-2.c: Likewise.
556 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
558 2019-01-25 Sudakshina Das <sudi.das@arm.com>
559 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
561 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
562 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
563 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
564 * aarch64-dis.h (ext_addr_simple_2): Likewise.
565 * aarch64-opc.c (operand_general_constraint_met_p): Remove
566 case for ldstgv_indexed.
567 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
568 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
569 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
570 * aarch64-asm-2.c: Regenerated.
571 * aarch64-dis-2.c: Regenerated.
572 * aarch64-opc-2.c: Regenerated.
574 2019-01-23 Nick Clifton <nickc@redhat.com>
576 * po/pt_BR.po: Updated Brazilian Portuguese translation.
578 2019-01-21 Nick Clifton <nickc@redhat.com>
580 * po/de.po: Updated German translation.
581 * po/uk.po: Updated Ukranian translation.
583 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
584 * mips-dis.c (mips_arch_choices): Fix typo in
585 gs464, gs464e and gs264e descriptors.
587 2019-01-19 Nick Clifton <nickc@redhat.com>
589 * configure: Regenerate.
590 * po/opcodes.pot: Regenerate.
592 2018-06-24 Nick Clifton <nickc@redhat.com>
596 2019-01-09 John Darrington <john@darrington.wattle.id.au>
598 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
600 -dis.c (opr_emit_disassembly): Do not omit an index if it is
603 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
605 * configure: Regenerate.
607 2019-01-07 Alan Modra <amodra@gmail.com>
609 * configure: Regenerate.
610 * po/POTFILES.in: Regenerate.
612 2019-01-03 John Darrington <john@darrington.wattle.id.au>
614 * s12z-opc.c: New file.
615 * s12z-opc.h: New file.
616 * s12z-dis.c: Removed all code not directly related to display
617 of instructions. Used the interface provided by the new files
619 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
620 * Makefile.in: Regenerate.
621 * configure.ac (bfd_s12z_arch): Correct the dependencies.
622 * configure: Regenerate.
624 2019-01-01 Alan Modra <amodra@gmail.com>
626 Update year range in copyright notice of all files.
628 For older changes see ChangeLog-2018
630 Copyright (C) 2019 Free Software Foundation, Inc.
632 Copying and distribution of this file, with or without modification,
633 are permitted in any medium without royalty provided the copyright
634 notice and this notice are preserved.
640 version-control: never