1 2013-05-02 Nick Clifton <nickc@redhat.com>
3 * msp430-dis.c: Add support for MSP430X instructions.
5 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
7 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
10 2013-04-17 Wei-chen Wang <cole945@gmail.com>
13 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
15 (hash_insns_list): Likewise.
17 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
19 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
22 2013-04-08 Jan Beulich <jbeulich@suse.com>
24 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
25 * i386-tbl.h: Re-generate.
27 2013-04-06 David S. Miller <davem@davemloft.net>
29 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
30 of an opcode, prefer the one with F_PREFERRED set.
31 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
32 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
33 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
34 mark existing mnenomics as aliases. Add "cc" suffix to edge
35 instructions generating condition codes, mark existing mnenomics
36 as aliases. Add "fp" prefix to VIS compare instructions, mark
37 existing mnenomics as aliases.
39 2013-04-03 Nick Clifton <nickc@redhat.com>
41 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
42 destination address by subtracting the operand from the current
44 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
45 a positive value in the insn.
46 (extract_u16_loop): Do not negate the returned value.
47 (D16_LOOP): Add V850_INVERSE_PCREL flag.
49 (ceilf.sw): Remove duplicate entry.
56 (maddf.s): Restrict to E3V5 architectures.
61 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
63 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
65 (print_insn): Pass sizeflag to get_sib.
67 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
70 * tic6x-dis.c: Add support for displaying 16-bit insns.
72 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
75 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
76 individual msb and lsb halves in src1 & src2 fields. Discard the
77 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
78 follow what Ti SDK does in that case as any value in the src1
79 field yields the same output with SDK disassembler.
81 2013-03-12 Michael Eager <eager@eagercon.com>
83 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
85 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
87 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
89 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
91 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
93 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
95 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
97 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
99 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
100 (thumb32_opcodes): Likewise.
101 (print_insn_thumb32): Handle 'S' control char.
103 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
105 * lm32-desc.c: Regenerate.
107 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
109 * i386-reg.tbl (riz): Add RegRex64.
110 * i386-tbl.h: Regenerated.
112 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
114 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
115 (aarch64_feature_crc): New static.
117 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
118 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
119 * aarch64-asm-2.c: Re-generate.
120 * aarch64-dis-2.c: Ditto.
121 * aarch64-opc-2.c: Ditto.
123 2013-02-27 Alan Modra <amodra@gmail.com>
125 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
126 * rl78-decode.c: Regenerate.
128 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
130 * rl78-decode.opc: Fix encoding of DIVWU insn.
131 * rl78-decode.c: Regenerate.
133 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
138 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
139 (cpu_flags): Add CpuSMAP.
141 * i386-opc.h (CpuSMAP): New.
142 (i386_cpu_flags): Add cpusmap.
144 * i386-opc.tbl: Add clac and stac.
146 * i386-init.h: Regenerated.
147 * i386-tbl.h: Likewise.
149 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
151 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
152 which also makes the disassembler output be in little
153 endian like it should be.
155 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
157 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
159 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
161 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
163 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
164 section disassembled.
166 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
168 * arm-dis.c: Update strht pattern.
170 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
172 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
173 single-float. Disable ll, lld, sc and scd for EE. Disable the
174 trunc.w.s macro for EE.
176 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
177 Andrew Jenner <andrew@codesourcery.com>
179 Based on patches from Altera Corporation.
181 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
183 * Makefile.in: Regenerated.
184 * configure.in: Add case for bfd_nios2_arch.
185 * configure: Regenerated.
186 * disassemble.c (ARCH_nios2): Define.
187 (disassembler): Add case for bfd_arch_nios2.
188 * nios2-dis.c: New file.
189 * nios2-opc.c: New file.
191 2013-02-04 Alan Modra <amodra@gmail.com>
193 * po/POTFILES.in: Regenerate.
194 * rl78-decode.c: Regenerate.
195 * rx-decode.c: Regenerate.
197 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
199 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
200 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
201 * aarch64-asm.c (convert_xtl_to_shll): New function.
202 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
203 calling convert_xtl_to_shll.
204 * aarch64-dis.c (convert_shll_to_xtl): New function.
205 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
206 calling convert_shll_to_xtl.
207 * aarch64-gen.c: Update copyright year.
208 * aarch64-asm-2.c: Re-generate.
209 * aarch64-dis-2.c: Re-generate.
210 * aarch64-opc-2.c: Re-generate.
212 2013-01-24 Nick Clifton <nickc@redhat.com>
214 * v850-dis.c: Add support for e3v5 architecture.
215 * v850-opc.c: Likewise.
217 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
219 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
220 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
221 * aarch64-opc.c (operand_general_constraint_met_p): For
222 AARCH64_MOD_LSL, move the range check on the shift amount before the
223 alignment check; change to call set_sft_amount_out_of_range_error
224 instead of set_imm_out_of_range_error.
225 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
226 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
227 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
230 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
232 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
234 * i386-init.h: Regenerated.
235 * i386-tbl.h: Likewise.
237 2013-01-15 Nick Clifton <nickc@redhat.com>
239 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
241 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
243 2013-01-14 Will Newton <will.newton@imgtec.com>
245 * metag-dis.c (REG_WIDTH): Increase to 64.
247 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
249 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
250 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
251 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
253 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
254 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
255 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
256 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
258 2013-01-10 Will Newton <will.newton@imgtec.com>
260 * Makefile.am: Add Meta.
261 * configure.in: Add Meta.
262 * disassemble.c: Add Meta support.
263 * metag-dis.c: New file.
264 * Makefile.in: Regenerate.
265 * configure: Regenerate.
267 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
269 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
270 (match_opcode): Rename to cr16_match_opcode.
272 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
274 * mips-dis.c: Add names for CP0 registers of r5900.
275 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
276 instructions sq and lq.
277 Add support for MIPS r5900 CPU.
278 Add support for 128 bit MMI (Multimedia Instructions).
279 Add support for EE instructions (Emotion Engine).
280 Disable unsupported floating point instructions (64 bit and
281 undefined compare operations).
282 Enable instructions of MIPS ISA IV which are supported by r5900.
283 Disable 64 bit co processor instructions.
284 Disable 64 bit multiplication and division instructions.
285 Disable instructions for co-processor 2 and 3, because these are
286 not supported (preparation for later VU0 support (Vector Unit)).
287 Disable cvt.w.s because this behaves like trunc.w.s and the
288 correct execution can't be ensured on r5900.
289 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
290 will confuse less developers and compilers.
292 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
294 * aarch64-opc.c (aarch64_print_operand): Change to print
295 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
297 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
298 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
301 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
303 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
304 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
306 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
308 * i386-gen.c (process_copyright): Update copyright year to 2013.
310 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
312 * cr16-dis.c (match_opcode,make_instruction): Remove static
314 (dwordU,wordU): Moved typedefs to opcode/cr16.h
315 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
317 For older changes see ChangeLog-2012
319 Copyright (C) 2013 Free Software Foundation, Inc.
321 Copying and distribution of this file, with or without modification,
322 are permitted in any medium without royalty provided the copyright
323 notice and this notice are preserved.
329 version-control: never