1 2012-11-21 Edgar E. Iglesias <edgar.iglesias@gmail.com>
3 * microblaze-opcm.h: Add REG_SLR_MASK, REG_SHR_MASK, REG_SHR and REG_SLR
4 * microblaze-dis.c (get_field_special): Handle REG_SLR_MASK and REG_SHR_MASK
6 2012-11-20 Kirill Yukhin <kirill.yukhin@intel.com>
7 H.J. Lu <hongjiu.lu@intel.com>
10 * i386-opc.tbl: Fix opcode for 64-bit jecxz.
11 * i386-tbl.h: Regenerated.
13 2012-11-20 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
15 * s390-opc.txt: Fix srstu and strag opcodes.
17 2012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
19 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
20 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
21 and increase MAX_OPCODES.
22 (op_code_struct): add mbar and sleep
23 * microblaze-opcm.h (microblaze_instr): add mbar
24 Define IMM_MBAR and IMM5_MBAR_MASK
25 * microblaze-dis.c: Add get_field_imm5_mbar
26 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
28 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
30 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
31 * microblaze-opcm.h (microblaze_instr): add clz
33 2012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
35 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
36 lhur, lwr, sbr, shr, swr
37 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
40 2012-11-09 Nick Clifton <nickc@redhat.com>
42 * configure.in: Add bfd_v850_rh850_arch.
43 * configure: Regenerate.
44 * disassemble.c (disassembler): Likewise.
46 2012-11-09 H.J. Lu <hongjiu.lu@intel.com>
48 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
49 * ia64-gen.c (fetch_insn_class): Likewise.
51 2012-11-08 Alan Modra <amodra@gmail.com>
53 * po/POTFILES.in: Regenerate.
55 2012-11-05 Alan Modra <amodra@gmail.com>
57 * configure.in: Apply 2012-09-10 change to config.in here.
59 2012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
61 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
62 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
64 * s390-opc.txt: Add new instructions. New instruction type for lptea.
66 2012-10-26 Christian Groessler <chris@groessler.org>
68 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
69 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
70 non-existing opcode trtrb.
71 * z8k-opc.h: Regenerate.
73 2012-10-26 Alan Modra <amodra@gmail.com>
75 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
77 2012-10-24 Roland McGrath <mcgrathr@google.com>
79 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
82 2012-10-22 Peter Bergner <bergner@vnet.ibm.com>
84 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
86 2012-10-18 Tom Tromey <tromey@redhat.com>
88 * tic54x-dis.c (print_instruction): Don't use K&R style.
89 (print_parallel_instruction, sprint_dual_address)
90 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
91 (sprint_cc2, sprint_condition): Likewise.
93 2012-10-18 Kai Tietz <ktietz@redhat.com>
95 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
97 (do_special_encoding): Likewise.
98 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
99 variables with default.
100 * arc-dis.c (write_comments_): Don't use strncat due
101 size of state->commentBuffer pointer isn't predictable.
103 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
105 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
106 rmr_el3; remove daifset and daifclr.
108 2012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
110 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
111 the alignment of addr.offset.imm instead of that of shifter.amount for
112 operand type AARCH64_OPND_ADDR_UIMM12.
114 2012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
116 * arm-dis.c: Use preferred form of vrint instruction variants
119 2012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
121 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
122 * i386-init.h: Regenerated.
124 2012-10-05 Peter Bergner <bergner@vnet.ibm.com>
126 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
127 * ppc-opc.c (VBA): New define.
128 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
129 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
131 2012-10-04 Nick Clifton <nickc@redhat.com>
133 * v850-dis.c (disassemble): Place square parentheses around second
134 register operand of clr1, not1, set1 and tst1 instructions.
136 2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
138 * s390-mkopc.c: Support new option zEC12.
139 * s390-opc.c: Add new instruction formats.
140 * s390-opc.txt: Add new instructions for zEC12.
142 2012-09-27 Anthony Green <green@moxielogic.com>
144 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
145 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
147 2012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
149 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
150 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
151 and CPU_BTVER2_FLAGS.
152 * i386-init.h: Regenerated.
154 2012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
156 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
157 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
158 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
159 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
160 (cpu_flags): Add CpuCX16.
161 * i386-opc.h (CpuCX16): New.
162 (i386_cpu_flags): Add cpucx16.
163 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
164 * i386-tbl.h: Regenerate.
165 * i386-init.h: Likewise.
167 2012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
169 * arm-dis.c: Changed ldra and strl-form mnemonics
172 2012-09-18 Chao-ying Fu <fu@mips.com>
174 * micromips-opc.c (micromips_opcodes): Correct the encoding of
175 the "swxc1" instruction.
177 2012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
179 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
180 the parameter 'inst'.
181 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
182 (convert_mov_to_movewide): Change to assert (0) when
183 aarch64_wide_constant_p returns FALSE.
185 2012-09-14 David Edelsohn <dje.gcc@gmail.com>
187 * configure: Regenerate.
189 2012-09-14 Anthony Green <green@moxielogic.com>
191 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
192 the address after the branch instruction.
194 2012-09-13 Anthony Green <green@moxielogic.com>
196 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
198 2012-09-10 Matthias Klose <doko@ubuntu.com>
200 * config.in: Disable sanity check for kfreebsd.
202 2012-09-10 H.J. Lu <hongjiu.lu@intel.com>
204 * configure: Regenerated.
206 2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
208 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
209 * ia64-gen.c: Promote completer index type to longlong.
210 (irf_operand): Add new register recognition.
211 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
212 (lookup_specifier): Add new resource recognition.
213 (insert_bit_table_ent): Relax abort condition according to the
214 changed completer index type.
215 (print_dis_table): Fix printf format for completer index.
216 * ia64-ic.tbl: Add a new instruction class.
217 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
218 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
219 * ia64-opc.h: Define short names for new operand types.
220 * ia64-raw.tbl: Add new RAW resource for DAHR register.
221 * ia64-waw.tbl: Add new WAW resource for DAHR register.
222 * ia64-asmtab.c: Regenerate.
224 2012-08-29 Peter Bergner <bergner@vnet.ibm.com>
226 * ppc-opc.c (VXASHB_MASK): New define.
227 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
229 2012-08-28 Peter Bergner <bergner@vnet.ibm.com>
231 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
232 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
233 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
234 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
235 vupklsh>: Use VXVA_MASK.
236 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
237 <mfvscr>: Use VXVAVB_MASK.
238 <mtvscr>: Use VXVDVA_MASK.
239 <vspltb>: Use VXUIMM4_MASK.
240 <vsplth>: Use VXUIMM3_MASK.
241 <vspltw>: Use VXUIMM2_MASK.
243 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
245 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
247 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
249 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
251 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
253 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
255 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
257 * arm-dis.c (neon_opcodes): Add support for AES instructions.
259 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
261 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
264 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
266 * arm-dis.c (coprocessor_opcodes): Add VRINT.
267 (neon_opcodes): Likewise.
269 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
271 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
273 (neon_opcodes): Likewise.
275 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
277 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
278 (neon_opcodes): Likewise.
280 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
282 * arm-dis.c (coprocessor_opcodes): Add VSEL.
283 (print_insn_coprocessor): Add new %<>c bitfield format
286 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
288 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
289 (thumb32_opcodes): Likewise.
290 (print_arm_insn): Add support for %<>T formatter.
292 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
294 * arm-dis.c (arm_opcodes): Add HLT.
295 (thumb_opcodes): Likewise.
297 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
299 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
301 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
303 * arm-dis.c (arm_opcodes): Add SEVL.
304 (thumb_opcodes): Likewise.
305 (thumb32_opcodes): Likewise.
307 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
309 * arm-dis.c (data_barrier_option): New function.
310 (print_insn_arm): Use data_barrier_option.
311 (print_insn_thumb32): Use data_barrier_option.
313 2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
315 * arm-dis.c (COND_UNCOND): New constant.
316 (print_insn_coprocessor): Add support for %u format specifier.
317 (print_insn_neon): Likewise.
319 2012-08-21 David S. Miller <davem@davemloft.net>
321 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
324 2012-08-20 Edmar Wienskoski <edmar@freescale.com>
326 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
327 vabsduh, vabsduw, mviwsplt.
329 2012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
331 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
334 * i386-opc.h: Update CpuPRFCHW comment.
336 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
337 * i386-init.h: Regenerated.
338 * i386-tbl.h: Likewise.
340 2012-08-17 Nick Clifton <nickc@redhat.com>
342 * po/uk.po: New Ukranian translation.
343 * configure.in (ALL_LINGUAS): Add uk.
344 * configure: Regenerate.
346 2012-08-16 Peter Bergner <bergner@vnet.ibm.com>
348 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
349 RBX for the third operand.
350 <"lswi">: Use RAX for second and NBI for the third operand.
352 2012-08-15 DJ Delorie <dj@redhat.com>
354 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
355 operands, so that data addresses can be corrected when not
357 * rl78-decode.c: Regenerate.
358 * rl78-dis.c (print_insn_rl78): Make order of modifiers
359 irrelevent. When the 'e' specifier is used on an operand and no
360 ES prefix is provided, adjust address to make it absolute.
362 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
364 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
366 2012-08-15 Peter Bergner <bergner@vnet.ibm.com>
368 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
370 2012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
372 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
373 macros, use local variables for info struct member accesses,
374 update the type of the variable used to hold the instruction
376 (print_insn_mips, print_mips16_insn_arg): Likewise.
377 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
378 local variables for info struct member accesses.
379 (print_insn_micromips): Add GET_OP_S local macro.
380 (_print_insn_mips): Update the type of the variable used to hold
381 the instruction word.
383 2012-08-13 Ian Bolton <ian.bolton@arm.com>
384 Laurent Desnogues <laurent.desnogues@arm.com>
385 Jim MacArthur <jim.macarthur@arm.com>
386 Marcus Shawcroft <marcus.shawcroft@arm.com>
387 Nigel Stephens <nigel.stephens@arm.com>
388 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
389 Richard Earnshaw <rearnsha@arm.com>
390 Sofiane Naci <sofiane.naci@arm.com>
391 Tejas Belagod <tejas.belagod@arm.com>
392 Yufeng Zhang <yufeng.zhang@arm.com>
394 * Makefile.am: Add AArch64.
395 * Makefile.in: Regenerate.
396 * aarch64-asm.c: New file.
397 * aarch64-asm.h: New file.
398 * aarch64-dis.c: New file.
399 * aarch64-dis.h: New file.
400 * aarch64-gen.c: New file.
401 * aarch64-opc.c: New file.
402 * aarch64-opc.h: New file.
403 * aarch64-tbl.h: New file.
404 * configure.in: Add AArch64.
405 * configure: Regenerate.
406 * disassemble.c: Add AArch64.
407 * aarch64-asm-2.c: New file (automatically generated).
408 * aarch64-dis-2.c: New file (automatically generated).
409 * aarch64-opc-2.c: New file (automatically generated).
410 * po/POTFILES.in: Regenerate.
412 2012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
414 * micromips-opc.c (micromips_opcodes): Update comment.
415 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
416 instructions for IOCT as appropriate.
417 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
419 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
420 the result of a check for the -Wno-missing-field-initializers
422 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
423 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
425 (mips16-opc.lo): Likewise.
426 (micromips-opc.lo): Likewise.
427 * aclocal.m4: Regenerate.
428 * configure: Regenerate.
429 * Makefile.in: Regenerate.
431 2012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
434 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
435 * i386-init.h: Regenerated.
437 2012-08-09 Nick Clifton <nickc@redhat.com>
439 * po/vi.po: Updated Vietnamese translation.
441 2012-08-07 Roland McGrath <mcgrathr@google.com>
443 * i386-dis.c (reg_table): Fill out REG_0F0D table with
444 AMD-reserved cases as "prefetch".
445 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
446 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
447 (reg_table): Use those under REG_0F18.
448 (mod_table): Add those cases as "nop/reserved".
450 2012-08-07 Jan Beulich <jbeulich@suse.com>
452 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
454 2012-08-06 Roland McGrath <mcgrathr@google.com>
456 * i386-dis.c (print_insn): Print spaces between multiple excess
457 prefixes. Return actual number of excess prefixes consumed,
460 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
462 2012-08-06 Roland McGrath <mcgrathr@google.com>
463 Victor Khimenko <khim@google.com>
464 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
467 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
468 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
469 (OP_E_register): Likewise.
470 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
472 2012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
474 * configure.in: Formatting.
475 * configure: Regenerate.
477 2012-08-01 Alan Modra <amodra@gmail.com>
479 * h8300-dis.c: Fix printf arg warnings.
480 * i960-dis.c: Likewise.
481 * mips-dis.c: Likewise.
482 * pdp11-dis.c: Likewise.
483 * sh-dis.c: Likewise.
484 * v850-dis.c: Likewise.
485 * configure.in: Formatting.
486 * configure: Regenerate.
487 * rl78-decode.c: Regenerate.
488 * po/POTFILES.in: Regenerate.
490 2012-07-31 Chao-Ying Fu <fu@mips.com>
491 Catherine Moore <clm@codesourcery.com>
492 Maciej W. Rozycki <macro@codesourcery.com>
494 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
495 (DSP_VOLA): Likewise.
496 (D32, D33): Likewise.
497 (micromips_opcodes): Add DSP ASE instructions.
498 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
499 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
501 2012-07-31 Jan Beulich <jbeulich@suse.com>
503 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
504 instruction group. Mark as requiring AVX2.
505 * i386-tbl.h: Re-generate.
507 2012-07-30 Nick Clifton <nickc@redhat.com>
509 * po/opcodes.pot: Updated template.
510 * po/es.po: Updated Spanish translation.
511 * po/fi.po: Updated Finnish translation.
513 2012-07-27 Mike Frysinger <vapier@gentoo.org>
515 * configure.in (BFD_VERSION): Run bfd/configure --version and
516 parse the output of that.
517 * configure: Regenerate.
519 2012-07-25 James Lemke <jwlemke@codesourcery.com>
521 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
523 2012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
524 Dr David Alan Gilbert <dave@treblig.org>
527 * arm-dis.c: Add necessary casts for printing integer values.
528 Use %s when printing string values.
529 * hppa-dis.c: Likewise.
530 * m68k-dis.c: Likewise.
531 * microblaze-dis.c: Likewise.
532 * mips-dis.c: Likewise.
533 * sparc-dis.c: Likewise.
535 2012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
538 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
539 (VEX_LEN_0FXOP_08_CD): Likewise.
540 (VEX_LEN_0FXOP_08_CE): Likewise.
541 (VEX_LEN_0FXOP_08_CF): Likewise.
542 (VEX_LEN_0FXOP_08_EC): Likewise.
543 (VEX_LEN_0FXOP_08_ED): Likewise.
544 (VEX_LEN_0FXOP_08_EE): Likewise.
545 (VEX_LEN_0FXOP_08_EF): Likewise.
546 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
547 vpcomub, vpcomuw, vpcomud, vpcomuq.
548 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
549 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
550 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
553 2012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
555 * i386-dis.c (PREFIX_0F38F6): New.
556 (prefix_table): Add adcx, adox instructions.
557 (three_byte_table): Use PREFIX_0F38F6.
558 (mod_table): Add rdseed instruction.
559 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
560 (cpu_flags): Likewise.
561 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
562 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
563 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
565 * i386-tbl.h: Regenerate.
566 * i386-init.h: Likewise.
568 2012-07-05 Thomas Schwinge <thomas@codesourcery.com>
570 * mips-dis.c: Remove gratuitous newline.
572 2012-07-05 Sean Keys <skeys@ipdatasys.com>
574 * xgate-dis.c: Removed an IF statement that will
575 always be false due to overlapping operand masks.
576 * xgate-opc.c: Corrected 'com' opcode entry and
579 2012-07-02 Roland McGrath <mcgrathr@google.com>
581 * i386-opc.tbl: Add RepPrefixOk to nop.
582 * i386-tbl.h: Regenerate.
584 2012-06-28 Nick Clifton <nickc@redhat.com>
586 * po/vi.po: Updated Vietnamese translation.
588 2012-06-22 Roland McGrath <mcgrathr@google.com>
590 * i386-opc.tbl: Add RepPrefixOk to ret.
591 * i386-tbl.h: Regenerate.
593 * i386-opc.h (RepPrefixOk): New enum constant.
594 (i386_opcode_modifier): New bitfield 'repprefixok'.
595 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
596 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
597 instructions that have IsString.
598 * i386-tbl.h: Regenerate.
600 2012-06-11 Andreas Schwab <schwab@linux-m68k.org>
602 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
603 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
604 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
605 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
606 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
607 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
608 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
609 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
610 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
612 2012-05-19 Alan Modra <amodra@gmail.com>
614 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
615 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
617 2012-05-18 Alan Modra <amodra@gmail.com>
619 * ia64-opc.c: Remove #include "ansidecl.h".
620 * z8kgen.c: Include sysdep.h first.
622 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
623 * bfin-dis.c: Likewise.
624 * i860-dis.c: Likewise.
625 * ia64-dis.c: Likewise.
626 * ia64-gen.c: Likewise.
627 * m68hc11-dis.c: Likewise.
628 * mmix-dis.c: Likewise.
629 * msp430-dis.c: Likewise.
630 * or32-dis.c: Likewise.
631 * rl78-dis.c: Likewise.
632 * rx-dis.c: Likewise.
633 * tic4x-dis.c: Likewise.
634 * tilegx-opc.c: Likewise.
635 * tilepro-opc.c: Likewise.
636 * rx-decode.c: Regenerate.
638 2012-05-17 James Lemke <jwlemke@codesourcery.com>
640 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
642 2012-05-17 James Lemke <jwlemke@codesourcery.com>
644 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
646 2012-05-17 Daniel Richard G. <skunk@iskunk.org>
647 Nick Clifton <nickc@redhat.com>
650 * configure.in: Add check that sysdep.h has been included before
651 any system header files.
652 * configure: Regenerate.
653 * config.in: Regenerate.
654 * sysdep.h: Generate an error if included before config.h.
655 * alpha-opc.c: Include sysdep.h before any other header file.
656 * alpha-dis.c: Likewise.
657 * avr-dis.c: Likewise.
658 * cgen-opc.c: Likewise.
659 * cr16-dis.c: Likewise.
660 * cris-dis.c: Likewise.
661 * crx-dis.c: Likewise.
662 * d10v-dis.c: Likewise.
663 * d10v-opc.c: Likewise.
664 * d30v-dis.c: Likewise.
665 * d30v-opc.c: Likewise.
666 * h8500-dis.c: Likewise.
667 * i370-dis.c: Likewise.
668 * i370-opc.c: Likewise.
669 * m10200-dis.c: Likewise.
670 * m10300-dis.c: Likewise.
671 * micromips-opc.c: Likewise.
672 * mips-opc.c: Likewise.
673 * mips61-opc.c: Likewise.
674 * moxie-dis.c: Likewise.
675 * or32-opc.c: Likewise.
676 * pj-dis.c: Likewise.
677 * ppc-dis.c: Likewise.
678 * ppc-opc.c: Likewise.
679 * s390-dis.c: Likewise.
680 * sh-dis.c: Likewise.
681 * sh64-dis.c: Likewise.
682 * sparc-dis.c: Likewise.
683 * sparc-opc.c: Likewise.
684 * spu-dis.c: Likewise.
685 * tic30-dis.c: Likewise.
686 * tic54x-dis.c: Likewise.
687 * tic80-dis.c: Likewise.
688 * tic80-opc.c: Likewise.
689 * tilegx-dis.c: Likewise.
690 * tilepro-dis.c: Likewise.
691 * v850-dis.c: Likewise.
692 * v850-opc.c: Likewise.
693 * vax-dis.c: Likewise.
694 * w65-dis.c: Likewise.
695 * xgate-dis.c: Likewise.
696 * xtensa-dis.c: Likewise.
697 * rl78-decode.opc: Likewise.
698 * rl78-decode.c: Regenerate.
699 * rx-decode.opc: Likewise.
700 * rx-decode.c: Regenerate.
702 2012-05-17 Alan Modra <amodra@gmail.com>
704 * ppc_dis.c: Don't include elf/ppc.h.
706 2012-05-16 Meador Inge <meadori@codesourcery.com>
708 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
711 2012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
712 Stephane Carrez <stcarrez@nerim.fr>
714 * configure.in: Add S12X and XGATE co-processor support to m68hc11
716 * disassemble.c: Likewise.
717 * configure: Regenerate.
718 * m68hc11-dis.c: Make objdump output more consistent, use hex
719 instead of decimal and use 0x prefix for hex.
720 * m68hc11-opc.c: Add S12X and XGATE opcodes.
722 2012-05-14 James Lemke <jwlemke@codesourcery.com>
724 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
725 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
726 (vle_opcd_indices): New array.
727 (lookup_vle): New function.
728 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
729 (print_insn_powerpc): Likewise.
730 * ppc-opc.c: Likewise.
732 2012-05-14 Catherine Moore <clm@codesourcery.com>
733 Maciej W. Rozycki <macro@codesourcery.com>
734 Rhonda Wittels <rhonda@codesourcery.com>
735 Nathan Froyd <froydnj@codesourcery.com>
737 * ppc-opc.c (insert_arx, extract_arx): New functions.
738 (insert_ary, extract_ary): New functions.
739 (insert_li20, extract_li20): New functions.
740 (insert_rx, extract_rx): New functions.
741 (insert_ry, extract_ry): New functions.
742 (insert_sci8, extract_sci8): New functions.
743 (insert_sci8n, extract_sci8n): New functions.
744 (insert_sd4h, extract_sd4h): New functions.
745 (insert_sd4w, extract_sd4w): New functions.
746 (insert_vlesi, extract_vlesi): New functions.
747 (insert_vlensi, extract_vlensi): New functions.
748 (insert_vleui, extract_vleui): New functions.
749 (insert_vleil, extract_vleil): New functions.
750 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
751 (BI16, BI32, BO32, B8): New.
752 (B15, B24, CRD32, CRS): New.
753 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
754 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
755 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
756 (SH6_MASK): Use PPC_OPSHIFT_INV.
757 (SI8, UI5, OIMM5, UI7, BO16): New.
758 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
759 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
761 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
762 (OPVUP, OPVUP_MASK OPVUP): New
763 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
764 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
765 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
766 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
767 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
768 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
769 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
770 (SE_IM5, SE_IM5_MASK): New.
771 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
772 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
773 (BO32DNZ, BO32DZ): New.
774 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
776 (powerpc_opcodes): Add new VLE instructions. Update existing
777 instruction to include PPCVLE if supported.
778 * ppc-dis.c (ppc_opts): Add vle entry.
779 (get_powerpc_dialect): New function.
780 (powerpc_init_dialect): VLE support.
781 (print_insn_big_powerpc): Call get_powerpc_dialect.
782 (print_insn_little_powerpc): Likewise.
783 (operand_value_powerpc): Handle negative shift counts.
784 (print_insn_powerpc): Handle 2-byte instruction lengths.
786 2012-05-11 Daniel Richard G. <skunk@iskunk.org>
789 * configure.in: Invoke ACX_HEADER_STRING.
790 * configure: Regenerate.
791 * config.in: Regenerate.
792 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
793 string.h and strings.h.
795 2012-05-11 Nick Clifton <nickc@redhat.com>
798 * arm-dis.c (print_insn): Fix detection of instruction mode in
799 files containing multiple executable sections.
801 2012-05-03 Sean Keys <skeys@ipdatasys.com>
803 * Makefile.in, configure: regenerate
804 * disassemble.c (disassembler): Recognize ARCH_XGATE.
805 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
807 * configure.in: Recognize xgate.
808 * xgate-dis.c, xgate-opc.c: New files for support of xgate
809 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
810 and opcode generation for xgate.
812 2012-04-30 DJ Delorie <dj@redhat.com>
814 * rx-decode.opc (MOV): Do not sign-extend immediates which are
815 already the maximum bit size.
816 * rx-decode.c: Regenerate.
818 2012-04-27 David S. Miller <davem@davemloft.net>
820 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
821 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
823 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
824 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
826 * sparc-opc.c (CBCOND): New define.
827 (CBCOND_XCC): Likewise.
828 (cbcond): New helper macro.
829 (sparc_opcodes): Add compare-and-branch instructions.
831 * sparc-dis.c (print_insn_sparc): Handle ')'.
832 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
834 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
835 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
837 2012-04-12 David S. Miller <davem@davemloft.net>
839 * sparc-dis.c (X_DISP10): Define.
840 (print_insn_sparc): Handle '='.
842 2012-04-01 Mike Frysinger <vapier@gentoo.org>
844 * bfin-dis.c (fmtconst): Replace decimal handling with a single
845 sprintf call and the '*' field width.
847 2012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
849 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
851 2012-03-16 Alan Modra <amodra@gmail.com>
853 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
854 (powerpc_opcd_indices): Bump array size.
855 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
856 corresponding to unused opcodes to following entry.
857 (lookup_powerpc): New function, extracted and optimised from..
858 (print_insn_powerpc): ..here.
860 2012-03-15 Alan Modra <amodra@gmail.com>
861 James Lemke <jwlemke@codesourcery.com>
863 * disassemble.c (disassemble_init_for_target): Handle ppc init.
864 * ppc-dis.c (private): New var.
865 (powerpc_init_dialect): Don't return calloc failure, instead use
867 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
868 (powerpc_opcd_indices): New array.
869 (disassemble_init_powerpc): New function.
870 (print_insn_big_powerpc): Don't init dialect here.
871 (print_insn_little_powerpc): Likewise.
872 (print_insn_powerpc): Start search using powerpc_opcd_indices.
874 2012-03-10 Edmar Wienskoski <edmar@freescale.com>
876 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
877 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
878 (PPCVEC2, PPCTMR, E6500): New short names.
879 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
880 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
881 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
882 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
883 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
884 optional operands on sync instruction for E6500 target.
886 2012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
888 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
890 2012-02-27 Alan Modra <amodra@gmail.com>
892 * mt-dis.c: Regenerate.
894 2012-02-27 Alan Modra <amodra@gmail.com>
896 * v850-opc.c (extract_v8): Rearrange to make it obvious this
897 is the inverse of corresponding insert function.
898 (extract_d22, extract_u9, extract_r4): Likewise.
899 (extract_d9): Correct sign extension.
900 (extract_d16_15): Don't assume "long" is 32 bits, and don't
901 rely on implementation defined behaviour for shift right of
903 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
904 (extract_d23): Likewise, and correct mask.
906 2012-02-27 Alan Modra <amodra@gmail.com>
908 * crx-dis.c (print_arg): Mask constant to 32 bits.
909 * crx-opc.c (cst4_map): Use int array.
911 2012-02-27 Alan Modra <amodra@gmail.com>
913 * arc-dis.c (BITS): Don't use shifts to mask off bits.
914 (FIELDD): Sign extend with xor,sub.
916 2012-02-25 Walter Lee <walt@tilera.com>
918 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
919 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
920 TILEPRO_OPC_LW_TLS_SN.
922 2012-02-21 H.J. Lu <hongjiu.lu@intel.com>
924 * i386-opc.h (HLEPrefixNone): New.
925 (HLEPrefixLock): Likewise.
926 (HLEPrefixAny): Likewise.
927 (HLEPrefixRelease): Likewise.
929 2012-02-08 H.J. Lu <hongjiu.lu@intel.com>
931 * i386-dis.c (HLE_Fixup1): New.
932 (HLE_Fixup2): Likewise.
933 (HLE_Fixup3): Likewise.
940 (MOD_C6_REG_7): Likewise.
941 (MOD_C7_REG_7): Likewise.
942 (RM_C6_REG_7): Likewise.
943 (RM_C7_REG_7): Likewise.
944 (XACQUIRE_PREFIX): Likewise.
945 (XRELEASE_PREFIX): Likewise.
946 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
947 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
948 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
949 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
950 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
951 MOD_C6_REG_7 and MOD_C7_REG_7.
952 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
953 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
955 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
956 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
958 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
960 (cpu_flags): Add CpuHLE and CpuRTM.
961 (opcode_modifiers): Add HLEPrefixOk.
963 * i386-opc.h (CpuHLE): New.
965 (HLEPrefixOk): Likewise.
966 (i386_cpu_flags): Add cpuhle and cpurtm.
967 (i386_opcode_modifier): Add hleprefixok.
969 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
970 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
971 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
972 operand. Add xacquire, xrelease, xabort, xbegin, xend and
974 * i386-init.h: Regenerated.
975 * i386-tbl.h: Likewise.
977 2012-01-24 DJ Delorie <dj@redhat.com>
979 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
980 * rl78-decode.c: Regenerate.
982 2012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
985 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
987 2012-01-17 Andreas Schwab <schwab@linux-m68k.org>
989 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
990 register and move them after pmove with PSR/PCSR register.
992 2012-01-13 H.J. Lu <hongjiu.lu@intel.com>
994 * i386-dis.c (mod_table): Add vmfunc.
996 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
997 (cpu_flags): CpuVMFUNC.
999 * i386-opc.h (CpuVMFUNC): New.
1000 (i386_cpu_flags): Add cpuvmfunc.
1002 * i386-opc.tbl: Add vmfunc.
1003 * i386-init.h: Regenerated.
1004 * i386-tbl.h: Likewise.
1006 For older changes see ChangeLog-2011
1012 version-control: never