1 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (PREFIX_VEX_38XX): Add a tab.
4 (PREFIX_VEX_3AXX): Likewis.
6 2008-04-07 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-opc.tbl: Remove 4 extra blank lines.
10 2008-04-04 H.J. Lu <hongjiu.lu@intel.com>
12 * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL
13 with CPU_PCLMUL_FLAGS/CpuPCLMUL.
14 (cpu_flags): Replace CpuCLMUL with CpuPCLMUL.
15 * i386-opc.tbl: Likewise.
17 * i386-opc.h (CpuCLMUL): Renamed to ...
20 (i386_cpu_flags): Replace cpuclmul with cpupclmul.
22 * i386-init.h: Regenerated.
24 2008-04-03 H.J. Lu <hongjiu.lu@intel.com>
26 * i386-dis.c (OP_E_register): New.
27 (OP_E_memory): Likewise.
29 (OP_EX_Vex): Likewise.
30 (OP_EX_VexW): Likewise.
31 (OP_XMM_Vex): Likewise.
32 (OP_XMM_VexW): Likewise.
33 (OP_REG_VexI4): Likewise.
34 (PCLMUL_Fixup): Likewise.
35 (VEXI4_Fixup): Likewise.
36 (VZERO_Fixup): Likewise.
37 (VCMP_Fixup): Likewise.
38 (VPERMIL2_Fixup): Likewise.
39 (rex_original): Likewise.
40 (rex_ignored): Likewise.
63 (xmmq_mode): Likewise.
64 (ymmq_mode): Likewise.
66 (vex128_mode): Likewise.
67 (vex256_mode): Likewise.
68 (USE_VEX_C4_TABLE): Likewise.
69 (USE_VEX_C5_TABLE): Likewise.
70 (USE_VEX_LEN_TABLE): Likewise.
71 (VEX_C4_TABLE): Likewise.
72 (VEX_C5_TABLE): Likewise.
73 (VEX_LEN_TABLE): Likewise.
74 (REG_VEX_XX): Likewise.
75 (MOD_VEX_XXX): Likewise.
76 (PREFIX_0F38DB..PREFIX_0F38DF): Likewise.
77 (PREFIX_0F3A44): Likewise.
78 (PREFIX_0F3ADF): Likewise.
79 (PREFIX_VEX_XXX): Likewise.
83 (VEX_LEN_XXX): Likewise.
86 (need_vex_reg): Likewise.
87 (vex_i4_done): Likewise.
88 (vex_table): Likewise.
89 (vex_len_table): Likewise.
90 (OP_REG_VexI4): Likewise.
91 (vex_cmp_op): Likewise.
92 (pclmul_op): Likewise.
93 (vpermil2_op): Likewise.
96 (PREFIX_0F38F0): Likewise.
97 (PREFIX_0F3A60): Likewise.
98 (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE.
99 (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF
100 and PREFIX_VEX_XXX entries.
101 (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE.
102 (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and
104 (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE.
105 Add MOD_VEX_XXX entries.
106 (ckprefix): Initialize rex_original and rex_ignored. Store the
107 REX byte in rex_original.
108 (get_valid_dis386): Handle the implicit prefix in VEX prefix
109 bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE.
110 (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before
111 calling get_valid_dis386. Use rex_original and rex_ignored when
113 (putop): Handle "XY".
114 (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and
116 (OP_E_extended): Updated to use OP_E_register and
118 (OP_XMM): Handle VEX.
120 (XMM_Fixup): Likewise.
121 (CMP_Fixup): Use ARRAY_SIZE.
123 * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS,
124 CPU_FMA_FLAGS and CPU_AVX_FLAGS.
125 (operand_type_init): Add OPERAND_TYPE_REGYMM and
126 OPERAND_TYPE_VEX_IMM4.
127 (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA.
128 (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD,
129 VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources,
130 VexImmExt and SSE2AVX.
131 (operand_types): Add RegYMM, Ymmword and Vex_Imm4.
133 * i386-opc.h (CpuAVX): New.
135 (CpuCLMUL): Likewise.
146 (Vex3Sources): Likewise.
147 (VexImmExt): Likewise.
151 (Vex_Imm4): Likewise.
152 (Implicit1stXmm0): Likewise.
155 (ByteOkIntel): Likewise.
158 (Unspecified): Likewise.
160 (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma.
161 (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256,
162 vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a,
163 vex3sources, veximmext and sse2avx.
164 (i386_operand_type): Add regymm, ymmword and vex_imm4.
166 * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions.
168 * i386-reg.tbl: Add AVX registers, ymm0..ymm15.
170 * i386-init.h: Regenerated.
171 * i386-tbl.h: Likewise.
173 2008-03-26 Bernd Schmidt <bernd.schmidt@analog.com>
175 From Robin Getz <robin.getz@analog.com>
176 * bfin-dis.c (bu32): Typedef.
177 (enum const_forms_t): Add c_uimm32 and c_huimm32.
178 (constant_formats[]): Add uimm32 and huimm16.
183 (luimm16_val): Define.
184 (struct saved_state): Define.
185 (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG,
186 A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG,
187 LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define.
189 (decode_LDIMMhalf_0): Print out the whole register value.
191 From Jie Zhang <jie.zhang@analog.com>
192 * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for
193 multiply and multiply-accumulate to data register instruction.
195 * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d,
196 c_imm32, c_huimm32e): Define.
197 (constant_formats): Add flags for printing decimal, leading spaces, and
199 (comment, parallel): Add global flags in all disassembly.
200 (fmtconst): Take advantage of new flags, and print default in hex.
201 (fmtconst_val): Likewise.
202 (decode_macfunc): Be consistant with spaces, tabs, comments,
203 capitalization in disassembly, fix minor coding style issues.
204 (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise.
205 (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0,
206 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
207 decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0,
208 decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
209 decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0,
210 decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0,
211 decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0,
212 decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0,
213 decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0,
214 _print_insn_bfin, print_insn_bfin): Likewise.
216 2008-03-17 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
218 * aclocal.m4: Regenerate.
219 * configure: Likewise.
220 * Makefile.in: Likewise.
222 2008-03-13 Alan Modra <amodra@bigpond.net.au>
224 * Makefile.am: Run "make dep-am".
225 * Makefile.in: Regenerate.
226 * configure: Regenerate.
228 2008-03-07 Alan Modra <amodra@bigpond.net.au>
230 * ppc-opc.c (powerpc_opcodes): Order and format.
232 2008-03-01 H.J. Lu <hongjiu.lu@intel.com>
234 * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64.
235 * i386-tbl.h: Regenerated.
237 2008-02-23 H.J. Lu <hongjiu.lu@intel.com>
239 * i386-opc.tbl: Disallow 16-bit near indirect branches for
241 * i386-tbl.h: Regenerated.
243 2008-02-21 Jan Beulich <jbeulich@novell.com>
245 * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword
246 and Fword for far indirect jmp. Allow Reg16 and Word for near
247 indirect jmp on x86-64. Disallow Fword for lcall.
248 * i386-tbl.h: Re-generate.
250 2008-02-18 M R Swami Reddy <MR.Swami.Reddy@nsc.com>
252 * cr16-opc.c (cr16_num_optab): Defined
254 2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
256 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG.
257 * i386-init.h: Regenerated.
259 2008-02-14 Nick Clifton <nickc@redhat.com>
262 * configure.in (SHARED_LIBADD): Select the correct host specific
263 file extension for shared libraries.
264 * configure: Regenerate.
266 2008-02-13 Jan Beulich <jbeulich@novell.com>
268 * i386-opc.h (RegFlat): New.
269 * i386-reg.tbl (flat): Add.
270 * i386-tbl.h: Re-generate.
272 2008-02-13 Jan Beulich <jbeulich@novell.com>
274 * i386-dis.c (a_mode): New.
275 (cond_jump_mode): Adjust.
276 (Ma): Change to a_mode.
277 (intel_operand_size): Handle a_mode.
278 * i386-opc.tbl: Allow Dword and Qword for bound.
279 * i386-tbl.h: Re-generate.
281 2008-02-13 Jan Beulich <jbeulich@novell.com>
283 * i386-gen.c (process_i386_registers): Process new fields.
284 * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to
285 unsigned char. Add dw2_regnum and Dw2Inval.
286 * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo
288 * i386-tbl.h: Re-generate.
290 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
292 * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS.
293 * i386-init.h: Updated.
295 2008-02-11 H.J. Lu <hongjiu.lu@intel.com>
297 * i386-gen.c (cpu_flags): Add CpuXsave.
299 * i386-opc.h (CpuXsave): New.
301 (i386_cpu_flags): Add cpuxsave.
303 * i386-dis.c (MOD_0FAE_REG_4): New.
304 (RM_0F01_REG_2): Likewise.
305 (MOD_0FAE_REG_5): Updated.
306 (RM_0F01_REG_3): Likewise.
307 (reg_table): Use MOD_0FAE_REG_4.
308 (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated
310 (rm_table): Add RM_0F01_REG_2.
312 * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv.
313 * i386-init.h: Regenerated.
314 * i386-tbl.h: Likewise.
316 2008-02-11 Jan Beulich <jbeulich@novell.com>
318 * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove
319 Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz).
320 * i386-tbl.h: Re-generate.
322 2008-02-04 H.J. Lu <hongjiu.lu@intel.com>
325 * configure: Regenerated.
327 2008-02-04 Adam Nemet <anemet@caviumnetworks.com>
329 * mips-dis.c: Update copyright.
330 (mips_arch_choices): Add Octeon.
331 * mips-opc.c: Update copyright.
333 (mips_builtin_opcodes): Add Octeon instruction synciobdma.
335 2008-01-29 Alan Modra <amodra@bigpond.net.au>
337 * ppc-opc.c: Support optional L form mtmsr.
339 2008-01-24 H.J. Lu <hongjiu.lu@intel.com>
341 * i386-dis.c (OP_E_extended): Handle r12 like rsp.
343 2008-01-23 H.J. Lu <hongjiu.lu@intel.com>
345 * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS.
346 * i386-init.h: Regenerated.
348 2008-01-23 Tristan Gingold <gingold@adacore.com>
350 * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr,
351 ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.
353 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
355 * i386-gen.c (cpu_flag_init): Remove CpuMMX2.
356 (cpu_flags): Likewise.
358 * i386-opc.h (CpuMMX2): Removed.
361 * i386-opc.tbl: Replace CpuMMX2 with CpuSSE|Cpu3dnowA.
362 * i386-init.h: Regenerated.
363 * i386-tbl.h: Likewise.
365 2008-01-22 H.J. Lu <hongjiu.lu@intel.com>
367 * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and
369 * i386-init.h: Regenerated.
371 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
373 * i386-opc.tbl: Use Qword on movddup.
374 * i386-tbl.h: Regenerated.
376 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
378 * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax.
379 * i386-tbl.h: Regenerated.
381 2008-01-15 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-dis.c (Mx): New.
384 (PREFIX_0FC3): Likewise.
385 (PREFIX_0FC7_REG_6): Updated.
386 (dis386_twobyte): Use PREFIX_0FC3.
387 (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd.
388 Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on
391 2008-01-14 H.J. Lu <hongjiu.lu@intel.com>
393 * i386-gen.c (opcode_modifiers): Add IntelSyntax.
394 (operand_types): Add Mem.
396 * i386-opc.h (IntelSyntax): New.
397 * i386-opc.h (Mem): New.
399 (Opcode_Modifier_Max): Updated.
400 (i386_opcode_modifier): Add intelsyntax.
401 (i386_operand_type): Add mem.
403 * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more
406 * i386-reg.tbl: Add size for accumulator.
408 * i386-init.h: Regenerated.
409 * i386-tbl.h: Likewise.
411 2008-01-13 H.J. Lu <hongjiu.lu@intel.com>
413 * i386-opc.h (Byte): Fix a typo.
415 2008-01-12 H.J. Lu <hongjiu.lu@intel.com>
418 * i386-gen.c (operand_type_init): Add Dword to
419 OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64.
420 (opcode_modifiers): Remove CheckSize, Byte, Word, Dword,
422 (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte,
423 Xmmword, Unspecified and Anysize.
424 (set_bitfield): Make Mmword an alias of Qword. Make Oword
427 * i386-opc.h (CheckSize): Removed.
435 (i386_opcode_modifier): Remove checksize, byte, word, dword,
439 (Unspecified): Likewise.
441 (i386_operand_type): Add byte, word, dword, fword, qword,
442 tbyte xmmword, unspecified and anysize.
444 * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword,
445 Tbyte, Xmmword, Unspecified and Anysize.
447 * i386-reg.tbl: Add size for accumulator.
449 * i386-init.h: Regenerated.
450 * i386-tbl.h: Likewise.
452 2008-01-10 H.J. Lu <hongjiu.lu@intel.com>
454 * i386-dis.c (REG_0F0E): Renamed to REG_0F0D.
456 (reg_table): Updated.
457 (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e.
458 (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.
460 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
462 * i386-gen.c (set_bitfield): Use fail () on error.
464 2008-01-08 H.J. Lu <hongjiu.lu@intel.com>
466 * i386-gen.c (lineno): New.
467 (filename): Likewise.
468 (set_bitfield): Report filename and line numer on error.
469 (process_i386_opcodes): Set filename and update lineno.
470 (process_i386_registers): Likewise.
472 2008-01-05 H.J. Lu <hongjiu.lu@intel.com>
474 * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to
477 * i386-opc.h (IntelMnemonic): Renamed to ..
479 (Opcode_Modifier_Max): Updated.
480 (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax
483 * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax
484 on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp.
485 * i386-tbl.h: Regenerated.
487 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
489 * i386-gen.c: Update copyright to 2008.
490 * i386-opc.h: Likewise.
491 * i386-opc.tbl: Likewise.
493 * i386-init.h: Regenerated.
494 * i386-tbl.h: Likewise.
496 2008-01-04 H.J. Lu <hongjiu.lu@intel.com>
498 * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps,
499 pextrb, pextrw, pinsrb, pinsrw and pmovmskb.
500 * i386-tbl.h: Regenerated.
502 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
504 * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and
506 (cpu_flags): Likewise.
508 * i386-opc.h (CpuSSE4_1_Or_5): Removed.
509 (CpuSSE4_2_Or_ABM): Likewise.
511 (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm.
513 * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and
514 Cpu686|CpuPadLock with CpuSSE4_1|CpuSSE5, CpuABM|CpuSSE4_2
515 and CpuPadLock, respectively.
516 * i386-init.h: Regenerated.
517 * i386-tbl.h: Likewise.
519 2008-01-03 H.J. Lu <hongjiu.lu@intel.com>
521 * i386-gen.c (opcode_modifiers): Remove No_xSuf.
523 * i386-opc.h (No_xSuf): Removed.
524 (CheckSize): Updated.
526 * i386-tbl.h: Regenerated.
528 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
530 * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to
531 CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and
533 (cpu_flags): Add CpuSSE4_2_Or_ABM.
535 * i386-opc.h (CpuSSE4_2_Or_ABM): New.
537 (i386_cpu_flags): Add cpusse4_2_or_abm.
539 * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of
540 CpuABM|CpuSSE4_2 on popcnt.
541 * i386-init.h: Regenerated.
542 * i386-tbl.h: Likewise.
544 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
546 * i386-opc.h: Update comments.
548 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
550 * i386-gen.c (opcode_modifiers): Use Qword instead of QWord.
551 * i386-opc.h: Likewise.
552 * i386-opc.tbl: Likewise.
554 2008-01-02 H.J. Lu <hongjiu.lu@intel.com>
557 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize,
558 Byte, Word, Dword, QWord and Xmmword.
560 * i386-opc.h (No_xSuf): New.
561 (CheckSize): Likewise.
568 (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word,
569 Dword, QWord and Xmmword.
571 * i386-opc.tbl: Add CheckSize|QWord to movq if IgnoreSize is
573 * i386-tbl.h: Regenerated.
575 2008-01-02 Mark Kettenis <kettenis@gnu.org>
577 * m88k-dis.c (instructions): Fix fcvt.* instructions.
580 For older changes see ChangeLog-2007
586 version-control: never