1 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
4 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
5 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
7 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
9 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
10 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
12 (prefix_table): Updated.
13 (three_byte_table): Likewise.
14 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
15 (cpu_flags): Add CpuSHA.
16 (i386_cpu_flags): Add cpusha.
17 * i386-init.h: Regenerate.
18 * i386-opc.h (CpuSHA): New.
19 (CpuUnused): Restored.
20 (i386_cpu_flags): Add cpusha.
21 * i386-opc.tbl: Add SHA instructions.
22 * i386-tbl.h: Regenerate.
24 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
25 Kirill Yukhin <kirill.yukhin@intel.com>
26 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
28 * i386-dis.c (BND_Fixup): New.
35 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
37 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
38 (dis tables): Replace XX with BND for near branch and call
40 (prefix_table): Add new entries.
41 (mod_table): Likewise.
43 (intel_names_bnd): New.
46 (prefix_name): Handle BND_PREFIX.
47 (print_insn): Initialize names_bnd.
48 (intel_operand_size): Handle new modes.
49 (OP_E_register): Likewise.
50 (OP_E_memory): Likewise.
52 * i386-gen.c (cpu_flag_init): Add CpuMPX.
53 (cpu_flags): Add CpuMPX.
54 (operand_type_init): Add RegBND.
55 (opcode_modifiers): Add BNDPrefixOk.
56 (operand_types): Add RegBND.
57 * i386-init.h: Regenerate.
58 * i386-opc.h (CpuMPX): New.
59 (CpuUnused): Comment out.
60 (i386_cpu_flags): Add cpumpx.
62 (i386_opcode_modifier): Add bndprefixok.
64 (i386_operand_type): Add regbnd.
65 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
66 Add MPX instructions and bnd prefix.
67 * i386-reg.tbl: Add bnd0-bnd3 registers.
68 * i386-tbl.h: Regenerate.
70 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
72 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
75 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
77 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
79 * Makefile.in: Regenerate.
80 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
83 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
85 * mips16-opc.c: Include mips-formats.h.
86 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
88 (decode_mips16_operand): New function.
89 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
90 (print_insn_arg): Handle OP_ENTRY_EXIT list.
91 Abort for OP_SAVE_RESTORE_LIST.
92 (print_mips16_insn_arg): Change interface. Use mips_operand
93 structures. Delete GET_OP_S. Move GET_OP definition to...
94 (print_insn_mips16): ...here. Call init_print_arg_state.
95 Update the call to print_mips16_insn_arg.
97 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
99 * mips-formats.h: New file.
100 * mips-opc.c: Include mips-formats.h.
101 (reg_0_map): New static array.
102 (decode_mips_operand): New function.
103 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
104 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
105 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
106 (int_c_map): New static arrays.
107 (decode_micromips_operand): New function.
108 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
109 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
110 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
111 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
112 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
113 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
114 (micromips_imm_b_map, micromips_imm_c_map): Delete.
115 (print_reg): New function.
116 (mips_print_arg_state): New structure.
117 (init_print_arg_state, print_insn_arg): New functions.
118 (print_insn_args): Change interface and use mips_operand structures.
119 Delete GET_OP_S. Move GET_OP definition to...
120 (print_insn_mips): ...here. Update the call to print_insn_args.
121 (print_insn_micromips): Use print_insn_args.
123 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
125 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
128 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
130 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
131 ADDA.S, MULA.S and SUBA.S.
133 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
136 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
137 * i386-tbl.h: Regenerated.
139 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
141 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
142 and SD A(B) macros up.
143 * micromips-opc.c (micromips_opcodes): Likewise.
145 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
147 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
150 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
152 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
153 MDMX-like instructions.
154 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
155 printing "Q" operands for INSN_5400 instructions.
157 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
159 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
161 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
164 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
166 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
168 * mips16-opc.c (mips16_opcodes): Likewise.
169 * micromips-opc.c (micromips_opcodes): Likewise.
170 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
171 (print_insn_mips16): Handle "+i".
172 (print_insn_micromips): Likewise. Conditionally preserve the
173 ISA bit for "a" but not for "+i".
175 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
177 * micromips-opc.c (WR_mhi): Rename to..
179 (micromips_opcodes): Update "movep" entry accordingly. Replace
181 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
182 (micromips_to_32_reg_h_map1): ...this.
183 (micromips_to_32_reg_i_map): Rename to...
184 (micromips_to_32_reg_h_map2): ...this.
185 (print_micromips_insn): Remove "mi" case. Print both registers
186 in the pair for "mh".
188 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
190 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
191 * micromips-opc.c (micromips_opcodes): Likewise.
192 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
193 and "+T" handling. Check for a "0" suffix when deciding whether to
194 use coprocessor 0 names. In that case, also check for ",H" selectors.
196 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
198 * s390-opc.c (J12_12, J24_24): New macros.
199 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
200 (MASK_MII_UPI): Rename to MASK_MII_UPP.
201 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
203 2013-07-04 Alan Modra <amodra@gmail.com>
205 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
207 2013-06-26 Nick Clifton <nickc@redhat.com>
209 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
210 field when checking for type 2 nop.
211 * rx-decode.c: Regenerate.
213 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
215 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
218 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
220 * mips-dis.c (is_mips16_plt_tail): New function.
221 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
223 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
225 2013-06-21 DJ Delorie <dj@redhat.com>
227 * msp430-decode.opc: New.
228 * msp430-decode.c: New/generated.
229 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
230 (MAINTAINER_CLEANFILES): Likewise.
231 Add rule to build msp430-decode.c frommsp430decode.opc
232 using the opc2c program.
233 * Makefile.in: Regenerate.
234 * configure.in: Add msp430-decode.lo to msp430 architecture files.
235 * configure: Regenerate.
237 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
239 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
240 (SYMTAB_AVAILABLE): Removed.
241 (#include "elf/aarch64.h): Ditto.
243 2013-06-17 Catherine Moore <clm@codesourcery.com>
244 Maciej W. Rozycki <macro@codesourcery.com>
245 Chao-Ying Fu <fu@mips.com>
247 * micromips-opc.c (EVA): Define.
249 (micromips_opcodes): Add EVA opcodes.
250 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
251 (print_insn_args): Handle EVA offsets.
252 (print_insn_micromips): Likewise.
253 * mips-opc.c (EVA): Define.
255 (mips_builtin_opcodes): Add EVA opcodes.
257 2013-06-17 Alan Modra <amodra@gmail.com>
259 * Makefile.am (mips-opc.lo): Add rules to create automatic
260 dependency files. Pass archdefs.
261 (micromips-opc.lo, mips16-opc.lo): Likewise.
262 * Makefile.in: Regenerate.
264 2013-06-14 DJ Delorie <dj@redhat.com>
266 * rx-decode.opc (rx_decode_opcode): Bit operations on
267 registers are 32-bit operations, not 8-bit operations.
268 * rx-decode.c: Regenerate.
270 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
272 * micromips-opc.c (IVIRT): New define.
273 (IVIRT64): New define.
274 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
275 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
277 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
278 dmtgc0 to print cp0 names.
280 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
282 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
285 2013-06-08 Catherine Moore <clm@codesourcery.com>
286 Richard Sandiford <rdsandiford@googlemail.com>
288 * micromips-opc.c (D32, D33, MC): Update definitions.
289 (micromips_opcodes): Initialize ase field.
290 * mips-dis.c (mips_arch_choice): Add ase field.
291 (mips_arch_choices): Initialize ase field.
292 (set_default_mips_dis_options): Declare and setup mips_ase.
293 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
294 MT32, MC): Update definitions.
295 (mips_builtin_opcodes): Initialize ase field.
297 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
299 * s390-opc.txt (flogr): Require a register pair destination.
301 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
303 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
306 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
308 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
310 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
312 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
313 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
314 XLS_MASK, PPCVSX2): New defines.
315 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
316 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
317 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
318 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
319 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
320 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
321 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
322 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
323 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
324 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
325 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
326 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
327 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
328 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
329 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
330 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
331 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
332 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
333 <lxvx, stxvx>: New extended mnemonics.
335 2013-05-17 Alan Modra <amodra@gmail.com>
337 * ia64-raw.tbl: Replace non-ASCII char.
338 * ia64-waw.tbl: Likewise.
339 * ia64-asmtab.c: Regenerate.
341 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
343 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
344 * i386-init.h: Regenerated.
346 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
348 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
349 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
350 check from [0, 255] to [-128, 255].
352 2013-05-09 Andrew Pinski <apinski@cavium.com>
354 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
355 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
356 (parse_mips_dis_option): Handle the virt option.
357 (print_insn_args): Handle "+J".
358 (print_mips_disassembler_options): Print out message about virt64.
359 * mips-opc.c (IVIRT): New define.
360 (IVIRT64): New define.
361 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
362 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
363 Move rfe to the bottom as it conflicts with tlbgp.
365 2013-05-09 Alan Modra <amodra@gmail.com>
367 * ppc-opc.c (extract_vlesi): Properly sign extend.
368 (extract_vlensi): Likewise. Comment reason for setting invalid.
370 2013-05-02 Nick Clifton <nickc@redhat.com>
372 * msp430-dis.c: Add support for MSP430X instructions.
374 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
376 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
379 2013-04-17 Wei-chen Wang <cole945@gmail.com>
382 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
384 (hash_insns_list): Likewise.
386 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
388 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
391 2013-04-08 Jan Beulich <jbeulich@suse.com>
393 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
394 * i386-tbl.h: Re-generate.
396 2013-04-06 David S. Miller <davem@davemloft.net>
398 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
399 of an opcode, prefer the one with F_PREFERRED set.
400 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
401 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
402 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
403 mark existing mnenomics as aliases. Add "cc" suffix to edge
404 instructions generating condition codes, mark existing mnenomics
405 as aliases. Add "fp" prefix to VIS compare instructions, mark
406 existing mnenomics as aliases.
408 2013-04-03 Nick Clifton <nickc@redhat.com>
410 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
411 destination address by subtracting the operand from the current
413 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
414 a positive value in the insn.
415 (extract_u16_loop): Do not negate the returned value.
416 (D16_LOOP): Add V850_INVERSE_PCREL flag.
418 (ceilf.sw): Remove duplicate entry.
419 (cvtf.hs): New entry.
425 (maddf.s): Restrict to E3V5 architectures.
427 (nmaddf.s): Likewise.
428 (nmsubf.s): Likewise.
430 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
432 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
434 (print_insn): Pass sizeflag to get_sib.
436 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
439 * tic6x-dis.c: Add support for displaying 16-bit insns.
441 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
444 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
445 individual msb and lsb halves in src1 & src2 fields. Discard the
446 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
447 follow what Ti SDK does in that case as any value in the src1
448 field yields the same output with SDK disassembler.
450 2013-03-12 Michael Eager <eager@eagercon.com>
452 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
454 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
456 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
458 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
460 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
462 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
464 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
466 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
468 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
469 (thumb32_opcodes): Likewise.
470 (print_insn_thumb32): Handle 'S' control char.
472 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
474 * lm32-desc.c: Regenerate.
476 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
478 * i386-reg.tbl (riz): Add RegRex64.
479 * i386-tbl.h: Regenerated.
481 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
483 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
484 (aarch64_feature_crc): New static.
486 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
487 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
488 * aarch64-asm-2.c: Re-generate.
489 * aarch64-dis-2.c: Ditto.
490 * aarch64-opc-2.c: Ditto.
492 2013-02-27 Alan Modra <amodra@gmail.com>
494 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
495 * rl78-decode.c: Regenerate.
497 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
499 * rl78-decode.opc: Fix encoding of DIVWU insn.
500 * rl78-decode.c: Regenerate.
502 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
507 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
508 (cpu_flags): Add CpuSMAP.
510 * i386-opc.h (CpuSMAP): New.
511 (i386_cpu_flags): Add cpusmap.
513 * i386-opc.tbl: Add clac and stac.
515 * i386-init.h: Regenerated.
516 * i386-tbl.h: Likewise.
518 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
520 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
521 which also makes the disassembler output be in little
522 endian like it should be.
524 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
526 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
528 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
530 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
532 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
533 section disassembled.
535 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
537 * arm-dis.c: Update strht pattern.
539 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
541 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
542 single-float. Disable ll, lld, sc and scd for EE. Disable the
543 trunc.w.s macro for EE.
545 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
546 Andrew Jenner <andrew@codesourcery.com>
548 Based on patches from Altera Corporation.
550 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
552 * Makefile.in: Regenerated.
553 * configure.in: Add case for bfd_nios2_arch.
554 * configure: Regenerated.
555 * disassemble.c (ARCH_nios2): Define.
556 (disassembler): Add case for bfd_arch_nios2.
557 * nios2-dis.c: New file.
558 * nios2-opc.c: New file.
560 2013-02-04 Alan Modra <amodra@gmail.com>
562 * po/POTFILES.in: Regenerate.
563 * rl78-decode.c: Regenerate.
564 * rx-decode.c: Regenerate.
566 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
568 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
569 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
570 * aarch64-asm.c (convert_xtl_to_shll): New function.
571 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
572 calling convert_xtl_to_shll.
573 * aarch64-dis.c (convert_shll_to_xtl): New function.
574 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
575 calling convert_shll_to_xtl.
576 * aarch64-gen.c: Update copyright year.
577 * aarch64-asm-2.c: Re-generate.
578 * aarch64-dis-2.c: Re-generate.
579 * aarch64-opc-2.c: Re-generate.
581 2013-01-24 Nick Clifton <nickc@redhat.com>
583 * v850-dis.c: Add support for e3v5 architecture.
584 * v850-opc.c: Likewise.
586 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
588 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
589 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
590 * aarch64-opc.c (operand_general_constraint_met_p): For
591 AARCH64_MOD_LSL, move the range check on the shift amount before the
592 alignment check; change to call set_sft_amount_out_of_range_error
593 instead of set_imm_out_of_range_error.
594 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
595 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
596 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
599 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
601 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
603 * i386-init.h: Regenerated.
604 * i386-tbl.h: Likewise.
606 2013-01-15 Nick Clifton <nickc@redhat.com>
608 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
610 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
612 2013-01-14 Will Newton <will.newton@imgtec.com>
614 * metag-dis.c (REG_WIDTH): Increase to 64.
616 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
618 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
619 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
620 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
622 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
623 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
624 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
625 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
627 2013-01-10 Will Newton <will.newton@imgtec.com>
629 * Makefile.am: Add Meta.
630 * configure.in: Add Meta.
631 * disassemble.c: Add Meta support.
632 * metag-dis.c: New file.
633 * Makefile.in: Regenerate.
634 * configure: Regenerate.
636 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
638 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
639 (match_opcode): Rename to cr16_match_opcode.
641 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
643 * mips-dis.c: Add names for CP0 registers of r5900.
644 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
645 instructions sq and lq.
646 Add support for MIPS r5900 CPU.
647 Add support for 128 bit MMI (Multimedia Instructions).
648 Add support for EE instructions (Emotion Engine).
649 Disable unsupported floating point instructions (64 bit and
650 undefined compare operations).
651 Enable instructions of MIPS ISA IV which are supported by r5900.
652 Disable 64 bit co processor instructions.
653 Disable 64 bit multiplication and division instructions.
654 Disable instructions for co-processor 2 and 3, because these are
655 not supported (preparation for later VU0 support (Vector Unit)).
656 Disable cvt.w.s because this behaves like trunc.w.s and the
657 correct execution can't be ensured on r5900.
658 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
659 will confuse less developers and compilers.
661 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
663 * aarch64-opc.c (aarch64_print_operand): Change to print
664 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
666 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
667 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
670 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
672 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
673 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
675 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
677 * i386-gen.c (process_copyright): Update copyright year to 2013.
679 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
681 * cr16-dis.c (match_opcode,make_instruction): Remove static
683 (dwordU,wordU): Moved typedefs to opcode/cr16.h
684 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
686 For older changes see ChangeLog-2012
688 Copyright (C) 2013 Free Software Foundation, Inc.
690 Copying and distribution of this file, with or without modification,
691 are permitted in any medium without royalty provided the copyright
692 notice and this notice are preserved.
698 version-control: never