1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
5 * i386-tbl.h: Re-generate.
7 2018-09-13 Jan Beulich <jbeulich@suse.com>
9 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
11 * i386-tbl.h: Re-generate.
13 2018-09-13 Jan Beulich <jbeulich@suse.com>
15 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
17 * i386-tbl.h: Re-generate.
19 2018-09-13 Jan Beulich <jbeulich@suse.com>
21 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
23 * i386-tbl.h: Re-generate.
25 2018-09-13 Jan Beulich <jbeulich@suse.com>
27 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
28 * i386-tbl.h: Re-generate.
30 2018-09-13 Jan Beulich <jbeulich@suse.com>
32 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
33 * i386-tbl.h: Re-generate.
35 2018-09-13 Jan Beulich <jbeulich@suse.com>
37 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
39 * i386-tbl.h: Re-generate.
41 2018-09-13 Jan Beulich <jbeulich@suse.com>
43 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
45 * i386-tbl.h: Re-generate.
47 2018-09-13 Jan Beulich <jbeulich@suse.com>
49 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
50 * i386-tbl.h: Re-generate.
52 2018-09-13 Jan Beulich <jbeulich@suse.com>
54 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
55 * i386-tbl.h: Re-generate.
57 2018-09-13 Jan Beulich <jbeulich@suse.com>
59 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
60 * i386-tbl.h: Re-generate.
62 2018-09-13 Jan Beulich <jbeulich@suse.com>
64 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
66 * i386-tbl.h: Re-generate.
68 2018-09-13 Jan Beulich <jbeulich@suse.com>
70 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
72 * i386-tbl.h: Re-generate.
74 2018-09-13 Jan Beulich <jbeulich@suse.com>
76 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
78 * i386-tbl.h: Re-generate.
80 2018-09-13 Jan Beulich <jbeulich@suse.com>
82 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
83 * i386-tbl.h: Re-generate.
85 2018-09-13 Jan Beulich <jbeulich@suse.com>
87 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
88 * i386-tbl.h: Re-generate.
90 2018-09-13 Jan Beulich <jbeulich@suse.com>
92 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
93 * i386-tbl.h: Re-generate.
95 2018-09-13 Jan Beulich <jbeulich@suse.com>
97 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
98 (vpbroadcastw, rdpid): Drop NoRex64.
99 * i386-tbl.h: Re-generate.
101 2018-09-13 Jan Beulich <jbeulich@suse.com>
103 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
104 store templates, adding D.
105 * i386-tbl.h: Re-generate.
107 2018-09-13 Jan Beulich <jbeulich@suse.com>
109 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
110 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
111 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
112 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
113 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
114 Fold load and store templates where possible, adding D. Drop
115 IgnoreSize where it was pointlessly present. Drop redundant
117 * i386-tbl.h: Re-generate.
119 2018-09-13 Jan Beulich <jbeulich@suse.com>
121 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
122 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
123 (intel_operand_size): Handle v_bndmk_mode.
124 (OP_E_memory): Likewise. Produce (bad) when also riprel.
126 2018-09-08 John Darrington <john@darrington.wattle.id.au>
128 * disassemble.c (ARCH_s12z): Define if ARCH_all.
130 2018-08-31 Kito Cheng <kito@andestech.com>
132 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
133 compressed floating point instructions.
135 2018-08-30 Kito Cheng <kito@andestech.com>
137 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
138 riscv_opcode.xlen_requirement.
139 * riscv-opc.c (riscv_opcodes): Update for struct change.
141 2018-08-29 Martin Aberg <maberg@gaisler.com>
143 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
144 psr (PWRPSR) instruction.
146 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
148 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
150 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
152 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
154 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
156 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
157 loongson3a as an alias of gs464 for compatibility.
158 * mips-opc.c (mips_opcodes): Change Comments.
160 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
162 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
164 (print_mips_disassembler_options): Document -M loongson-ext.
165 * mips-opc.c (LEXT2): New macro.
166 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
168 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
170 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
172 (parse_mips_ase_option): Handle -M loongson-ext option.
173 (print_mips_disassembler_options): Document -M loongson-ext.
174 * mips-opc.c (IL3A): Delete.
175 * mips-opc.c (LEXT): New macro.
176 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
179 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
181 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
183 (parse_mips_ase_option): Handle -M loongson-cam option.
184 (print_mips_disassembler_options): Document -M loongson-cam.
185 * mips-opc.c (LCAM): New macro.
186 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
189 2018-08-21 Alan Modra <amodra@gmail.com>
191 * ppc-dis.c (operand_value_powerpc): Init "invalid".
192 (skip_optional_operands): Count optional operands, and update
193 ppc_optional_operand_value call.
194 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
195 (extract_vlensi): Likewise.
196 (extract_fxm): Return default value for missing optional operand.
197 (extract_ls, extract_raq, extract_tbr): Likewise.
198 (insert_sxl, extract_sxl): New functions.
199 (insert_esync, extract_esync): Remove Power9 handling and simplify.
200 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
201 flag and extra entry.
202 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
205 2018-08-20 Alan Modra <amodra@gmail.com>
207 * sh-opc.h (MASK): Simplify.
209 2018-08-18 John Darrington <john@darrington.wattle.id.au>
211 * s12z-dis.c (bm_decode): Deal with cases where the mode is
212 BM_RESERVED0 or BM_RESERVED1
213 (bm_rel_decode, bm_n_bytes): Ditto.
215 2018-08-18 John Darrington <john@darrington.wattle.id.au>
219 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
221 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
222 address with the addr32 prefix and without base nor index
225 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
227 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
228 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
229 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
230 (cpu_flags): Add CpuCMOV and CpuFXSR.
231 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
232 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
233 * i386-init.h: Regenerated.
234 * i386-tbl.h: Likewise.
236 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
238 * arc-regs.h: Update auxiliary registers.
240 2018-08-06 Jan Beulich <jbeulich@suse.com>
242 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
243 (RegIP, RegIZ): Define.
244 * i386-reg.tbl: Adjust comments.
245 (rip): Use Qword instead of BaseIndex. Use RegIP.
246 (eip): Use Dword instead of BaseIndex. Use RegIP.
247 (riz): Add Qword. Use RegIZ.
248 (eiz): Add Dword. Use RegIZ.
249 * i386-tbl.h: Re-generate.
251 2018-08-03 Jan Beulich <jbeulich@suse.com>
253 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
254 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
255 vpmovzxdq, vpmovzxwd): Remove NoRex64.
256 * i386-tbl.h: Re-generate.
258 2018-08-03 Jan Beulich <jbeulich@suse.com>
260 * i386-gen.c (operand_types): Remove Mem field.
261 * i386-opc.h (union i386_operand_type): Remove mem field.
262 * i386-init.h, i386-tbl.h: Re-generate.
264 2018-08-01 Alan Modra <amodra@gmail.com>
266 * po/POTFILES.in: Regenerate.
268 2018-07-31 Nick Clifton <nickc@redhat.com>
270 * po/sv.po: Updated Swedish translation.
272 2018-07-31 Jan Beulich <jbeulich@suse.com>
274 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
275 * i386-init.h, i386-tbl.h: Re-generate.
277 2018-07-31 Jan Beulich <jbeulich@suse.com>
279 * i386-opc.h (ZEROING_MASKING) Rename to ...
280 (DYNAMIC_MASKING): ... this. Adjust comment.
281 * i386-opc.tbl (MaskingMorZ): Define.
282 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
283 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
284 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
285 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
286 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
287 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
288 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
289 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
290 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
292 2018-07-31 Jan Beulich <jbeulich@suse.com>
294 * i386-opc.tbl: Use element rather than vector size for AVX512*
295 scatter/gather insns.
296 * i386-tbl.h: Re-generate.
298 2018-07-31 Jan Beulich <jbeulich@suse.com>
300 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
301 (cpu_flags): Drop CpuVREX.
302 * i386-opc.h (CpuVREX): Delete.
303 (union i386_cpu_flags): Remove cpuvrex.
304 * i386-init.h, i386-tbl.h: Re-generate.
306 2018-07-30 Jim Wilson <jimw@sifive.com>
308 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
310 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
312 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
314 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
315 * Makefile.in: Regenerated.
316 * configure.ac: Add C-SKY.
317 * configure: Regenerated.
318 * csky-dis.c: New file.
319 * csky-opc.h: New file.
320 * disassemble.c (ARCH_csky): Define.
321 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
322 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
324 2018-07-27 Alan Modra <amodra@gmail.com>
326 * ppc-opc.c (insert_sprbat): Correct function parameter and
328 (extract_sprbat): Likewise, variable too.
330 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
331 Alan Modra <amodra@gmail.com>
333 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
334 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
335 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
336 support disjointed BAT.
337 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
338 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
339 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
341 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
342 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
344 * i386-gen.c (adjust_broadcast_modifier): New function.
345 (process_i386_opcode_modifier): Add an argument for operands.
346 Adjust the Broadcast value based on operands.
347 (output_i386_opcode): Pass operand_types to
348 process_i386_opcode_modifier.
349 (process_i386_opcodes): Pass NULL as operands to
350 process_i386_opcode_modifier.
351 * i386-opc.h (BYTE_BROADCAST): New.
352 (WORD_BROADCAST): Likewise.
353 (DWORD_BROADCAST): Likewise.
354 (QWORD_BROADCAST): Likewise.
355 (i386_opcode_modifier): Expand broadcast to 3 bits.
356 * i386-tbl.h: Regenerated.
358 2018-07-24 Alan Modra <amodra@gmail.com>
361 * or1k-desc.h: Regenerate.
363 2018-07-24 Jan Beulich <jbeulich@suse.com>
365 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
366 vcvtusi2ss, and vcvtusi2sd.
367 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
368 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
369 * i386-tbl.h: Re-generate.
371 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
373 * arc-opc.c (extract_w6): Fix extending the sign.
375 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
377 * arc-tbl.h (vewt): Allow it for ARC EM family.
379 2018-07-23 Alan Modra <amodra@gmail.com>
382 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
383 opcode variants for mtspr/mfspr encodings.
385 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
386 Maciej W. Rozycki <macro@mips.com>
388 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
389 loongson3a descriptors.
390 (parse_mips_ase_option): Handle -M loongson-mmi option.
391 (print_mips_disassembler_options): Document -M loongson-mmi.
392 * mips-opc.c (LMMI): New macro.
393 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
396 2018-07-19 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
399 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
400 IgnoreSize and [XYZ]MMword where applicable.
401 * i386-tbl.h: Re-generate.
403 2018-07-19 Jan Beulich <jbeulich@suse.com>
405 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
406 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
407 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
408 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
409 * i386-tbl.h: Re-generate.
411 2018-07-19 Jan Beulich <jbeulich@suse.com>
413 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
414 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
415 VPCLMULQDQ templates into their respective AVX512VL counterparts
416 where possible, using Disp8ShiftVL and CheckRegSize instead of
417 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
418 * i386-tbl.h: Re-generate.
420 2018-07-19 Jan Beulich <jbeulich@suse.com>
422 * i386-opc.tbl: Fold AVX512DQ templates into their respective
423 AVX512VL counterparts where possible, using Disp8ShiftVL and
424 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
425 IgnoreSize) as appropriate.
426 * i386-tbl.h: Re-generate.
428 2018-07-19 Jan Beulich <jbeulich@suse.com>
430 * i386-opc.tbl: Fold AVX512BW templates into their respective
431 AVX512VL counterparts where possible, using Disp8ShiftVL and
432 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
433 IgnoreSize) as appropriate.
434 * i386-tbl.h: Re-generate.
436 2018-07-19 Jan Beulich <jbeulich@suse.com>
438 * i386-opc.tbl: Fold AVX512CD templates into their respective
439 AVX512VL counterparts where possible, using Disp8ShiftVL and
440 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
441 IgnoreSize) as appropriate.
442 * i386-tbl.h: Re-generate.
444 2018-07-19 Jan Beulich <jbeulich@suse.com>
446 * i386-opc.h (DISP8_SHIFT_VL): New.
447 * i386-opc.tbl (Disp8ShiftVL): Define.
448 (various): Fold AVX512VL templates into their respective
449 AVX512F counterparts where possible, using Disp8ShiftVL and
450 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
451 IgnoreSize) as appropriate.
452 * i386-tbl.h: Re-generate.
454 2018-07-19 Jan Beulich <jbeulich@suse.com>
456 * Makefile.am: Change dependencies and rule for
457 $(srcdir)/i386-init.h.
458 * Makefile.in: Re-generate.
459 * i386-gen.c (process_i386_opcodes): New local variable
460 "marker". Drop opening of input file. Recognize marker and line
462 * i386-opc.tbl (OPCODE_I386_H): Define.
463 (i386-opc.h): Include it.
466 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
469 * i386-opc.h (Byte): Update comments.
478 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
480 * i386-tbl.h: Regenerated.
482 2018-07-12 Sudakshina Das <sudi.das@arm.com>
484 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
485 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
486 * aarch64-asm-2.c: Regenerate.
487 * aarch64-dis-2.c: Regenerate.
488 * aarch64-opc-2.c: Regenerate.
490 2018-07-12 Tamar Christina <tamar.christina@arm.com>
493 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
494 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
495 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
496 sqdmulh, sqrdmulh): Use Em16.
498 2018-07-11 Sudakshina Das <sudi.das@arm.com>
500 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
501 csdb together with them.
502 (thumb32_opcodes): Likewise.
504 2018-07-11 Jan Beulich <jbeulich@suse.com>
506 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
507 requiring 32-bit registers as operands 2 and 3. Improve
509 (mwait, mwaitx): Fold templates. Improve comments.
510 OPERAND_TYPE_INOUTPORTREG.
511 * i386-tbl.h: Re-generate.
513 2018-07-11 Jan Beulich <jbeulich@suse.com>
515 * i386-gen.c (operand_type_init): Remove
516 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
517 OPERAND_TYPE_INOUTPORTREG.
518 * i386-init.h: Re-generate.
520 2018-07-11 Jan Beulich <jbeulich@suse.com>
522 * i386-opc.tbl (wrssd, wrussd): Add Dword.
523 (wrssq, wrussq): Add Qword.
524 * i386-tbl.h: Re-generate.
526 2018-07-11 Jan Beulich <jbeulich@suse.com>
528 * i386-opc.h: Rename OTMax to OTNum.
529 (OTNumOfUints): Adjust calculation.
530 (OTUnused): Directly alias to OTNum.
532 2018-07-09 Maciej W. Rozycki <macro@mips.com>
534 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
536 (lea_reg_xys): Likewise.
537 (print_insn_loop_primitive): Rename `reg' local variable to
540 2018-07-06 Tamar Christina <tamar.christina@arm.com>
543 * aarch64-tbl.h (ldarh): Fix disassembly mask.
545 2018-07-06 Tamar Christina <tamar.christina@arm.com>
548 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
549 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
551 2018-07-02 Maciej W. Rozycki <macro@mips.com>
554 * mips-dis.c (mips_option_arg_t): New enumeration.
555 (mips_options): New variable.
556 (disassembler_options_mips): New function.
557 (print_mips_disassembler_options): Reimplement in terms of
558 `disassembler_options_mips'.
559 * arm-dis.c (disassembler_options_arm): Adapt to using the
560 `disasm_options_and_args_t' structure.
561 * ppc-dis.c (disassembler_options_powerpc): Likewise.
562 * s390-dis.c (disassembler_options_s390): Likewise.
564 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
566 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
568 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
569 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
570 * testsuite/ld-arm/tls-longplt.d: Likewise.
572 2018-06-29 Tamar Christina <tamar.christina@arm.com>
575 * aarch64-asm-2.c: Regenerate.
576 * aarch64-dis-2.c: Likewise.
577 * aarch64-opc-2.c: Likewise.
578 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
579 * aarch64-opc.c (operand_general_constraint_met_p,
580 aarch64_print_operand): Likewise.
581 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
582 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
584 (AARCH64_OPERANDS): Add Em2.
586 2018-06-26 Nick Clifton <nickc@redhat.com>
588 * po/uk.po: Updated Ukranian translation.
589 * po/de.po: Updated German translation.
590 * po/pt_BR.po: Updated Brazilian Portuguese translation.
592 2018-06-26 Nick Clifton <nickc@redhat.com>
594 * nfp-dis.c: Fix spelling mistake.
596 2018-06-24 Nick Clifton <nickc@redhat.com>
598 * configure: Regenerate.
599 * po/opcodes.pot: Regenerate.
601 2018-06-24 Nick Clifton <nickc@redhat.com>
605 2018-06-19 Tamar Christina <tamar.christina@arm.com>
607 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
608 * aarch64-asm-2.c: Regenerate.
609 * aarch64-dis-2.c: Likewise.
611 2018-06-21 Maciej W. Rozycki <macro@mips.com>
613 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
614 `-M ginv' option description.
616 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
619 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
622 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
624 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
625 * configure.ac: Remove AC_PREREQ.
626 * Makefile.in: Re-generate.
627 * aclocal.m4: Re-generate.
628 * configure: Re-generate.
630 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
632 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
633 mips64r6 descriptors.
634 (parse_mips_ase_option): Handle -Mginv option.
635 (print_mips_disassembler_options): Document -Mginv.
636 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
638 (mips_opcodes): Define ginvi and ginvt.
640 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
641 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
643 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
644 * mips-opc.c (CRC, CRC64): New macros.
645 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
646 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
649 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
652 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
653 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
655 2018-06-06 Alan Modra <amodra@gmail.com>
657 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
658 setjmp. Move init for some other vars later too.
660 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
662 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
663 (dis_private): Add new fields for property section tracking.
664 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
665 (xtensa_instruction_fits): New functions.
666 (fetch_data): Bump minimal fetch size to 4.
667 (print_insn_xtensa): Make struct dis_private static.
668 Load and prepare property table on section change.
669 Don't disassemble literals. Don't disassemble instructions that
670 cross property table boundaries.
672 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
674 * configure: Regenerated.
676 2018-06-01 Jan Beulich <jbeulich@suse.com>
678 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
679 * i386-tbl.h: Re-generate.
681 2018-06-01 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.tbl (sldt, str): Add NoRex64.
684 * i386-tbl.h: Re-generate.
686 2018-06-01 Jan Beulich <jbeulich@suse.com>
688 * i386-opc.tbl (invpcid): Add Oword.
689 * i386-tbl.h: Re-generate.
691 2018-06-01 Alan Modra <amodra@gmail.com>
693 * sysdep.h (_bfd_error_handler): Don't declare.
694 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
695 * rl78-decode.opc: Likewise.
696 * msp430-decode.c: Regenerate.
697 * rl78-decode.c: Regenerate.
699 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
701 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
702 * i386-init.h : Regenerated.
704 2018-05-25 Alan Modra <amodra@gmail.com>
706 * Makefile.in: Regenerate.
707 * po/POTFILES.in: Regenerate.
709 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
711 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
712 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
713 (insert_bab, extract_bab, insert_btab, extract_btab,
714 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
715 (BAT, BBA VBA RBS XB6S): Delete macros.
716 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
717 (BB, BD, RBX, XC6): Update for new macros.
718 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
719 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
720 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
721 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
723 2018-05-18 John Darrington <john@darrington.wattle.id.au>
725 * Makefile.am: Add support for s12z architecture.
726 * configure.ac: Likewise.
727 * disassemble.c: Likewise.
728 * disassemble.h: Likewise.
729 * Makefile.in: Regenerate.
730 * configure: Regenerate.
731 * s12z-dis.c: New file.
734 2018-05-18 Alan Modra <amodra@gmail.com>
736 * nfp-dis.c: Don't #include libbfd.h.
737 (init_nfp3200_priv): Use bfd_get_section_contents.
738 (nit_nfp6000_mecsr_sec): Likewise.
740 2018-05-17 Nick Clifton <nickc@redhat.com>
742 * po/zh_CN.po: Updated simplified Chinese translation.
744 2018-05-16 Tamar Christina <tamar.christina@arm.com>
747 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
748 * aarch64-dis-2.c: Regenerate.
750 2018-05-15 Tamar Christina <tamar.christina@arm.com>
753 * aarch64-asm.c (opintl.h): Include.
754 (aarch64_ins_sysreg): Enforce read/write constraints.
755 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
756 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
757 (F_REG_READ, F_REG_WRITE): New.
758 * aarch64-opc.c (aarch64_print_operand): Generate notes for
760 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
761 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
762 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
763 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
764 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
765 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
766 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
767 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
768 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
769 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
770 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
771 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
772 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
773 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
774 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
775 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
776 msr (F_SYS_WRITE), mrs (F_SYS_READ).
778 2018-05-15 Tamar Christina <tamar.christina@arm.com>
781 * aarch64-dis.c (no_notes: New.
782 (parse_aarch64_dis_option): Support notes.
783 (aarch64_decode_insn, print_operands): Likewise.
784 (print_aarch64_disassembler_options): Document notes.
785 * aarch64-opc.c (aarch64_print_operand): Support notes.
787 2018-05-15 Tamar Christina <tamar.christina@arm.com>
790 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
791 and take error struct.
792 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
793 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
794 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
795 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
796 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
797 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
798 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
799 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
800 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
801 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
802 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
803 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
804 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
805 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
806 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
807 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
808 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
809 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
810 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
811 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
812 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
813 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
814 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
815 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
816 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
817 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
818 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
819 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
820 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
821 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
822 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
823 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
824 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
825 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
826 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
827 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
828 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
829 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
830 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
831 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
832 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
833 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
834 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
835 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
836 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
837 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
838 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
839 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
840 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
841 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
842 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
843 (determine_disassembling_preference, aarch64_decode_insn,
844 print_insn_aarch64_word, print_insn_data): Take errors struct.
845 (print_insn_aarch64): Use errors.
846 * aarch64-asm-2.c: Regenerate.
847 * aarch64-dis-2.c: Regenerate.
848 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
849 boolean in aarch64_insert_operan.
850 (print_operand_extractor): Likewise.
851 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
853 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
855 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
857 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
859 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
861 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
863 * cr16-opc.c (cr16_instruction): Comment typo fix.
864 * hppa-dis.c (print_insn_hppa): Likewise.
866 2018-05-08 Jim Wilson <jimw@sifive.com>
868 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
869 (match_c_slli64, match_srxi_as_c_srxi): New.
870 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
871 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
872 <c.slli, c.srli, c.srai>: Use match_s_slli.
873 <c.slli64, c.srli64, c.srai64>: New.
875 2018-05-08 Alan Modra <amodra@gmail.com>
877 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
878 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
879 partition opcode space for index lookup.
881 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
883 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
884 <insn_length>: ...with this. Update usage.
885 Remove duplicate call to *info->memory_error_func.
887 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
888 H.J. Lu <hongjiu.lu@intel.com>
890 * i386-dis.c (Gva): New.
891 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
892 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
893 (prefix_table): New instructions (see prefix above).
894 (mod_table): New instructions (see prefix above).
895 (OP_G): Handle va_mode.
896 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
898 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
899 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
900 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
901 * i386-opc.tbl: Add movidir{i,64b}.
902 * i386-init.h: Regenerated.
903 * i386-tbl.h: Likewise.
905 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
907 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
909 * i386-opc.h (AddrPrefixOp0): Renamed to ...
910 (AddrPrefixOpReg): This.
911 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
912 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
914 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
916 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
917 (vle_num_opcodes): Likewise.
918 (spe2_num_opcodes): Likewise.
919 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
921 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
922 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
925 2018-05-01 Tamar Christina <tamar.christina@arm.com>
927 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
929 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
931 Makefile.am: Added nfp-dis.c.
932 configure.ac: Added bfd_nfp_arch.
933 disassemble.h: Added print_insn_nfp prototype.
934 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
935 nfp-dis.c: New, for NFP support.
936 po/POTFILES.in: Added nfp-dis.c to the list.
937 Makefile.in: Regenerate.
938 configure: Regenerate.
940 2018-04-26 Jan Beulich <jbeulich@suse.com>
942 * i386-opc.tbl: Fold various non-memory operand AVX512VL
943 templates into their base ones.
944 * i386-tlb.h: Re-generate.
946 2018-04-26 Jan Beulich <jbeulich@suse.com>
948 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
949 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
950 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
951 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
952 * i386-init.h: Re-generate.
954 2018-04-26 Jan Beulich <jbeulich@suse.com>
956 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
957 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
958 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
959 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
961 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
963 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
965 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
966 cpuregzmm, and cpuregmask.
967 * i386-init.h: Re-generate.
968 * i386-tbl.h: Re-generate.
970 2018-04-26 Jan Beulich <jbeulich@suse.com>
972 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
973 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
974 * i386-init.h: Re-generate.
976 2018-04-26 Jan Beulich <jbeulich@suse.com>
978 * i386-gen.c (VexImmExt): Delete.
979 * i386-opc.h (VexImmExt, veximmext): Delete.
980 * i386-opc.tbl: Drop all VexImmExt uses.
981 * i386-tlb.h: Re-generate.
983 2018-04-25 Jan Beulich <jbeulich@suse.com>
985 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
987 * i386-tlb.h: Re-generate.
989 2018-04-25 Tamar Christina <tamar.christina@arm.com>
991 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
993 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
995 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
997 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
998 (cpu_flags): Add CpuCLDEMOTE.
999 * i386-init.h: Regenerate.
1000 * i386-opc.h (enum): Add CpuCLDEMOTE,
1001 (i386_cpu_flags): Add cpucldemote.
1002 * i386-opc.tbl: Add cldemote.
1003 * i386-tbl.h: Regenerate.
1005 2018-04-16 Alan Modra <amodra@gmail.com>
1007 * Makefile.am: Remove sh5 and sh64 support.
1008 * configure.ac: Likewise.
1009 * disassemble.c: Likewise.
1010 * disassemble.h: Likewise.
1011 * sh-dis.c: Likewise.
1012 * sh64-dis.c: Delete.
1013 * sh64-opc.c: Delete.
1014 * sh64-opc.h: Delete.
1015 * Makefile.in: Regenerate.
1016 * configure: Regenerate.
1017 * po/POTFILES.in: Regenerate.
1019 2018-04-16 Alan Modra <amodra@gmail.com>
1021 * Makefile.am: Remove w65 support.
1022 * configure.ac: Likewise.
1023 * disassemble.c: Likewise.
1024 * disassemble.h: Likewise.
1025 * w65-dis.c: Delete.
1026 * w65-opc.h: Delete.
1027 * Makefile.in: Regenerate.
1028 * configure: Regenerate.
1029 * po/POTFILES.in: Regenerate.
1031 2018-04-16 Alan Modra <amodra@gmail.com>
1033 * configure.ac: Remove we32k support.
1034 * configure: Regenerate.
1036 2018-04-16 Alan Modra <amodra@gmail.com>
1038 * Makefile.am: Remove m88k support.
1039 * configure.ac: Likewise.
1040 * disassemble.c: Likewise.
1041 * disassemble.h: Likewise.
1042 * m88k-dis.c: Delete.
1043 * Makefile.in: Regenerate.
1044 * configure: Regenerate.
1045 * po/POTFILES.in: Regenerate.
1047 2018-04-16 Alan Modra <amodra@gmail.com>
1049 * Makefile.am: Remove i370 support.
1050 * configure.ac: Likewise.
1051 * disassemble.c: Likewise.
1052 * disassemble.h: Likewise.
1053 * i370-dis.c: Delete.
1054 * i370-opc.c: Delete.
1055 * Makefile.in: Regenerate.
1056 * configure: Regenerate.
1057 * po/POTFILES.in: Regenerate.
1059 2018-04-16 Alan Modra <amodra@gmail.com>
1061 * Makefile.am: Remove h8500 support.
1062 * configure.ac: Likewise.
1063 * disassemble.c: Likewise.
1064 * disassemble.h: Likewise.
1065 * h8500-dis.c: Delete.
1066 * h8500-opc.h: Delete.
1067 * Makefile.in: Regenerate.
1068 * configure: Regenerate.
1069 * po/POTFILES.in: Regenerate.
1071 2018-04-16 Alan Modra <amodra@gmail.com>
1073 * configure.ac: Remove tahoe support.
1074 * configure: Regenerate.
1076 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1078 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1080 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1082 * i386-tbl.h: Regenerated.
1084 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1086 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1087 PREFIX_MOD_1_0FAE_REG_6.
1089 (OP_E_register): Use va_mode.
1090 * i386-dis-evex.h (prefix_table):
1091 New instructions (see prefixes above).
1092 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1093 (cpu_flags): Likewise.
1094 * i386-opc.h (enum): Likewise.
1095 (i386_cpu_flags): Likewise.
1096 * i386-opc.tbl: Add umonitor, umwait, tpause.
1097 * i386-init.h: Regenerate.
1098 * i386-tbl.h: Likewise.
1100 2018-04-11 Alan Modra <amodra@gmail.com>
1102 * opcodes/i860-dis.c: Delete.
1103 * opcodes/i960-dis.c: Delete.
1104 * Makefile.am: Remove i860 and i960 support.
1105 * configure.ac: Likewise.
1106 * disassemble.c: Likewise.
1107 * disassemble.h: Likewise.
1108 * Makefile.in: Regenerate.
1109 * configure: Regenerate.
1110 * po/POTFILES.in: Regenerate.
1112 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1117 (print_insn): Clear vex instead of vex.evex.
1119 2018-04-04 Nick Clifton <nickc@redhat.com>
1121 * po/es.po: Updated Spanish translation.
1123 2018-03-28 Jan Beulich <jbeulich@suse.com>
1125 * i386-gen.c (opcode_modifiers): Delete VecESize.
1126 * i386-opc.h (VecESize): Delete.
1127 (struct i386_opcode_modifier): Delete vecesize.
1128 * i386-opc.tbl: Drop VecESize.
1129 * i386-tlb.h: Re-generate.
1131 2018-03-28 Jan Beulich <jbeulich@suse.com>
1133 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1134 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1135 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1136 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1137 * i386-tlb.h: Re-generate.
1139 2018-03-28 Jan Beulich <jbeulich@suse.com>
1141 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1143 * i386-tlb.h: Re-generate.
1145 2018-03-28 Jan Beulich <jbeulich@suse.com>
1147 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1148 (vex_len_table): Drop Y for vcvt*2si.
1149 (putop): Replace plain 'Y' handling by abort().
1151 2018-03-28 Nick Clifton <nickc@redhat.com>
1154 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1155 instructions with only a base address register.
1156 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1157 handle AARHC64_OPND_SVE_ADDR_R.
1158 (aarch64_print_operand): Likewise.
1159 * aarch64-asm-2.c: Regenerate.
1160 * aarch64_dis-2.c: Regenerate.
1161 * aarch64-opc-2.c: Regenerate.
1163 2018-03-22 Jan Beulich <jbeulich@suse.com>
1165 * i386-opc.tbl: Drop VecESize from register only insn forms and
1166 memory forms not allowing broadcast.
1167 * i386-tlb.h: Re-generate.
1169 2018-03-22 Jan Beulich <jbeulich@suse.com>
1171 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1172 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1173 sha256*): Drop Disp<N>.
1175 2018-03-22 Jan Beulich <jbeulich@suse.com>
1177 * i386-dis.c (EbndS, bnd_swap_mode): New.
1178 (prefix_table): Use EbndS.
1179 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1180 * i386-opc.tbl (bndmov): Move misplaced Load.
1181 * i386-tlb.h: Re-generate.
1183 2018-03-22 Jan Beulich <jbeulich@suse.com>
1185 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1186 templates allowing memory operands and folded ones for register
1188 * i386-tlb.h: Re-generate.
1190 2018-03-22 Jan Beulich <jbeulich@suse.com>
1192 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1193 256-bit templates. Drop redundant leftover Disp<N>.
1194 * i386-tlb.h: Re-generate.
1196 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1198 * riscv-opc.c (riscv_insn_types): New.
1200 2018-03-13 Nick Clifton <nickc@redhat.com>
1202 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1204 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1206 * i386-opc.tbl: Add Optimize to clr.
1207 * i386-tbl.h: Regenerated.
1209 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1211 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1212 * i386-opc.h (OldGcc): Removed.
1213 (i386_opcode_modifier): Remove oldgcc.
1214 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1215 instructions for old (<= 2.8.1) versions of gcc.
1216 * i386-tbl.h: Regenerated.
1218 2018-03-08 Jan Beulich <jbeulich@suse.com>
1220 * i386-opc.h (EVEXDYN): New.
1221 * i386-opc.tbl: Fold various AVX512VL templates.
1222 * i386-tlb.h: Re-generate.
1224 2018-03-08 Jan Beulich <jbeulich@suse.com>
1226 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1227 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1228 vpexpandd, vpexpandq): Fold AFX512VF templates.
1229 * i386-tlb.h: Re-generate.
1231 2018-03-08 Jan Beulich <jbeulich@suse.com>
1233 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1234 Fold 128- and 256-bit VEX-encoded templates.
1235 * i386-tlb.h: Re-generate.
1237 2018-03-08 Jan Beulich <jbeulich@suse.com>
1239 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1240 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1241 vpexpandd, vpexpandq): Fold AVX512F templates.
1242 * i386-tlb.h: Re-generate.
1244 2018-03-08 Jan Beulich <jbeulich@suse.com>
1246 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1247 64-bit templates. Drop Disp<N>.
1248 * i386-tlb.h: Re-generate.
1250 2018-03-08 Jan Beulich <jbeulich@suse.com>
1252 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1253 and 256-bit templates.
1254 * i386-tlb.h: Re-generate.
1256 2018-03-08 Jan Beulich <jbeulich@suse.com>
1258 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1259 * i386-tlb.h: Re-generate.
1261 2018-03-08 Jan Beulich <jbeulich@suse.com>
1263 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1265 * i386-tlb.h: Re-generate.
1267 2018-03-08 Jan Beulich <jbeulich@suse.com>
1269 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1270 * i386-tlb.h: Re-generate.
1272 2018-03-08 Jan Beulich <jbeulich@suse.com>
1274 * i386-gen.c (opcode_modifiers): Delete FloatD.
1275 * i386-opc.h (FloatD): Delete.
1276 (struct i386_opcode_modifier): Delete floatd.
1277 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1279 * i386-tlb.h: Re-generate.
1281 2018-03-08 Jan Beulich <jbeulich@suse.com>
1283 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1285 2018-03-08 Jan Beulich <jbeulich@suse.com>
1287 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1288 * i386-tlb.h: Re-generate.
1290 2018-03-08 Jan Beulich <jbeulich@suse.com>
1292 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1294 * i386-tlb.h: Re-generate.
1296 2018-03-07 Alan Modra <amodra@gmail.com>
1298 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1300 * disassemble.h (print_insn_rs6000): Delete.
1301 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1302 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1303 (print_insn_rs6000): Delete.
1305 2018-03-03 Alan Modra <amodra@gmail.com>
1307 * sysdep.h (opcodes_error_handler): Define.
1308 (_bfd_error_handler): Declare.
1309 * Makefile.am: Remove stray #.
1310 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1312 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1313 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1314 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1315 opcodes_error_handler to print errors. Standardize error messages.
1316 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1317 and include opintl.h.
1318 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1319 * i386-gen.c: Standardize error messages.
1320 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1321 * Makefile.in: Regenerate.
1322 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1323 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1324 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1325 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1326 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1327 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1328 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1329 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1330 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1331 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1332 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1333 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1334 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1336 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1338 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1339 vpsub[bwdq] instructions.
1340 * i386-tbl.h: Regenerated.
1342 2018-03-01 Alan Modra <amodra@gmail.com>
1344 * configure.ac (ALL_LINGUAS): Sort.
1345 * configure: Regenerate.
1347 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1349 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1350 macro by assignements.
1352 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1355 * i386-gen.c (opcode_modifiers): Add Optimize.
1356 * i386-opc.h (Optimize): New enum.
1357 (i386_opcode_modifier): Add optimize.
1358 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1359 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1360 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1361 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1362 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1364 * i386-tbl.h: Regenerated.
1366 2018-02-26 Alan Modra <amodra@gmail.com>
1368 * crx-dis.c (getregliststring): Allocate a large enough buffer
1369 to silence false positive gcc8 warning.
1371 2018-02-22 Shea Levy <shea@shealevy.com>
1373 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1375 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1377 * i386-opc.tbl: Add {rex},
1378 * i386-tbl.h: Regenerated.
1380 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1382 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1383 (mips16_opcodes): Replace `M' with `m' for "restore".
1385 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1387 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1389 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1391 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1392 variable to `function_index'.
1394 2018-02-13 Nick Clifton <nickc@redhat.com>
1397 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1398 about truncation of printing.
1400 2018-02-12 Henry Wong <henry@stuffedcow.net>
1402 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1404 2018-02-05 Nick Clifton <nickc@redhat.com>
1406 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1408 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1410 * i386-dis.c (enum): Add pconfig.
1411 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1412 (cpu_flags): Add CpuPCONFIG.
1413 * i386-opc.h (enum): Add CpuPCONFIG.
1414 (i386_cpu_flags): Add cpupconfig.
1415 * i386-opc.tbl: Add PCONFIG instruction.
1416 * i386-init.h: Regenerate.
1417 * i386-tbl.h: Likewise.
1419 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1421 * i386-dis.c (enum): Add PREFIX_0F09.
1422 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1423 (cpu_flags): Add CpuWBNOINVD.
1424 * i386-opc.h (enum): Add CpuWBNOINVD.
1425 (i386_cpu_flags): Add cpuwbnoinvd.
1426 * i386-opc.tbl: Add WBNOINVD instruction.
1427 * i386-init.h: Regenerate.
1428 * i386-tbl.h: Likewise.
1430 2018-01-17 Jim Wilson <jimw@sifive.com>
1432 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1434 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1436 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1437 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1438 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1439 (cpu_flags): Add CpuIBT, CpuSHSTK.
1440 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1441 (i386_cpu_flags): Add cpuibt, cpushstk.
1442 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1443 * i386-init.h: Regenerate.
1444 * i386-tbl.h: Likewise.
1446 2018-01-16 Nick Clifton <nickc@redhat.com>
1448 * po/pt_BR.po: Updated Brazilian Portugese translation.
1449 * po/de.po: Updated German translation.
1451 2018-01-15 Jim Wilson <jimw@sifive.com>
1453 * riscv-opc.c (match_c_nop): New.
1454 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1456 2018-01-15 Nick Clifton <nickc@redhat.com>
1458 * po/uk.po: Updated Ukranian translation.
1460 2018-01-13 Nick Clifton <nickc@redhat.com>
1462 * po/opcodes.pot: Regenerated.
1464 2018-01-13 Nick Clifton <nickc@redhat.com>
1466 * configure: Regenerate.
1468 2018-01-13 Nick Clifton <nickc@redhat.com>
1470 2.30 branch created.
1472 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1474 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1475 * i386-tbl.h: Regenerate.
1477 2018-01-10 Jan Beulich <jbeulich@suse.com>
1479 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1480 * i386-tbl.h: Re-generate.
1482 2018-01-10 Jan Beulich <jbeulich@suse.com>
1484 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1485 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1486 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1487 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1488 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1489 Disp8MemShift of AVX512VL forms.
1490 * i386-tbl.h: Re-generate.
1492 2018-01-09 Jim Wilson <jimw@sifive.com>
1494 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1495 then the hi_addr value is zero.
1497 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1499 * arm-dis.c (arm_opcodes): Add csdb.
1500 (thumb32_opcodes): Add csdb.
1502 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1504 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1505 * aarch64-asm-2.c: Regenerate.
1506 * aarch64-dis-2.c: Regenerate.
1507 * aarch64-opc-2.c: Regenerate.
1509 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1512 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1513 Remove AVX512 vmovd with 64-bit operands.
1514 * i386-tbl.h: Regenerated.
1516 2018-01-05 Jim Wilson <jimw@sifive.com>
1518 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1521 2018-01-03 Alan Modra <amodra@gmail.com>
1523 Update year range in copyright notice of all files.
1525 2018-01-02 Jan Beulich <jbeulich@suse.com>
1527 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1528 and OPERAND_TYPE_REGZMM entries.
1530 For older changes see ChangeLog-2017
1532 Copyright (C) 2018 Free Software Foundation, Inc.
1534 Copying and distribution of this file, with or without modification,
1535 are permitted in any medium without royalty provided the copyright
1536 notice and this notice are preserved.
1542 version-control: never