1 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
3 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
4 "sldt", "str" and "smsw".
6 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
9 * i386-dis.c (GRP11_C6): NEW.
17 (GRPPADLCK1): Likewise.
18 (GRPPADLCK2): Likewise.
19 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
21 (grps): Add entries for GRP11_C6 and GRP11_C7.
23 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
24 Michael Meissner <michael.meissner@amd.com>
26 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
27 support for amdfam10 SSE4a/ABM instructions. Modify all
28 initializer macros to have additional arguments. Disallow REP
29 prefix for non-string instructions.
33 2006-07-05 Julian Brown <julian@codesourcery.com>
35 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
37 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
39 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
40 (twobyte_has_modrm): Set 1 for 0x1f.
42 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
44 * i386-dis.c (NOP_Fixup): Removed.
46 (NOP_Fixup2): Likewise.
47 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
49 2006-06-12 Julian Brown <julian@codesourcery.com>
51 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
54 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
56 * i386.c (GRP10): Renamed to ...
58 (GRP11): Renamed to ...
60 (GRP12): Renamed to ...
62 (GRP13): Renamed to ...
64 (GRP14): Renamed to ...
66 (dis386_twobyte): Updated.
69 2006-06-09 Nick Clifton <nickc@redhat.com>
71 * po/fi.po: Updated Finnish translation.
73 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
75 * po/Make-in (pdf, ps): New dummy targets.
77 2006-06-06 Paul Brook <paul@codesourcery.com>
79 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
81 (neon_opcodes): Add conditional execution specifiers.
82 (thumb_opcodes): Ditto.
83 (thumb32_opcodes): Ditto.
84 (arm_conditional): Change 0xe to "al" and add "" to end.
85 (ifthen_state, ifthen_next_state, ifthen_address): New.
86 (IFTHEN_COND): Define.
87 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
88 (print_insn_arm): Change %c to use new values of arm_conditional.
89 (print_insn_thumb16): Print thumb conditions. Add %I.
90 (print_insn_thumb32): Print thumb conditions.
91 (find_ifthen_state): New function.
92 (print_insn): Track IT block state.
94 2006-06-06 Ben Elliston <bje@au.ibm.com>
95 Anton Blanchard <anton@samba.org>
96 Peter Bergner <bergner@vnet.ibm.com>
98 * ppc-dis.c (powerpc_dialect): Handle power6 option.
99 (print_ppc_disassembler_options): Mention power6.
101 2006-06-06 Thiemo Seufer <ths@mips.com>
102 Chao-ying Fu <fu@mips.com>
104 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
105 * mips-opc.c: Add DSP64 instructions.
107 2006-06-06 Alan Modra <amodra@bigpond.net.au>
109 * m68hc11-dis.c (print_insn): Warning fix.
111 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
113 * po/Make-in (top_builddir): Define.
115 2006-06-05 Alan Modra <amodra@bigpond.net.au>
117 * Makefile.am: Run "make dep-am".
118 * Makefile.in: Regenerate.
119 * config.in: Regenerate.
121 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
123 * Makefile.am (INCLUDES): Use @INCINTL@.
124 * acinclude.m4: Include new gettext macros.
125 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
126 Remove local code for po/Makefile.
127 * Makefile.in, aclocal.m4, configure: Regenerated.
129 2006-05-30 Nick Clifton <nickc@redhat.com>
131 * po/es.po: Updated Spanish translation.
133 2006-05-25 Richard Sandiford <richard@codesourcery.com>
135 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
136 and fmovem entries. Put register list entries before immediate
137 mask entries. Use "l" rather than "L" in the fmovem entries.
138 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
140 (m68k_scan_mask): New function, split out from...
141 (print_insn_m68k): ...here. If no architecture has been set,
142 first try printing an m680x0 instruction, then try a Coldfire one.
144 2006-05-24 Nick Clifton <nickc@redhat.com>
146 * po/ga.po: Updated Irish translation.
148 2006-05-22 Nick Clifton <nickc@redhat.com>
150 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
152 2006-05-22 Nick Clifton <nickc@redhat.com>
154 * po/nl.po: Updated translation.
156 2006-05-18 Alan Modra <amodra@bigpond.net.au>
158 * avr-dis.c: Formatting fix.
160 2006-05-14 Thiemo Seufer <ths@mips.com>
162 * mips16-opc.c (I1, I32, I64): New shortcut defines.
163 (mips16_opcodes): Change membership of instructions to their
166 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
168 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
170 2006-05-05 Julian Brown <julian@codesourcery.com>
172 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
175 2006-05-05 Thiemo Seufer <ths@mips.com>
176 David Ung <davidu@mips.com>
178 * mips-opc.c: Add macro for cache instruction.
180 2006-05-04 Thiemo Seufer <ths@mips.com>
181 Nigel Stephens <nigel@mips.com>
182 David Ung <davidu@mips.com>
184 * mips-dis.c (mips_arch_choices): Add smartmips instruction
185 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
186 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
188 * mips-opc.c: fix random typos in comments.
189 (INSN_SMARTMIPS): New defines.
190 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
191 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
192 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
193 FP_S and FP_D flags to denote single and double register
194 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
195 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
196 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
197 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
199 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
201 2006-05-03 Thiemo Seufer <ths@mips.com>
203 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
205 2006-05-02 Thiemo Seufer <ths@mips.com>
206 Nigel Stephens <nigel@mips.com>
207 David Ung <davidu@mips.com>
209 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
210 (print_mips16_insn_arg): Force mips16 to odd addresses.
212 2006-04-30 Thiemo Seufer <ths@mips.com>
213 David Ung <davidu@mips.com>
215 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
217 * mips-dis.c (print_insn_args): Adds udi argument handling.
219 2006-04-28 James E Wilson <wilson@specifix.com>
221 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
224 2006-04-28 Thiemo Seufer <ths@mips.com>
225 David Ung <davidu@mips.com>
226 Nigel Stephens <nigel@mips.com>
228 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
231 2006-04-28 Thiemo Seufer <ths@mips.com>
232 Nigel Stephens <nigel@mips.com>
233 David Ung <davidu@mips.com>
235 * mips-dis.c (print_insn_args): Add mips_opcode argument.
236 (print_insn_mips): Adjust print_insn_args call.
238 2006-04-28 Thiemo Seufer <ths@mips.com>
239 Nigel Stephens <nigel@mips.com>
241 * mips-dis.c (print_insn_args): Print $fcc only for FP
242 instructions, use $cc elsewise.
244 2006-04-28 Thiemo Seufer <ths@mips.com>
245 Nigel Stephens <nigel@mips.com>
247 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
248 Map MIPS16 registers to O32 names.
249 (print_mips16_insn_arg): Use mips16_reg_names.
251 2006-04-26 Julian Brown <julian@codesourcery.com>
253 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
256 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
257 Julian Brown <julian@codesourcery.com>
259 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
260 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
261 Add unified load/store instruction names.
262 (neon_opcode_table): New.
263 (arm_opcodes): Expand meaning of %<bitfield>['`?].
264 (arm_decode_bitfield): New.
265 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
266 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
267 (print_insn_neon): New.
268 (print_insn_arm): Adjust print_insn_coprocessor call. Call
269 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
270 (print_insn_thumb32): Likewise.
272 2006-04-19 Alan Modra <amodra@bigpond.net.au>
274 * Makefile.am: Run "make dep-am".
275 * Makefile.in: Regenerate.
277 2006-04-19 Alan Modra <amodra@bigpond.net.au>
279 * avr-dis.c (avr_operand): Warning fix.
281 * configure: Regenerate.
283 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
285 * po/POTFILES.in: Regenerated.
287 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
290 * avr-dis.c (avr_operand): Arrange for a comment to appear before
291 the symolic form of an address, so that the output of objdump -d
294 2006-04-10 DJ Delorie <dj@redhat.com>
296 * m32c-asm.c: Regenerate.
298 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
300 * Makefile.am: Add install-html target.
301 * Makefile.in: Regenerate.
303 2006-04-06 Nick Clifton <nickc@redhat.com>
305 * po/vi/po: Updated Vietnamese translation.
307 2006-03-31 Paul Koning <ni1d@arrl.net>
309 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
311 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
313 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
314 logic to identify halfword shifts.
316 2006-03-16 Paul Brook <paul@codesourcery.com>
318 * arm-dis.c (arm_opcodes): Rename swi to svc.
319 (thumb_opcodes): Ditto.
321 2006-03-13 DJ Delorie <dj@redhat.com>
323 * m32c-asm.c: Regenerate.
324 * m32c-desc.c: Likewise.
325 * m32c-desc.h: Likewise.
326 * m32c-dis.c: Likewise.
327 * m32c-ibld.c: Likewise.
328 * m32c-opc.c: Likewise.
329 * m32c-opc.h: Likewise.
331 2006-03-10 DJ Delorie <dj@redhat.com>
333 * m32c-desc.c: Regenerate with mul.l, mulu.l.
334 * m32c-opc.c: Likewise.
335 * m32c-opc.h: Likewise.
338 2006-03-09 Nick Clifton <nickc@redhat.com>
340 * po/sv.po: Updated Swedish translation.
342 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
345 * i386-dis.c (REP_Fixup): New function.
346 (AL): Remove duplicate.
351 (indirDXr): Likewise.
354 (dis386): Updated entries of ins, outs, movs, lods and stos.
356 2006-03-05 Nick Clifton <nickc@redhat.com>
358 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
359 signed 32-bit value into an unsigned 32-bit field when the host is
361 * fr30-ibld.c: Regenerate.
362 * frv-ibld.c: Regenerate.
363 * ip2k-ibld.c: Regenerate.
364 * iq2000-asm.c: Regenerate.
365 * iq2000-ibld.c: Regenerate.
366 * m32c-ibld.c: Regenerate.
367 * m32r-ibld.c: Regenerate.
368 * openrisc-ibld.c: Regenerate.
369 * xc16x-ibld.c: Regenerate.
370 * xstormy16-ibld.c: Regenerate.
372 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
374 * xc16x-asm.c: Regenerate.
375 * xc16x-dis.c: Regenerate.
377 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
379 * po/Make-in: Add html target.
381 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
383 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
384 Intel Merom New Instructions.
385 (THREE_BYTE_0): Likewise.
386 (THREE_BYTE_1): Likewise.
387 (three_byte_table): Likewise.
388 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
389 THREE_BYTE_1 for entry 0x3a.
390 (twobyte_has_modrm): Updated.
391 (twobyte_uses_SSE_prefix): Likewise.
392 (print_insn): Handle 3-byte opcodes used by Intel Merom New
395 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
397 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
398 (v9_hpriv_reg_names): New table.
399 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
400 New cases '$' and '%' for read/write hyperprivileged register.
401 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
402 window handling and rdhpr/wrhpr instructions.
404 2006-02-24 DJ Delorie <dj@redhat.com>
406 * m32c-desc.c: Regenerate with linker relaxation attributes.
407 * m32c-desc.h: Likewise.
408 * m32c-dis.c: Likewise.
409 * m32c-opc.c: Likewise.
411 2006-02-24 Paul Brook <paul@codesourcery.com>
413 * arm-dis.c (arm_opcodes): Add V7 instructions.
414 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
415 (print_arm_address): New function.
416 (print_insn_arm): Use it. Add 'P' and 'U' cases.
417 (psr_name): New function.
418 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
420 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
422 * ia64-opc-i.c (bXc): New.
424 (OpX2TaTbYaXcC): Likewise.
427 (ia64_opcodes_i): Add instructions for tf.
429 * ia64-opc.h (IMMU5b): New.
431 * ia64-asmtab.c: Regenerated.
433 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
435 * ia64-gen.c: Update copyright years.
436 * ia64-opc-b.c: Likewise.
438 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
440 * ia64-gen.c (lookup_regindex): Handle ".vm".
441 (print_dependency_table): Handle '\"'.
443 * ia64-ic.tbl: Updated from SDM 2.2.
444 * ia64-raw.tbl: Likewise.
445 * ia64-waw.tbl: Likewise.
446 * ia64-asmtab.c: Regenerated.
448 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
450 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
451 Anil Paranjape <anilp1@kpitcummins.com>
452 Shilin Shakti <shilins@kpitcummins.com>
454 * xc16x-desc.h: New file
455 * xc16x-desc.c: New file
456 * xc16x-opc.h: New file
457 * xc16x-opc.c: New file
458 * xc16x-ibld.c: New file
459 * xc16x-asm.c: New file
460 * xc16x-dis.c: New file
461 * Makefile.am: Entries for xc16x
462 * Makefile.in: Regenerate
463 * cofigure.in: Add xc16x target information.
464 * configure: Regenerate.
465 * disassemble.c: Add xc16x target information.
467 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
469 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
472 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
474 * i386-dis.c ('Z'): Add a new macro.
475 (dis386_twobyte): Use "movZ" for control register moves.
477 2006-02-10 Nick Clifton <nickc@redhat.com>
479 * iq2000-asm.c: Regenerate.
481 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
483 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
485 2006-01-26 David Ung <davidu@mips.com>
487 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
488 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
489 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
490 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
491 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
493 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
495 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
496 ld_d_r, pref_xd_cb): Use signed char to hold data to be
498 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
499 buffer overflows when disassembling instructions like
501 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
502 operand, if the offset is negative.
504 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
506 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
507 unsigned char to hold data to be disassembled.
509 2006-01-17 Andreas Schwab <schwab@suse.de>
512 * disassemble.c (disassemble_init_for_target): Set
513 disassembler_needs_relocs for bfd_arch_arm.
515 2006-01-16 Paul Brook <paul@codesourcery.com>
517 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
518 f?add?, and f?sub? instructions.
520 2006-01-16 Nick Clifton <nickc@redhat.com>
522 * po/zh_CN.po: New Chinese (simplified) translation.
523 * configure.in (ALL_LINGUAS): Add "zh_CH".
524 * configure: Regenerate.
526 2006-01-05 Paul Brook <paul@codesourcery.com>
528 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
530 2006-01-06 DJ Delorie <dj@redhat.com>
532 * m32c-desc.c: Regenerate.
533 * m32c-opc.c: Regenerate.
534 * m32c-opc.h: Regenerate.
536 2006-01-03 DJ Delorie <dj@redhat.com>
538 * cgen-ibld.in (extract_normal): Avoid memory range errors.
539 * m32c-ibld.c: Regenerated.
541 For older changes see ChangeLog-2005
547 version-control: never