1 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
3 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
5 2016-12-01 Nick Clifton <nickc@redhat.com>
8 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
11 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
13 * arc-opc.c (insert_ra_chk): New function.
14 (insert_rb_chk): Likewise.
15 (insert_rad): Update text error message.
16 (insert_rcd): Likewise.
17 (insert_rhv2): Likewise.
18 (insert_r0): Likewise.
19 (insert_r1): Likewise.
20 (insert_r2): Likewise.
21 (insert_r3): Likewise.
22 (insert_sp): Likewise.
23 (insert_gp): Likewise.
24 (insert_pcl): Likewise.
25 (insert_blink): Likewise.
26 (insert_ilink1): Likewise.
27 (insert_ilink2): Likewise.
28 (insert_ras): Likewise.
29 (insert_rbs): Likewise.
30 (insert_rcs): Likewise.
31 (insert_simm3s): Likewise.
32 (insert_rrange): Likewise.
33 (insert_fpel): Likewise.
34 (insert_blinkel): Likewise.
35 (insert_pcel): Likewise.
36 (insert_nps_3bit_dst): Likewise.
37 (insert_nps_3bit_dst_short): Likewise.
38 (insert_nps_3bit_src2_short): Likewise.
39 (insert_nps_bitop_size_2b): Likewise.
40 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
45 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
46 * arc-tbl.h (div, divu): All instructions are DIVREM class.
47 Change first insn argument to check for LP_COUNT usage.
49 (ld, ldd): All instructions are LOAD class. Change first insn
50 argument to check for LP_COUNT usage.
51 (st, std): All instructions are STORE class.
52 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
53 Change first insn argument to check for LP_COUNT usage.
54 (mov): All instructions are MOVE class. Change first insn
55 argument to check for LP_COUNT usage.
57 2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
59 * arc-dis.c (is_compatible_p): Remove function.
60 (skip_this_opcode): Don't add any decoding class to decode list.
62 (find_format_from_table): Go through all opcodes, and warn if we
63 use a guessed mnemonic.
65 2016-11-28 Ramiro Polla <ramiro@hex-rays.com>
66 Amit Pawar <amit.pawar@amd.com>
69 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
72 2016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
74 * configure: Regenerate.
76 2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
78 * sparc-opc.c (HWS_V8): Definition moved from
79 gas/config/tc-sparc.c.
89 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
92 2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
94 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
97 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
99 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
100 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
101 (aarch64_opcode_table): Add fcmla and fcadd.
102 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
103 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
104 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
105 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
106 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
107 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
108 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
109 (operand_general_constraint_met_p): Rotate and index range check.
110 (aarch64_print_operand): Handle rotate operand.
111 * aarch64-asm-2.c: Regenerate.
112 * aarch64-dis-2.c: Likewise.
113 * aarch64-opc-2.c: Likewise.
115 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
117 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
118 * aarch64-asm-2.c: Regenerate.
119 * aarch64-dis-2.c: Regenerate.
120 * aarch64-opc-2.c: Regenerate.
122 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
124 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
125 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
126 * aarch64-asm-2.c: Regenerate.
127 * aarch64-dis-2.c: Regenerate.
128 * aarch64-opc-2.c: Regenerate.
130 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
132 * aarch64-tbl.h (QL_X1NIL): New.
133 (arch64_opcode_table): Add ldraa, ldrab.
134 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
135 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
136 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
137 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
138 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
139 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
140 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
141 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
142 (aarch64_print_operand): Likewise.
143 * aarch64-asm-2.c: Regenerate.
144 * aarch64-dis-2.c: Regenerate.
145 * aarch64-opc-2.c: Regenerate.
147 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
149 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
150 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
151 * aarch64-asm-2.c: Regenerate.
152 * aarch64-dis-2.c: Regenerate.
153 * aarch64-opc-2.c: Regenerate.
155 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
157 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
158 (AARCH64_OPERANDS): Add Rm_SP.
159 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
160 * aarch64-asm-2.c: Regenerate.
161 * aarch64-dis-2.c: Regenerate.
162 * aarch64-opc-2.c: Regenerate.
164 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
166 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
167 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
168 autdzb, xpaci, xpacd.
169 * aarch64-asm-2.c: Regenerate.
170 * aarch64-dis-2.c: Regenerate.
171 * aarch64-opc-2.c: Regenerate.
173 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
175 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
176 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
177 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
178 (aarch64_sys_reg_supported_p): Add feature test for new registers.
180 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
182 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
183 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
184 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
186 * aarch64-asm-2.c: Regenerate.
187 * aarch64-dis-2.c: Regenerate.
189 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
191 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
193 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
196 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
197 * i386-dis.c (EdqwS): Removed.
198 (dqw_swap_mode): Likewise.
199 (intel_operand_size): Don't check dqw_swap_mode.
200 (OP_E_register): Likewise.
201 (OP_E_memory): Likewise.
204 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
205 * i386-tbl.h: Regerated.
207 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
209 * i386-opc.tbl: Merge AVX512F vmovq.
210 * i386-tbl.h: Regerated.
212 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
215 * i386-dis.c (THREE_BYTE_0F7A): Removed.
216 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
217 (three_byte_table): Remove THREE_BYTE_0F7A.
219 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
222 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
223 (FGRPd9_4): Replace 1 with 2.
224 (FGRPd9_5): Replace 2 with 3.
225 (FGRPd9_6): Replace 3 with 4.
226 (FGRPd9_7): Replace 4 with 5.
227 (FGRPda_5): Replace 5 with 6.
228 (FGRPdb_4): Replace 6 with 7.
229 (FGRPde_3): Replace 7 with 8.
230 (FGRPdf_4): Replace 8 with 9.
231 (fgrps): Add an entry for Bad_Opcode.
233 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
235 * arc-opc.c (arc_flag_operands): Add F_DI14.
236 (arc_flag_classes): Add C_DI14.
237 * arc-nps400-tbl.h: Add new exc instructions.
239 2016-11-03 Graham Markall <graham.markall@embecosm.com>
241 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
243 * arc-nps-400-tbl.h: Add dcmac instruction.
244 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
245 (insert_nps_rbdouble_64): Added.
246 (extract_nps_rbdouble_64): Added.
247 (insert_nps_proto_size): Added.
248 (extract_nps_proto_size): Added.
250 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
252 * arc-dis.c (struct arc_operand_iterator): Remove all fields
253 relating to long instruction processing, add new limm field.
254 (OPCODE): Rename to...
255 (OPCODE_32BIT_INSN): ...this.
257 (skip_this_opcode): Handle different instruction lengths, update
259 (special_flag_p): Update parameter type.
260 (find_format_from_table): Update for more instruction lengths.
261 (find_format_long_instructions): Delete.
262 (find_format): Update for more instruction lengths.
263 (arc_insn_length): Likewise.
264 (extract_operand_value): Update for more instruction lengths.
265 (operand_iterator_next): Remove code relating to long
267 (arc_opcode_to_insn_type): New function.
268 (print_insn_arc):Update for more instructions lengths.
269 * arc-ext.c (extInstruction_t): Change argument type.
270 * arc-ext.h (extInstruction_t): Change argument type.
271 * arc-fxi.h: Change type unsigned to unsigned long long
272 extensively throughout.
273 * arc-nps400-tbl.h: Add long instructions taken from
274 arc_long_opcodes table in arc-opc.c.
275 * arc-opc.c: Update parameter types on insert/extract handlers.
276 (arc_long_opcodes): Delete.
277 (arc_num_long_opcodes): Delete.
278 (arc_opcode_len): Update for more instruction lengths.
280 2016-11-03 Graham Markall <graham.markall@embecosm.com>
282 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
284 2016-11-03 Graham Markall <graham.markall@embecosm.com>
286 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
288 (find_format_long_instructions): Likewise.
289 * arc-opc.c (arc_opcode_len): New function.
291 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
293 * arc-nps400-tbl.h: Fix some instruction masks.
295 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
297 * i386-dis.c (REG_82): Removed.
298 (X86_64_82_REG_0): Likewise.
299 (X86_64_82_REG_1): Likewise.
300 (X86_64_82_REG_2): Likewise.
301 (X86_64_82_REG_3): Likewise.
302 (X86_64_82_REG_4): Likewise.
303 (X86_64_82_REG_5): Likewise.
304 (X86_64_82_REG_6): Likewise.
305 (X86_64_82_REG_7): Likewise.
307 (dis386): Use X86_64_82 instead of REG_82.
308 (reg_table): Remove REG_82.
309 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
310 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
311 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
314 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
317 * i386-dis.c (REG_82): New.
318 (X86_64_82_REG_0): Likewise.
319 (X86_64_82_REG_1): Likewise.
320 (X86_64_82_REG_2): Likewise.
321 (X86_64_82_REG_3): Likewise.
322 (X86_64_82_REG_4): Likewise.
323 (X86_64_82_REG_5): Likewise.
324 (X86_64_82_REG_6): Likewise.
325 (X86_64_82_REG_7): Likewise.
326 (dis386): Use REG_82.
327 (reg_table): Add REG_82.
328 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
329 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
330 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
332 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
334 * i386-dis.c (REG_82): Renamed to ...
337 (reg_table): Likewise.
339 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
341 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
342 * i386-dis-evex.h (evex_table): Updated.
343 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
344 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
345 (cpu_flags): Add CpuAVX512_4VNNIW.
346 * i386-opc.h (enum): (AVX512_4VNNIW): New.
347 (i386_cpu_flags): Add cpuavx512_4vnniw.
348 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
349 * i386-init.h: Regenerate.
352 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
354 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
355 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
356 * i386-dis-evex.h (evex_table): Updated.
357 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
358 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
359 (cpu_flags): Add CpuAVX512_4FMAPS.
360 (opcode_modifiers): Add ImplicitQuadGroup modifier.
361 * i386-opc.h (AVX512_4FMAP): New.
362 (i386_cpu_flags): Add cpuavx512_4fmaps.
363 (ImplicitQuadGroup): New.
364 (i386_opcode_modifier): Add implicitquadgroup.
365 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
366 * i386-init.h: Regenerate.
369 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
370 Andrew Waterman <andrew@sifive.com>
372 Add support for RISC-V architecture.
373 * configure.ac: Add entry for bfd_riscv_arch.
374 * configure: Regenerate.
375 * disassemble.c (disassembler): Add support for riscv.
376 (disassembler_usage): Likewise.
377 * riscv-dis.c: New file.
378 * riscv-opc.c: New file.
380 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
382 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
383 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
384 (rm_table): Update the RM_0FAE_REG_7 entry.
385 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
386 (cpu_flags): Remove CpuPCOMMIT.
387 * i386-opc.h (CpuPCOMMIT): Removed.
388 (i386_cpu_flags): Remove cpupcommit.
389 * i386-opc.tbl: Remove pcommit.
390 * i386-init.h: Regenerated.
391 * i386-tbl.h: Likewise.
393 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
396 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
397 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
398 32-bit mode. Don't check vex.register_specifier in 32-bit
400 (OP_VEX): Check for invalid mask registers.
402 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
405 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
408 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
411 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
413 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
415 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
416 local variable to `index_regno'.
418 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
420 * arc-tbl.h: Removed any "inv.+" instructions from the table.
422 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
424 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
427 2016-10-11 Jiong Wang <jiong.wang@arm.com>
430 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
432 2016-10-07 Jiong Wang <jiong.wang@arm.com>
435 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
438 2016-10-07 Alan Modra <amodra@gmail.com>
440 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
442 2016-10-06 Alan Modra <amodra@gmail.com>
444 * aarch64-opc.c: Spell fall through comments consistently.
445 * i386-dis.c: Likewise.
446 * aarch64-dis.c: Add missing fall through comments.
447 * aarch64-opc.c: Likewise.
448 * arc-dis.c: Likewise.
449 * arm-dis.c: Likewise.
450 * i386-dis.c: Likewise.
451 * m68k-dis.c: Likewise.
452 * mep-asm.c: Likewise.
453 * ns32k-dis.c: Likewise.
454 * sh-dis.c: Likewise.
455 * tic4x-dis.c: Likewise.
456 * tic6x-dis.c: Likewise.
457 * vax-dis.c: Likewise.
459 2016-10-06 Alan Modra <amodra@gmail.com>
461 * arc-ext.c (create_map): Add missing break.
462 * msp430-decode.opc (encode_as): Likewise.
463 * msp430-decode.c: Regenerate.
465 2016-10-06 Alan Modra <amodra@gmail.com>
467 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
468 * crx-dis.c (print_insn_crx): Likewise.
470 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
473 * i386-dis.c (putop): Don't assign alt twice.
475 2016-09-29 Jiong Wang <jiong.wang@arm.com>
478 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
480 2016-09-29 Alan Modra <amodra@gmail.com>
482 * ppc-opc.c (L): Make compulsory.
483 (LOPT): New, optional form of L.
484 (HTM_R): Define as LOPT.
486 (L32OPT): New, optional for 32-bit L.
487 (L2OPT): New, 2-bit L for dcbf.
490 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
491 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
493 <tlbiel, tlbie>: Use LOPT.
494 <wclr, wclrall>: Use L2.
496 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
498 * Makefile.in: Regenerate.
499 * configure: Likewise.
501 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
503 * arc-ext-tbl.h (EXTINSN2OPF): Define.
504 (EXTINSN2OP): Use EXTINSN2OPF.
505 (bspeekm, bspop, modapp): New extension instructions.
506 * arc-opc.c (F_DNZ_ND): Define.
511 * arc-tbl.h (dbnz): New instruction.
512 (prealloc): Allow it for ARC EM.
515 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
517 * aarch64-opc.c (print_immediate_offset_address): Print spaces
518 after commas in addresses.
519 (aarch64_print_operand): Likewise.
521 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
523 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
524 rather than "should be" or "expected to be" in error messages.
526 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
528 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
529 (print_mnemonic_name): ...here.
530 (print_comment): New function.
531 (print_aarch64_insn): Call it.
532 * aarch64-opc.c (aarch64_conds): Add SVE names.
533 (aarch64_print_operand): Print alternative condition names in
536 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
538 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
539 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
540 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
541 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
542 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
543 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
544 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
545 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
546 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
547 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
548 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
549 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
550 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
551 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
552 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
553 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
554 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
555 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
556 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
557 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
558 (OP_SVE_XWU, OP_SVE_XXU): New macros.
559 (aarch64_feature_sve): New variable.
561 (_SVE_INSN): Likewise.
562 (aarch64_opcode_table): Add SVE instructions.
563 * aarch64-opc.h (extract_fields): Declare.
564 * aarch64-opc-2.c: Regenerate.
565 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
566 * aarch64-asm-2.c: Regenerate.
567 * aarch64-dis.c (extract_fields): Make global.
568 (do_misc_decoding): Handle the new SVE aarch64_ops.
569 * aarch64-dis-2.c: Regenerate.
571 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
573 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
574 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
576 * aarch64-opc.c (fields): Add corresponding entries.
577 * aarch64-asm.c (aarch64_get_variant): New function.
578 (aarch64_encode_variant_using_iclass): Likewise.
579 (aarch64_opcode_encode): Call it.
580 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
581 (aarch64_opcode_decode): Call it.
583 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
585 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
586 and FP register operands.
587 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
588 (FLD_SVE_Vn): New aarch64_field_kinds.
589 * aarch64-opc.c (fields): Add corresponding entries.
590 (aarch64_print_operand): Handle the new SVE core and FP register
592 * aarch64-opc-2.c: Regenerate.
593 * aarch64-asm-2.c: Likewise.
594 * aarch64-dis-2.c: Likewise.
596 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
598 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
600 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
601 * aarch64-opc.c (fields): Add corresponding entry.
602 (operand_general_constraint_met_p): Handle the new SVE FP immediate
604 (aarch64_print_operand): Likewise.
605 * aarch64-opc-2.c: Regenerate.
606 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
607 (ins_sve_float_zero_one): New inserters.
608 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
609 (aarch64_ins_sve_float_half_two): Likewise.
610 (aarch64_ins_sve_float_zero_one): Likewise.
611 * aarch64-asm-2.c: Regenerate.
612 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
613 (ext_sve_float_zero_one): New extractors.
614 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
615 (aarch64_ext_sve_float_half_two): Likewise.
616 (aarch64_ext_sve_float_zero_one): Likewise.
617 * aarch64-dis-2.c: Regenerate.
619 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
621 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
622 integer immediate operands.
623 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
624 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
625 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
626 * aarch64-opc.c (fields): Add corresponding entries.
627 (operand_general_constraint_met_p): Handle the new SVE integer
629 (aarch64_print_operand): Likewise.
630 (aarch64_sve_dupm_mov_immediate_p): New function.
631 * aarch64-opc-2.c: Regenerate.
632 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
633 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
634 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
635 (aarch64_ins_limm): ...here.
636 (aarch64_ins_inv_limm): New function.
637 (aarch64_ins_sve_aimm): Likewise.
638 (aarch64_ins_sve_asimm): Likewise.
639 (aarch64_ins_sve_limm_mov): Likewise.
640 (aarch64_ins_sve_shlimm): Likewise.
641 (aarch64_ins_sve_shrimm): Likewise.
642 * aarch64-asm-2.c: Regenerate.
643 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
644 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
645 * aarch64-dis.c (decode_limm): New function, split out from...
646 (aarch64_ext_limm): ...here.
647 (aarch64_ext_inv_limm): New function.
648 (decode_sve_aimm): Likewise.
649 (aarch64_ext_sve_aimm): Likewise.
650 (aarch64_ext_sve_asimm): Likewise.
651 (aarch64_ext_sve_limm_mov): Likewise.
652 (aarch64_top_bit): Likewise.
653 (aarch64_ext_sve_shlimm): Likewise.
654 (aarch64_ext_sve_shrimm): Likewise.
655 * aarch64-dis-2.c: Regenerate.
657 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
659 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
661 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
662 the AARCH64_MOD_MUL_VL entry.
663 (value_aligned_p): Cope with non-power-of-two alignments.
664 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
665 (print_immediate_offset_address): Likewise.
666 (aarch64_print_operand): Likewise.
667 * aarch64-opc-2.c: Regenerate.
668 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
669 (ins_sve_addr_ri_s9xvl): New inserters.
670 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
671 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
672 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
673 * aarch64-asm-2.c: Regenerate.
674 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
675 (ext_sve_addr_ri_s9xvl): New extractors.
676 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
677 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
678 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
679 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
680 * aarch64-dis-2.c: Regenerate.
682 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
684 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
686 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
687 (FLD_SVE_xs_22): New aarch64_field_kinds.
688 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
689 (get_operand_specific_data): New function.
690 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
691 FLD_SVE_xs_14 and FLD_SVE_xs_22.
692 (operand_general_constraint_met_p): Handle the new SVE address
694 (sve_reg): New array.
695 (get_addr_sve_reg_name): New function.
696 (aarch64_print_operand): Handle the new SVE address operands.
697 * aarch64-opc-2.c: Regenerate.
698 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
699 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
700 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
701 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
702 (aarch64_ins_sve_addr_rr_lsl): Likewise.
703 (aarch64_ins_sve_addr_rz_xtw): Likewise.
704 (aarch64_ins_sve_addr_zi_u5): Likewise.
705 (aarch64_ins_sve_addr_zz): Likewise.
706 (aarch64_ins_sve_addr_zz_lsl): Likewise.
707 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
708 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
709 * aarch64-asm-2.c: Regenerate.
710 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
711 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
712 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
713 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
714 (aarch64_ext_sve_addr_ri_u6): Likewise.
715 (aarch64_ext_sve_addr_rr_lsl): Likewise.
716 (aarch64_ext_sve_addr_rz_xtw): Likewise.
717 (aarch64_ext_sve_addr_zi_u5): Likewise.
718 (aarch64_ext_sve_addr_zz): Likewise.
719 (aarch64_ext_sve_addr_zz_lsl): Likewise.
720 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
721 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
722 * aarch64-dis-2.c: Regenerate.
724 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
726 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
727 AARCH64_OPND_SVE_PATTERN_SCALED.
728 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
729 * aarch64-opc.c (fields): Add a corresponding entry.
730 (set_multiplier_out_of_range_error): New function.
731 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
732 (operand_general_constraint_met_p): Handle
733 AARCH64_OPND_SVE_PATTERN_SCALED.
734 (print_register_offset_address): Use PRIi64 to print the
736 (aarch64_print_operand): Likewise. Handle
737 AARCH64_OPND_SVE_PATTERN_SCALED.
738 * aarch64-opc-2.c: Regenerate.
739 * aarch64-asm.h (ins_sve_scale): New inserter.
740 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
741 * aarch64-asm-2.c: Regenerate.
742 * aarch64-dis.h (ext_sve_scale): New inserter.
743 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
744 * aarch64-dis-2.c: Regenerate.
746 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
748 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
749 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
750 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
751 (FLD_SVE_prfop): Likewise.
752 * aarch64-opc.c: Include libiberty.h.
753 (aarch64_sve_pattern_array): New variable.
754 (aarch64_sve_prfop_array): Likewise.
755 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
756 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
757 AARCH64_OPND_SVE_PRFOP.
758 * aarch64-asm-2.c: Regenerate.
759 * aarch64-dis-2.c: Likewise.
760 * aarch64-opc-2.c: Likewise.
762 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
764 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
765 AARCH64_OPND_QLF_P_[ZM].
766 (aarch64_print_operand): Print /z and /m where appropriate.
768 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
770 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
771 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
772 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
773 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
774 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
775 * aarch64-opc.c (fields): Add corresponding entries here.
776 (operand_general_constraint_met_p): Check that SVE register lists
777 have the correct length. Check the ranges of SVE index registers.
778 Check for cases where p8-p15 are used in 3-bit predicate fields.
779 (aarch64_print_operand): Handle the new SVE operands.
780 * aarch64-opc-2.c: Regenerate.
781 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
782 * aarch64-asm.c (aarch64_ins_sve_index): New function.
783 (aarch64_ins_sve_reglist): Likewise.
784 * aarch64-asm-2.c: Regenerate.
785 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
786 * aarch64-dis.c (aarch64_ext_sve_index): New function.
787 (aarch64_ext_sve_reglist): Likewise.
788 * aarch64-dis-2.c: Regenerate.
790 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
792 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
793 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
794 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
795 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
798 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
800 * aarch64-opc.c (get_offset_int_reg_name): New function.
801 (print_immediate_offset_address): Likewise.
802 (print_register_offset_address): Take the base and offset
803 registers as parameters.
804 (aarch64_print_operand): Update caller accordingly. Use
805 print_immediate_offset_address.
807 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
809 * aarch64-opc.c (BANK): New macro.
810 (R32, R64): Take a register number as argument
813 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
815 * aarch64-opc.c (print_register_list): Add a prefix parameter.
816 (aarch64_print_operand): Update accordingly.
818 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
820 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
822 * aarch64-asm.h (ins_fpimm): New inserter.
823 * aarch64-asm.c (aarch64_ins_fpimm): New function.
824 * aarch64-asm-2.c: Regenerate.
825 * aarch64-dis.h (ext_fpimm): New extractor.
826 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
827 (aarch64_ext_fpimm): New function.
828 * aarch64-dis-2.c: Regenerate.
830 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
832 * aarch64-asm.c: Include libiberty.h.
833 (insert_fields): New function.
834 (aarch64_ins_imm): Use it.
835 * aarch64-dis.c (extract_fields): New function.
836 (aarch64_ext_imm): Use it.
838 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
840 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
841 with an esize parameter.
842 (operand_general_constraint_met_p): Update accordingly.
843 Fix misindented code.
844 * aarch64-asm.c (aarch64_ins_limm): Update call to
845 aarch64_logical_immediate_p.
847 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
849 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
851 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
853 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
855 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
857 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
859 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
861 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
862 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
863 xor3>: Delete mnemonics.
864 <cp_abort>: Rename mnemonic from ...
865 <cpabort>: ...to this.
866 <setb>: Change to a X form instruction.
867 <sync>: Change to 1 operand form.
868 <copy>: Delete mnemonic.
869 <copy_first>: Rename mnemonic from ...
871 <paste, paste.>: Delete mnemonics.
872 <paste_last>: Rename mnemonic from ...
873 <paste.>: ...to this.
875 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
877 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
879 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
881 * s390-mkopc.c (main): Support alternate arch strings.
883 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
885 * s390-opc.txt: Fix kmctr instruction type.
887 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
889 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
890 * i386-init.h: Regenerated.
892 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
894 * opcodes/arc-dis.c (print_insn_arc): Changed.
896 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
898 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
901 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
903 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
904 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
905 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
907 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
909 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
910 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
911 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
912 PREFIX_MOD_3_0FAE_REG_4.
913 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
914 PREFIX_MOD_3_0FAE_REG_4.
915 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
916 (cpu_flags): Add CpuPTWRITE.
917 * i386-opc.h (CpuPTWRITE): New.
918 (i386_cpu_flags): Add cpuptwrite.
919 * i386-opc.tbl: Add ptwrite instruction.
920 * i386-init.h: Regenerated.
921 * i386-tbl.h: Likewise.
923 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
925 * arc-dis.h: Wrap around in extern "C".
927 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
929 * aarch64-tbl.h (V8_2_INSN): New macro.
930 (aarch64_opcode_table): Use it.
932 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
934 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
935 CORE_INSN, __FP_INSN and SIMD_INSN.
937 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
939 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
940 (aarch64_opcode_table): Update uses accordingly.
942 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
943 Kwok Cheung Yeung <kcy@codesourcery.com>
946 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
947 'e_cmplwi' to 'e_cmpli' instead.
948 (OPVUPRT, OPVUPRT_MASK): Define.
949 (powerpc_opcodes): Add E200Z4 insns.
950 (vle_opcodes): Add context save/restore insns.
952 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
954 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
955 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
958 2016-07-27 Graham Markall <graham.markall@embecosm.com>
960 * arc-nps400-tbl.h: Change block comments to GNU format.
961 * arc-dis.c: Add new globals addrtypenames,
962 addrtypenames_max, and addtypeunknown.
963 (get_addrtype): New function.
964 (print_insn_arc): Print colons and address types when
966 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
967 define insert and extract functions for all address types.
968 (arc_operands): Add operands for colon and all address
970 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
971 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
972 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
973 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
974 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
975 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
977 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
979 * configure: Regenerated.
981 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
983 * arc-dis.c (skipclass): New structure.
984 (decodelist): New variable.
985 (is_compatible_p): New function.
986 (new_element): Likewise.
987 (skip_class_p): Likewise.
988 (find_format_from_table): Use skip_class_p function.
989 (find_format): Decode first the extension instructions.
990 (print_insn_arc): Select either ARCEM or ARCHS based on elf
992 (parse_option): New function.
993 (parse_disassembler_options): Likewise.
994 (print_arc_disassembler_options): Likewise.
995 (print_insn_arc): Use parse_disassembler_options function. Proper
996 select ARCv2 cpu variant.
997 * disassemble.c (disassembler_usage): Add ARC disassembler
1000 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1002 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1003 annotation from the "nal" entry and reorder it beyond "bltzal".
1005 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1007 * sparc-opc.c (ldtxa): New macro.
1008 (sparc_opcodes): Use the macro defined above to add entries for
1009 the LDTXA instructions.
1010 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1013 2016-07-07 James Bowman <james.bowman@ftdichip.com>
1015 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1018 2016-07-01 Jan Beulich <jbeulich@suse.com>
1020 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1021 (movzb): Adjust to cover all permitted suffixes.
1023 * i386-tbl.h: Re-generate.
1025 2016-07-01 Jan Beulich <jbeulich@suse.com>
1027 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1028 (lgdt): Remove Tbyte from non-64-bit variant.
1029 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1030 xsaves64, xsavec64): Remove Disp16.
1031 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1032 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1034 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1035 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1036 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1038 * i386-tbl.h: Re-generate.
1040 2016-07-01 Jan Beulich <jbeulich@suse.com>
1042 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1043 * i386-tbl.h: Re-generate.
1045 2016-06-30 Yao Qi <yao.qi@linaro.org>
1047 * arm-dis.c (print_insn): Fix typo in comment.
1049 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1051 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1052 range of ldst_elemlist operands.
1053 (print_register_list): Use PRIi64 to print the index.
1054 (aarch64_print_operand): Likewise.
1056 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1058 * mcore-opc.h: Remove sentinal.
1059 * mcore-dis.c (print_insn_mcore): Adjust.
1061 2016-06-23 Graham Markall <graham.markall@embecosm.com>
1063 * arc-opc.c: Correct description of availability of NPS400
1066 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1068 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1069 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1070 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1071 xor3>: New mnemonics.
1072 <setb>: Change to a VX form instruction.
1073 (insert_sh6): Add support for rldixor.
1074 (extract_sh6): Likewise.
1076 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1078 * arc-ext.h: Wrap in extern C.
1080 2016-06-21 Graham Markall <graham.markall@embecosm.com>
1082 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1083 Use same method for determining instruction length on ARC700 and
1085 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1086 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1087 with the NPS400 subclass.
1088 * arc-opc.c: Likewise.
1090 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1092 * sparc-opc.c (rdasr): New macro.
1098 (sparc_opcodes): Use the macros above to fix and expand the
1099 definition of read/write instructions from/to
1100 asr/privileged/hyperprivileged instructions.
1101 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1102 %hva_mask_nz. Prefer softint_set and softint_clear over
1103 set_softint and clear_softint.
1104 (print_insn_sparc): Support %ver in Rd.
1106 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1108 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1109 architecture according to the hardware capabilities they require.
1111 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1113 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1114 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1115 bfd_mach_sparc_v9{c,d,e,v,m}.
1116 * sparc-opc.c (MASK_V9C): Define.
1117 (MASK_V9D): Likewise.
1118 (MASK_V9E): Likewise.
1119 (MASK_V9V): Likewise.
1120 (MASK_V9M): Likewise.
1121 (v6): Add MASK_V9{C,D,E,V,M}.
1122 (v6notlet): Likewise.
1126 (v9andleon): Likewise.
1134 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1136 2016-06-15 Nick Clifton <nickc@redhat.com>
1138 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1139 constants to match expected behaviour.
1140 (nds32_parse_opcode): Likewise. Also for whitespace.
1142 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1144 * arc-opc.c (extract_rhv1): Extract value from insn.
1146 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1148 * arc-nps400-tbl.h: Add ldbit instruction.
1149 * arc-opc.c: Add flag classes required for ldbit.
1151 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1153 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1154 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1155 support the above instructions.
1157 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1159 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1160 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1161 csma, cbba, zncv, and hofs.
1162 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1163 support the above instructions.
1165 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1167 * arc-nps400-tbl.h: Add andab and orab instructions.
1169 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1171 * arc-nps400-tbl.h: Add addl-like instructions.
1173 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1175 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1177 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1179 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1182 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1184 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1186 (init_disasm): Handle new command line option "insnlength".
1187 (print_s390_disassembler_options): Mention new option in help
1189 (print_insn_s390): Use the encoded insn length when dumping
1190 unknown instructions.
1192 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1194 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1195 to the address and set as symbol address for LDS/ STS immediate operands.
1197 2016-06-07 Alan Modra <amodra@gmail.com>
1199 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1200 cpu for "vle" to e500.
1201 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1202 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1203 (PPCNONE): Delete, substitute throughout.
1204 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1205 except for major opcode 4 and 31.
1206 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1208 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1210 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1211 ARM_EXT_RAS in relevant entries.
1213 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1216 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1219 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1222 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1223 (indir_v_mode): New.
1224 Add comments for '&'.
1225 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1226 (putop): Handle '&'.
1227 (intel_operand_size): Handle indir_v_mode.
1228 (OP_E_register): Likewise.
1229 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1230 64-bit indirect call/jmp for AMD64.
1231 * i386-tbl.h: Regenerated
1233 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1235 * arc-dis.c (struct arc_operand_iterator): New structure.
1236 (find_format_from_table): All the old content from find_format,
1237 with some minor adjustments, and parameter renaming.
1238 (find_format_long_instructions): New function.
1239 (find_format): Rewritten.
1240 (arc_insn_length): Add LSB parameter.
1241 (extract_operand_value): New function.
1242 (operand_iterator_next): New function.
1243 (print_insn_arc): Use new functions to find opcode, and iterator
1245 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1246 (extract_nps_3bit_dst_short): New function.
1247 (insert_nps_3bit_src2_short): New function.
1248 (extract_nps_3bit_src2_short): New function.
1249 (insert_nps_bitop1_size): New function.
1250 (extract_nps_bitop1_size): New function.
1251 (insert_nps_bitop2_size): New function.
1252 (extract_nps_bitop2_size): New function.
1253 (insert_nps_bitop_mod4_msb): New function.
1254 (extract_nps_bitop_mod4_msb): New function.
1255 (insert_nps_bitop_mod4_lsb): New function.
1256 (extract_nps_bitop_mod4_lsb): New function.
1257 (insert_nps_bitop_dst_pos3_pos4): New function.
1258 (extract_nps_bitop_dst_pos3_pos4): New function.
1259 (insert_nps_bitop_ins_ext): New function.
1260 (extract_nps_bitop_ins_ext): New function.
1261 (arc_operands): Add new operands.
1262 (arc_long_opcodes): New global array.
1263 (arc_num_long_opcodes): New global.
1264 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1266 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1268 * nds32-asm.h: Add extern "C".
1269 * sh-opc.h: Likewise.
1271 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1273 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1274 0,b,limm to the rflt instruction.
1276 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1278 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1281 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1284 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1285 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1286 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1287 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1288 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1289 * i386-init.h: Regenerated.
1291 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1294 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1295 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1296 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1297 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1298 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1299 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1300 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1301 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1302 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1303 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1304 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1305 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1306 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1307 CpuRegMask for AVX512.
1308 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1310 (set_bitfield_from_cpu_flag_init): New function.
1311 (set_bitfield): Remove const on f. Call
1312 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1313 * i386-opc.h (CpuRegMMX): New.
1314 (CpuRegXMM): Likewise.
1315 (CpuRegYMM): Likewise.
1316 (CpuRegZMM): Likewise.
1317 (CpuRegMask): Likewise.
1318 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1320 * i386-init.h: Regenerated.
1321 * i386-tbl.h: Likewise.
1323 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1326 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1327 (opcode_modifiers): Add AMD64 and Intel64.
1328 (main): Properly verify CpuMax.
1329 * i386-opc.h (CpuAMD64): Removed.
1330 (CpuIntel64): Likewise.
1331 (CpuMax): Set to CpuNo64.
1332 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1334 (Intel64): Likewise.
1335 (i386_opcode_modifier): Add amd64 and intel64.
1336 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1338 * i386-init.h: Regenerated.
1339 * i386-tbl.h: Likewise.
1341 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1344 * i386-gen.c (main): Fail if CpuMax is incorrect.
1345 * i386-opc.h (CpuMax): Set to CpuIntel64.
1346 * i386-tbl.h: Regenerated.
1348 2016-05-27 Nick Clifton <nickc@redhat.com>
1351 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1352 (msp430dis_opcode_unsigned): New function.
1353 (msp430dis_opcode_signed): New function.
1354 (msp430_singleoperand): Use the new opcode reading functions.
1355 Only disassenmble bytes if they were successfully read.
1356 (msp430_doubleoperand): Likewise.
1357 (msp430_branchinstr): Likewise.
1358 (msp430x_callx_instr): Likewise.
1359 (print_insn_msp430): Check that it is safe to read bytes before
1360 attempting disassembly. Use the new opcode reading functions.
1362 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1364 * ppc-opc.c (CY): New define. Document it.
1365 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1367 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1369 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1370 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1371 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1372 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1374 * i386-init.h: Regenerated.
1376 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1379 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1380 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1381 * i386-init.h: Regenerated.
1383 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1385 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1386 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1387 * i386-init.h: Regenerated.
1389 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1391 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1393 (print_insn_arc): Set insn_type information.
1394 * arc-opc.c (C_CC): Add F_CLASS_COND.
1395 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1396 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1397 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1398 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1399 (brne, brne_s, jeq_s, jne_s): Likewise.
1401 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1403 * arc-tbl.h (neg): New instruction variant.
1405 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1407 * arc-dis.c (find_format, find_format, get_auxreg)
1408 (print_insn_arc): Changed.
1409 * arc-ext.h (INSERT_XOP): Likewise.
1411 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1413 * tic54x-dis.c (sprint_mmr): Adjust.
1414 * tic54x-opc.c: Likewise.
1416 2016-05-19 Alan Modra <amodra@gmail.com>
1418 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1420 2016-05-19 Alan Modra <amodra@gmail.com>
1422 * ppc-opc.c: Formatting.
1423 (NSISIGNOPT): Define.
1424 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1426 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1428 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1429 replacing references to `micromips_ase' throughout.
1430 (_print_insn_mips): Don't use file-level microMIPS annotation to
1431 determine the disassembly mode with the symbol table.
1433 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1435 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1437 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1439 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1441 * mips-opc.c (D34): New macro.
1442 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1444 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1446 * i386-dis.c (prefix_table): Add RDPID instruction.
1447 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1448 (cpu_flags): Add RDPID bitfield.
1449 * i386-opc.h (enum): Add RDPID element.
1450 (i386_cpu_flags): Add RDPID field.
1451 * i386-opc.tbl: Add RDPID instruction.
1452 * i386-init.h: Regenerate.
1453 * i386-tbl.h: Regenerate.
1455 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1457 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1458 branch type of a symbol.
1459 (print_insn): Likewise.
1461 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1463 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1464 Mainline Security Extensions instructions.
1465 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1466 Extensions instructions.
1467 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1469 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1472 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1474 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1476 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1478 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1479 (arcExtMap_genOpcode): Likewise.
1480 * arc-opc.c (arg_32bit_rc): Define new variable.
1481 (arg_32bit_u6): Likewise.
1482 (arg_32bit_limm): Likewise.
1484 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1486 * aarch64-gen.c (VERIFIER): Define.
1487 * aarch64-opc.c (VERIFIER): Define.
1488 (verify_ldpsw): Use static linkage.
1489 * aarch64-opc.h (verify_ldpsw): Remove.
1490 * aarch64-tbl.h: Use VERIFIER for verifiers.
1492 2016-04-28 Nick Clifton <nickc@redhat.com>
1495 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1496 * aarch64-opc.c (verify_ldpsw): New function.
1497 * aarch64-opc.h (verify_ldpsw): New prototype.
1498 * aarch64-tbl.h: Add initialiser for verifier field.
1499 (LDPSW): Set verifier to verify_ldpsw.
1501 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1505 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1506 smaller than address size.
1508 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1510 * alpha-dis.c: Regenerate.
1511 * crx-dis.c: Likewise.
1512 * disassemble.c: Likewise.
1513 * epiphany-opc.c: Likewise.
1514 * fr30-opc.c: Likewise.
1515 * frv-opc.c: Likewise.
1516 * ip2k-opc.c: Likewise.
1517 * iq2000-opc.c: Likewise.
1518 * lm32-opc.c: Likewise.
1519 * lm32-opinst.c: Likewise.
1520 * m32c-opc.c: Likewise.
1521 * m32r-opc.c: Likewise.
1522 * m32r-opinst.c: Likewise.
1523 * mep-opc.c: Likewise.
1524 * mt-opc.c: Likewise.
1525 * or1k-opc.c: Likewise.
1526 * or1k-opinst.c: Likewise.
1527 * tic80-opc.c: Likewise.
1528 * xc16x-opc.c: Likewise.
1529 * xstormy16-opc.c: Likewise.
1531 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1533 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1534 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1535 calcsd, and calcxd instructions.
1536 * arc-opc.c (insert_nps_bitop_size): Delete.
1537 (extract_nps_bitop_size): Delete.
1538 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1539 (extract_nps_qcmp_m3): Define.
1540 (extract_nps_qcmp_m2): Define.
1541 (extract_nps_qcmp_m1): Define.
1542 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1543 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1544 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1545 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1546 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1549 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1551 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1553 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1555 * Makefile.in: Regenerated with automake 1.11.6.
1556 * aclocal.m4: Likewise.
1558 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1560 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1562 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1563 (extract_nps_cmem_uimm16): New function.
1564 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1566 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1568 * arc-dis.c (arc_insn_length): New function.
1569 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1570 (find_format): Change insnLen parameter to unsigned.
1572 2016-04-13 Nick Clifton <nickc@redhat.com>
1575 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1576 the LD.B and LD.BU instructions.
1578 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1580 * arc-dis.c (find_format): Check for extension flags.
1581 (print_flags): New function.
1582 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1584 * arc-ext.c (arcExtMap_coreRegName): Use
1585 LAST_EXTENSION_CORE_REGISTER.
1586 (arcExtMap_coreReadWrite): Likewise.
1587 (dump_ARC_extmap): Update printing.
1588 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1589 (arc_aux_regs): Add cpu field.
1590 * arc-regs.h: Add cpu field, lower case name aux registers.
1592 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1594 * arc-tbl.h: Add rtsc, sleep with no arguments.
1596 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1598 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1600 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1601 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1602 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1603 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1604 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1605 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1606 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1607 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1608 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1609 (arc_opcode arc_opcodes): Null terminate the array.
1610 (arc_num_opcodes): Remove.
1611 * arc-ext.h (INSERT_XOP): Define.
1612 (extInstruction_t): Likewise.
1613 (arcExtMap_instName): Delete.
1614 (arcExtMap_insn): New function.
1615 (arcExtMap_genOpcode): Likewise.
1616 * arc-ext.c (ExtInstruction): Remove.
1617 (create_map): Zero initialize instruction fields.
1618 (arcExtMap_instName): Remove.
1619 (arcExtMap_insn): New function.
1620 (dump_ARC_extmap): More info while debuging.
1621 (arcExtMap_genOpcode): New function.
1622 * arc-dis.c (find_format): New function.
1623 (print_insn_arc): Use find_format.
1624 (arc_get_disassembler): Enable dump_ARC_extmap only when
1627 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1629 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1630 instruction bits out.
1632 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1634 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1635 * arc-opc.c (arc_flag_operands): Add new flags.
1636 (arc_flag_classes): Add new classes.
1638 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1640 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1642 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1644 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1645 encode1, rflt, crc16, and crc32 instructions.
1646 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1647 (arc_flag_classes): Add C_NPS_R.
1648 (insert_nps_bitop_size_2b): New function.
1649 (extract_nps_bitop_size_2b): Likewise.
1650 (insert_nps_bitop_uimm8): Likewise.
1651 (extract_nps_bitop_uimm8): Likewise.
1652 (arc_operands): Add new operand entries.
1654 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1656 * arc-regs.h: Add a new subclass field. Add double assist
1657 accumulator register values.
1658 * arc-tbl.h: Use DPA subclass to mark the double assist
1659 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1660 * arc-opc.c (RSP): Define instead of SP.
1661 (arc_aux_regs): Add the subclass field.
1663 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1665 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1667 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1669 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1672 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1674 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1675 issues. No functional changes.
1677 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1679 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1680 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1681 (RTT): Remove duplicate.
1682 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1683 (PCT_CONFIG*): Remove.
1684 (D1L, D1H, D2H, D2L): Define.
1686 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1688 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1690 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1692 * arc-tbl.h (invld07): Remove.
1693 * arc-ext-tbl.h: New file.
1694 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1695 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1697 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1699 Fix -Wstack-usage warnings.
1700 * aarch64-dis.c (print_operands): Substitute size.
1701 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1703 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1705 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1706 to get a proper diagnostic when an invalid ASR register is used.
1708 2016-03-22 Nick Clifton <nickc@redhat.com>
1710 * configure: Regenerate.
1712 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1714 * arc-nps400-tbl.h: New file.
1715 * arc-opc.c: Add top level comment.
1716 (insert_nps_3bit_dst): New function.
1717 (extract_nps_3bit_dst): New function.
1718 (insert_nps_3bit_src2): New function.
1719 (extract_nps_3bit_src2): New function.
1720 (insert_nps_bitop_size): New function.
1721 (extract_nps_bitop_size): New function.
1722 (arc_flag_operands): Add nps400 entries.
1723 (arc_flag_classes): Add nps400 entries.
1724 (arc_operands): Add nps400 entries.
1725 (arc_opcodes): Add nps400 include.
1727 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1729 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1730 the new class enum values.
1732 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1734 * arc-dis.c (print_insn_arc): Handle nps400.
1736 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1738 * arc-opc.c (BASE): Delete.
1740 2016-03-18 Nick Clifton <nickc@redhat.com>
1743 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1744 of MOV insn that aliases an ORR insn.
1746 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1748 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1750 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1752 * mcore-opc.h: Add const qualifiers.
1753 * microblaze-opc.h (struct op_code_struct): Likewise.
1754 * sh-opc.h: Likewise.
1755 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1756 (tic4x_print_op): Likewise.
1758 2016-03-02 Alan Modra <amodra@gmail.com>
1760 * or1k-desc.h: Regenerate.
1761 * fr30-ibld.c: Regenerate.
1762 * rl78-decode.c: Regenerate.
1764 2016-03-01 Nick Clifton <nickc@redhat.com>
1767 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1769 2016-02-24 Renlin Li <renlin.li@arm.com>
1771 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1772 (print_insn_coprocessor): Support fp16 instructions.
1774 2016-02-24 Renlin Li <renlin.li@arm.com>
1776 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1777 vminnm, vrint(mpna).
1779 2016-02-24 Renlin Li <renlin.li@arm.com>
1781 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1782 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1784 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1786 * i386-dis.c (print_insn): Parenthesize expression to prevent
1787 truncated addresses.
1790 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1791 Janek van Oirschot <jvanoirs@synopsys.com>
1793 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1796 2016-02-04 Nick Clifton <nickc@redhat.com>
1799 * msp430-dis.c (print_insn_msp430): Add a special case for
1800 decoding an RRC instruction with the ZC bit set in the extension
1803 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1805 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1806 * epiphany-ibld.c: Regenerate.
1807 * fr30-ibld.c: Regenerate.
1808 * frv-ibld.c: Regenerate.
1809 * ip2k-ibld.c: Regenerate.
1810 * iq2000-ibld.c: Regenerate.
1811 * lm32-ibld.c: Regenerate.
1812 * m32c-ibld.c: Regenerate.
1813 * m32r-ibld.c: Regenerate.
1814 * mep-ibld.c: Regenerate.
1815 * mt-ibld.c: Regenerate.
1816 * or1k-ibld.c: Regenerate.
1817 * xc16x-ibld.c: Regenerate.
1818 * xstormy16-ibld.c: Regenerate.
1820 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1822 * epiphany-dis.c: Regenerated from latest cpu files.
1824 2016-02-01 Michael McConville <mmcco@mykolab.com>
1826 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1829 2016-01-25 Renlin Li <renlin.li@arm.com>
1831 * arm-dis.c (mapping_symbol_for_insn): New function.
1832 (find_ifthen_state): Call mapping_symbol_for_insn().
1834 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1836 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1837 of MSR UAO immediate operand.
1839 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1841 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1842 instruction support.
1844 2016-01-17 Alan Modra <amodra@gmail.com>
1846 * configure: Regenerate.
1848 2016-01-14 Nick Clifton <nickc@redhat.com>
1850 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1851 instructions that can support stack pointer operations.
1852 * rl78-decode.c: Regenerate.
1853 * rl78-dis.c: Fix display of stack pointer in MOVW based
1856 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1858 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1859 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1860 erxtatus_el1 and erxaddr_el1.
1862 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1864 * arm-dis.c (arm_opcodes): Add "esb".
1865 (thumb_opcodes): Likewise.
1867 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1869 * ppc-opc.c <xscmpnedp>: Delete.
1870 <xvcmpnedp>: Likewise.
1871 <xvcmpnedp.>: Likewise.
1872 <xvcmpnesp>: Likewise.
1873 <xvcmpnesp.>: Likewise.
1875 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1878 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1881 2016-01-01 Alan Modra <amodra@gmail.com>
1883 Update year range in copyright notice of all files.
1885 For older changes see ChangeLog-2015
1887 Copyright (C) 2016 Free Software Foundation, Inc.
1889 Copying and distribution of this file, with or without modification,
1890 are permitted in any medium without royalty provided the copyright
1891 notice and this notice are preserved.
1897 version-control: never