1 2019-06-25 Jan Beulich <jbeulich@suse.com>
3 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
4 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
6 * i386-opc.tbl (movnti): Add IgnoreSize.
7 * i386-tbl.h: Re-generate.
9 2019-06-25 Jan Beulich <jbeulich@suse.com>
11 * i386-opc.tbl (and): Mark Imm8S form for optimization.
12 * i386-tbl.h: Re-generate.
14 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
16 * i386-dis-evex.h: Break into ...
17 * i386-dis-evex-len.h: New file.
18 * i386-dis-evex-mod.h: Likewise.
19 * i386-dis-evex-prefix.h: Likewise.
20 * i386-dis-evex-reg.h: Likewise.
21 * i386-dis-evex-w.h: Likewise.
22 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
23 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
26 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
29 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
30 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
32 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
33 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
34 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
35 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
36 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
37 EVEX_LEN_0F385B_P_2_W_1.
38 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
39 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
40 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
41 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
42 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
43 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
44 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
45 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
46 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
47 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
49 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
52 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
53 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
54 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
55 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
56 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
57 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
58 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
59 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
60 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
61 EVEX_LEN_0F3A43_P_2_W_1.
62 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
63 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
64 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
65 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
66 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
67 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
68 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
69 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
70 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
71 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
72 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
73 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
75 2019-06-14 Nick Clifton <nickc@redhat.com>
77 * po/fr.po; Updated French translation.
79 2019-06-13 Stafford Horne <shorne@gmail.com>
81 * or1k-asm.c: Regenerated.
82 * or1k-desc.c: Regenerated.
83 * or1k-desc.h: Regenerated.
84 * or1k-dis.c: Regenerated.
85 * or1k-ibld.c: Regenerated.
86 * or1k-opc.c: Regenerated.
87 * or1k-opc.h: Regenerated.
88 * or1k-opinst.c: Regenerated.
90 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
92 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
94 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
97 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
98 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
99 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
100 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
101 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
102 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
103 EVEX_LEN_0F3A1B_P_2_W_1.
104 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
105 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
106 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
107 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
108 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
109 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
110 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
111 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
113 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
116 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
117 EVEX.vvvv when disassembling VEX and EVEX instructions.
118 (OP_VEX): Set vex.register_specifier to 0 after readding
119 vex.register_specifier.
120 (OP_Vex_2src_1): Likewise.
121 (OP_Vex_2src_2): Likewise.
122 (OP_LWP_E): Likewise.
123 (OP_EX_Vex): Don't check vex.register_specifier.
124 (OP_XMM_Vex): Likewise.
126 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
127 Lili Cui <lili.cui@intel.com>
129 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
130 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
132 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
133 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
134 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
135 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
136 (i386_cpu_flags): Add cpuavx512_vp2intersect.
137 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
138 * i386-init.h: Regenerated.
139 * i386-tbl.h: Likewise.
141 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
142 Lili Cui <lili.cui@intel.com>
144 * doc/c-i386.texi: Document enqcmd.
145 * testsuite/gas/i386/enqcmd-intel.d: New file.
146 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
147 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
148 * testsuite/gas/i386/enqcmd.d: Likewise.
149 * testsuite/gas/i386/enqcmd.s: Likewise.
150 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
151 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
152 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
153 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
154 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
155 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
156 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
159 2019-06-04 Alan Hayward <alan.hayward@arm.com>
161 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
163 2019-06-03 Alan Modra <amodra@gmail.com>
165 * ppc-dis.c (prefix_opcd_indices): Correct size.
167 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
170 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
172 * i386-tbl.h: Regenerated.
174 2019-05-24 Alan Modra <amodra@gmail.com>
176 * po/POTFILES.in: Regenerate.
178 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
179 Alan Modra <amodra@gmail.com>
181 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
182 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
183 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
184 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
185 XTOP>): Define and add entries.
186 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
187 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
188 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
189 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
191 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
192 Alan Modra <amodra@gmail.com>
194 * ppc-dis.c (ppc_opts): Add "future" entry.
195 (PREFIX_OPCD_SEGS): Define.
196 (prefix_opcd_indices): New array.
197 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
198 (lookup_prefix): New function.
199 (print_insn_powerpc): Handle 64-bit prefix instructions.
200 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
201 (PMRR, POWERXX): Define.
202 (prefix_opcodes): New instruction table.
203 (prefix_num_opcodes): New constant.
205 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
207 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
208 * configure: Regenerated.
209 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
211 (HFILES): Add bpf-desc.h and bpf-opc.h.
212 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
213 bpf-ibld.c and bpf-opc.c.
215 * Makefile.in: Regenerated.
216 * disassemble.c (ARCH_bpf): Define.
217 (disassembler): Add case for bfd_arch_bpf.
218 (disassemble_init_for_target): Likewise.
219 (enum epbf_isa_attr): Define.
220 * disassemble.h: extern print_insn_bpf.
221 * bpf-asm.c: Generated.
222 * bpf-opc.h: Likewise.
223 * bpf-opc.c: Likewise.
224 * bpf-ibld.c: Likewise.
225 * bpf-dis.c: Likewise.
226 * bpf-desc.h: Likewise.
227 * bpf-desc.c: Likewise.
229 2019-05-21 Sudakshina Das <sudi.das@arm.com>
231 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
232 and VMSR with the new operands.
234 2019-05-21 Sudakshina Das <sudi.das@arm.com>
236 * arm-dis.c (enum mve_instructions): New enum
237 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
239 (mve_opcodes): New instructions as above.
240 (is_mve_encoding_conflict): Add cases for csinc, csinv,
242 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
244 2019-05-21 Sudakshina Das <sudi.das@arm.com>
246 * arm-dis.c (emun mve_instructions): Updated for new instructions.
247 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
248 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
249 uqshl, urshrl and urshr.
250 (is_mve_okay_in_it): Add new instructions to TRUE list.
251 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
252 (print_insn_mve): Updated to accept new %j,
253 %<bitfield>m and %<bitfield>n patterns.
255 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
257 * mips-opc.c (mips_builtin_opcodes): Change source register
260 2019-05-20 Nick Clifton <nickc@redhat.com>
262 * po/fr.po: Updated French translation.
264 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
265 Michael Collison <michael.collison@arm.com>
267 * arm-dis.c (thumb32_opcodes): Add new instructions.
268 (enum mve_instructions): Likewise.
269 (enum mve_undefined): Add new reasons.
270 (is_mve_encoding_conflict): Handle new instructions.
271 (is_mve_undefined): Likewise.
272 (is_mve_unpredictable): Likewise.
273 (print_mve_undefined): Likewise.
274 (print_mve_size): Likewise.
276 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
277 Michael Collison <michael.collison@arm.com>
279 * arm-dis.c (thumb32_opcodes): Add new instructions.
280 (enum mve_instructions): Likewise.
281 (is_mve_encoding_conflict): Handle new instructions.
282 (is_mve_undefined): Likewise.
283 (is_mve_unpredictable): Likewise.
284 (print_mve_size): Likewise.
286 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
287 Michael Collison <michael.collison@arm.com>
289 * arm-dis.c (thumb32_opcodes): Add new instructions.
290 (enum mve_instructions): Likewise.
291 (is_mve_encoding_conflict): Likewise.
292 (is_mve_unpredictable): Likewise.
293 (print_mve_size): Likewise.
295 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
296 Michael Collison <michael.collison@arm.com>
298 * arm-dis.c (thumb32_opcodes): Add new instructions.
299 (enum mve_instructions): Likewise.
300 (is_mve_encoding_conflict): Handle new instructions.
301 (is_mve_undefined): Likewise.
302 (is_mve_unpredictable): Likewise.
303 (print_mve_size): Likewise.
305 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
306 Michael Collison <michael.collison@arm.com>
308 * arm-dis.c (thumb32_opcodes): Add new instructions.
309 (enum mve_instructions): Likewise.
310 (is_mve_encoding_conflict): Handle new instructions.
311 (is_mve_undefined): Likewise.
312 (is_mve_unpredictable): Likewise.
313 (print_mve_size): Likewise.
314 (print_insn_mve): Likewise.
316 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
317 Michael Collison <michael.collison@arm.com>
319 * arm-dis.c (thumb32_opcodes): Add new instructions.
320 (print_insn_thumb32): Handle new instructions.
322 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
323 Michael Collison <michael.collison@arm.com>
325 * arm-dis.c (enum mve_instructions): Add new instructions.
326 (enum mve_undefined): Add new reasons.
327 (is_mve_encoding_conflict): Handle new instructions.
328 (is_mve_undefined): Likewise.
329 (is_mve_unpredictable): Likewise.
330 (print_mve_undefined): Likewise.
331 (print_mve_size): Likewise.
332 (print_mve_shift_n): Likewise.
333 (print_insn_mve): Likewise.
335 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
336 Michael Collison <michael.collison@arm.com>
338 * arm-dis.c (enum mve_instructions): Add new instructions.
339 (is_mve_encoding_conflict): Handle new instructions.
340 (is_mve_unpredictable): Likewise.
341 (print_mve_rotate): Likewise.
342 (print_mve_size): Likewise.
343 (print_insn_mve): Likewise.
345 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
346 Michael Collison <michael.collison@arm.com>
348 * arm-dis.c (enum mve_instructions): Add new instructions.
349 (is_mve_encoding_conflict): Handle new instructions.
350 (is_mve_unpredictable): Likewise.
351 (print_mve_size): Likewise.
352 (print_insn_mve): Likewise.
354 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
355 Michael Collison <michael.collison@arm.com>
357 * arm-dis.c (enum mve_instructions): Add new instructions.
358 (enum mve_undefined): Add new reasons.
359 (is_mve_encoding_conflict): Handle new instructions.
360 (is_mve_undefined): Likewise.
361 (is_mve_unpredictable): Likewise.
362 (print_mve_undefined): Likewise.
363 (print_mve_size): Likewise.
364 (print_insn_mve): Likewise.
366 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
367 Michael Collison <michael.collison@arm.com>
369 * arm-dis.c (enum mve_instructions): Add new instructions.
370 (is_mve_encoding_conflict): Handle new instructions.
371 (is_mve_undefined): Likewise.
372 (is_mve_unpredictable): Likewise.
373 (print_mve_size): Likewise.
374 (print_insn_mve): Likewise.
376 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
377 Michael Collison <michael.collison@arm.com>
379 * arm-dis.c (enum mve_instructions): Add new instructions.
380 (enum mve_unpredictable): Add new reasons.
381 (enum mve_undefined): Likewise.
382 (is_mve_okay_in_it): Handle new isntructions.
383 (is_mve_encoding_conflict): Likewise.
384 (is_mve_undefined): Likewise.
385 (is_mve_unpredictable): Likewise.
386 (print_mve_vmov_index): Likewise.
387 (print_simd_imm8): Likewise.
388 (print_mve_undefined): Likewise.
389 (print_mve_unpredictable): Likewise.
390 (print_mve_size): Likewise.
391 (print_insn_mve): Likewise.
393 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
394 Michael Collison <michael.collison@arm.com>
396 * arm-dis.c (enum mve_instructions): Add new instructions.
397 (enum mve_unpredictable): Add new reasons.
398 (enum mve_undefined): Likewise.
399 (is_mve_encoding_conflict): Handle new instructions.
400 (is_mve_undefined): Likewise.
401 (is_mve_unpredictable): Likewise.
402 (print_mve_undefined): Likewise.
403 (print_mve_unpredictable): Likewise.
404 (print_mve_rounding_mode): Likewise.
405 (print_mve_vcvt_size): Likewise.
406 (print_mve_size): Likewise.
407 (print_insn_mve): Likewise.
409 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
410 Michael Collison <michael.collison@arm.com>
412 * arm-dis.c (enum mve_instructions): Add new instructions.
413 (enum mve_unpredictable): Add new reasons.
414 (enum mve_undefined): Likewise.
415 (is_mve_undefined): Handle new instructions.
416 (is_mve_unpredictable): Likewise.
417 (print_mve_undefined): Likewise.
418 (print_mve_unpredictable): Likewise.
419 (print_mve_size): Likewise.
420 (print_insn_mve): Likewise.
422 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
423 Michael Collison <michael.collison@arm.com>
425 * arm-dis.c (enum mve_instructions): Add new instructions.
426 (enum mve_undefined): Add new reasons.
427 (insns): Add new instructions.
428 (is_mve_encoding_conflict):
429 (print_mve_vld_str_addr): New print function.
430 (is_mve_undefined): Handle new instructions.
431 (is_mve_unpredictable): Likewise.
432 (print_mve_undefined): Likewise.
433 (print_mve_size): Likewise.
434 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
435 (print_insn_mve): Handle new operands.
437 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
438 Michael Collison <michael.collison@arm.com>
440 * arm-dis.c (enum mve_instructions): Add new instructions.
441 (enum mve_unpredictable): Add new reasons.
442 (is_mve_encoding_conflict): Handle new instructions.
443 (is_mve_unpredictable): Likewise.
444 (mve_opcodes): Add new instructions.
445 (print_mve_unpredictable): Handle new reasons.
446 (print_mve_register_blocks): New print function.
447 (print_mve_size): Handle new instructions.
448 (print_insn_mve): Likewise.
450 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
451 Michael Collison <michael.collison@arm.com>
453 * arm-dis.c (enum mve_instructions): Add new instructions.
454 (enum mve_unpredictable): Add new reasons.
455 (enum mve_undefined): Likewise.
456 (is_mve_encoding_conflict): Handle new instructions.
457 (is_mve_undefined): Likewise.
458 (is_mve_unpredictable): Likewise.
459 (coprocessor_opcodes): Move NEON VDUP from here...
460 (neon_opcodes): ... to here.
461 (mve_opcodes): Add new instructions.
462 (print_mve_undefined): Handle new reasons.
463 (print_mve_unpredictable): Likewise.
464 (print_mve_size): Handle new instructions.
465 (print_insn_neon): Handle vdup.
466 (print_insn_mve): Handle new operands.
468 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
469 Michael Collison <michael.collison@arm.com>
471 * arm-dis.c (enum mve_instructions): Add new instructions.
472 (enum mve_unpredictable): Add new values.
473 (mve_opcodes): Add new instructions.
474 (vec_condnames): New array with vector conditions.
475 (mve_predicatenames): New array with predicate suffixes.
476 (mve_vec_sizename): New array with vector sizes.
477 (enum vpt_pred_state): New enum with vector predication states.
478 (struct vpt_block): New struct type for vpt blocks.
479 (vpt_block_state): Global struct to keep track of state.
480 (mve_extract_pred_mask): New helper function.
481 (num_instructions_vpt_block): Likewise.
482 (mark_outside_vpt_block): Likewise.
483 (mark_inside_vpt_block): Likewise.
484 (invert_next_predicate_state): Likewise.
485 (update_next_predicate_state): Likewise.
486 (update_vpt_block_state): Likewise.
487 (is_vpt_instruction): Likewise.
488 (is_mve_encoding_conflict): Add entries for new instructions.
489 (is_mve_unpredictable): Likewise.
490 (print_mve_unpredictable): Handle new cases.
491 (print_instruction_predicate): Likewise.
492 (print_mve_size): New function.
493 (print_vec_condition): New function.
494 (print_insn_mve): Handle vpt blocks and new print operands.
496 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
498 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
499 8, 14 and 15 for Armv8.1-M Mainline.
501 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
502 Michael Collison <michael.collison@arm.com>
504 * arm-dis.c (enum mve_instructions): New enum.
505 (enum mve_unpredictable): Likewise.
506 (enum mve_undefined): Likewise.
507 (struct mopcode32): New struct.
508 (is_mve_okay_in_it): New function.
509 (is_mve_architecture): Likewise.
510 (arm_decode_field): Likewise.
511 (arm_decode_field_multiple): Likewise.
512 (is_mve_encoding_conflict): Likewise.
513 (is_mve_undefined): Likewise.
514 (is_mve_unpredictable): Likewise.
515 (print_mve_undefined): Likewise.
516 (print_mve_unpredictable): Likewise.
517 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
518 (print_insn_mve): New function.
519 (print_insn_thumb32): Handle MVE architecture.
520 (select_arm_features): Force thumb for Armv8.1-m Mainline.
522 2019-05-10 Nick Clifton <nickc@redhat.com>
525 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
526 end of the table prematurely.
528 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
530 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
533 2019-05-11 Alan Modra <amodra@gmail.com>
535 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
536 when -Mraw is in effect.
538 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
540 * aarch64-dis-2.c: Regenerate.
541 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
542 (OP_SVE_BBB): New variant set.
543 (OP_SVE_DDDD): New variant set.
544 (OP_SVE_HHH): New variant set.
545 (OP_SVE_HHHU): New variant set.
546 (OP_SVE_SSS): New variant set.
547 (OP_SVE_SSSU): New variant set.
548 (OP_SVE_SHH): New variant set.
549 (OP_SVE_SBBU): New variant set.
550 (OP_SVE_DSS): New variant set.
551 (OP_SVE_DHHU): New variant set.
552 (OP_SVE_VMV_HSD_BHS): New variant set.
553 (OP_SVE_VVU_HSD_BHS): New variant set.
554 (OP_SVE_VVVU_SD_BH): New variant set.
555 (OP_SVE_VVVU_BHSD): New variant set.
556 (OP_SVE_VVV_QHD_DBS): New variant set.
557 (OP_SVE_VVV_HSD_BHS): New variant set.
558 (OP_SVE_VVV_HSD_BHS2): New variant set.
559 (OP_SVE_VVV_BHS_HSD): New variant set.
560 (OP_SVE_VV_BHS_HSD): New variant set.
561 (OP_SVE_VVV_SD): New variant set.
562 (OP_SVE_VVU_BHS_HSD): New variant set.
563 (OP_SVE_VZVV_SD): New variant set.
564 (OP_SVE_VZVV_BH): New variant set.
565 (OP_SVE_VZV_SD): New variant set.
566 (aarch64_opcode_table): Add sve2 instructions.
568 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
570 * aarch64-asm-2.c: Regenerated.
571 * aarch64-dis-2.c: Regenerated.
572 * aarch64-opc-2.c: Regenerated.
573 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
574 for SVE_SHLIMM_UNPRED_22.
575 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
576 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
579 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
581 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
582 sve_size_tsz_bhs iclass encode.
583 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
584 sve_size_tsz_bhs iclass decode.
586 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
588 * aarch64-asm-2.c: Regenerated.
589 * aarch64-dis-2.c: Regenerated.
590 * aarch64-opc-2.c: Regenerated.
591 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
592 for SVE_Zm4_11_INDEX.
593 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
594 (fields): Handle SVE_i2h field.
595 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
596 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
598 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
600 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
601 sve_shift_tsz_bhsd iclass encode.
602 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
603 sve_shift_tsz_bhsd iclass decode.
605 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
607 * aarch64-asm-2.c: Regenerated.
608 * aarch64-dis-2.c: Regenerated.
609 * aarch64-opc-2.c: Regenerated.
610 * aarch64-asm.c (aarch64_ins_sve_shrimm):
611 (aarch64_encode_variant_using_iclass): Handle
612 sve_shift_tsz_hsd iclass encode.
613 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
614 sve_shift_tsz_hsd iclass decode.
615 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
616 for SVE_SHRIMM_UNPRED_22.
617 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
618 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
621 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
623 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
624 sve_size_013 iclass encode.
625 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
626 sve_size_013 iclass decode.
628 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
630 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
631 sve_size_bh iclass encode.
632 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
633 sve_size_bh iclass decode.
635 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
637 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
638 sve_size_sd2 iclass encode.
639 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
640 sve_size_sd2 iclass decode.
641 * aarch64-opc.c (fields): Handle SVE_sz2 field.
642 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
644 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
646 * aarch64-asm-2.c: Regenerated.
647 * aarch64-dis-2.c: Regenerated.
648 * aarch64-opc-2.c: Regenerated.
649 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
651 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
652 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
654 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
656 * aarch64-asm-2.c: Regenerated.
657 * aarch64-dis-2.c: Regenerated.
658 * aarch64-opc-2.c: Regenerated.
659 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
660 for SVE_Zm3_11_INDEX.
661 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
662 (fields): Handle SVE_i3l and SVE_i3h2 fields.
663 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
665 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
667 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
669 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
670 sve_size_hsd2 iclass encode.
671 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
672 sve_size_hsd2 iclass decode.
673 * aarch64-opc.c (fields): Handle SVE_size field.
674 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
676 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
678 * aarch64-asm-2.c: Regenerated.
679 * aarch64-dis-2.c: Regenerated.
680 * aarch64-opc-2.c: Regenerated.
681 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
683 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
684 (fields): Handle SVE_rot3 field.
685 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
686 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
688 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
690 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
693 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
696 (aarch64_feature_sve2, aarch64_feature_sve2aes,
697 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
698 aarch64_feature_sve2bitperm): New feature sets.
699 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
700 for feature set addresses.
701 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
702 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
704 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
705 Faraz Shahbazker <fshahbazker@wavecomp.com>
707 * mips-dis.c (mips_calculate_combination_ases): Add ISA
708 argument and set ASE_EVA_R6 appropriately.
709 (set_default_mips_dis_options): Pass ISA to above.
710 (parse_mips_dis_option): Likewise.
711 * mips-opc.c (EVAR6): New macro.
712 (mips_builtin_opcodes): Add llwpe, scwpe.
714 2019-05-01 Sudakshina Das <sudi.das@arm.com>
716 * aarch64-asm-2.c: Regenerated.
717 * aarch64-dis-2.c: Regenerated.
718 * aarch64-opc-2.c: Regenerated.
719 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
720 AARCH64_OPND_TME_UIMM16.
721 (aarch64_print_operand): Likewise.
722 * aarch64-tbl.h (QL_IMM_NIL): New.
725 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
727 2019-04-29 John Darrington <john@darrington.wattle.id.au>
729 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
731 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
732 Faraz Shahbazker <fshahbazker@wavecomp.com>
734 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
736 2019-04-24 John Darrington <john@darrington.wattle.id.au>
738 * s12z-opc.h: Add extern "C" bracketing to help
739 users who wish to use this interface in c++ code.
741 2019-04-24 John Darrington <john@darrington.wattle.id.au>
743 * s12z-opc.c (bm_decode): Handle bit map operations with the
746 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
748 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
749 specifier. Add entries for VLDR and VSTR of system registers.
750 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
751 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
752 of %J and %K format specifier.
754 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
756 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
757 Add new entries for VSCCLRM instruction.
758 (print_insn_coprocessor): Handle new %C format control code.
760 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
762 * arm-dis.c (enum isa): New enum.
763 (struct sopcode32): New structure.
764 (coprocessor_opcodes): change type of entries to struct sopcode32 and
765 set isa field of all current entries to ANY.
766 (print_insn_coprocessor): Change type of insn to struct sopcode32.
767 Only match an entry if its isa field allows the current mode.
769 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
771 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
773 (print_insn_thumb32): Add logic to print %n CLRM register list.
775 2019-04-15 Sudakshina Das <sudi.das@arm.com>
777 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
780 2019-04-15 Sudakshina Das <sudi.das@arm.com>
782 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
783 (print_insn_thumb32): Edit the switch case for %Z.
785 2019-04-15 Sudakshina Das <sudi.das@arm.com>
787 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
789 2019-04-15 Sudakshina Das <sudi.das@arm.com>
791 * arm-dis.c (thumb32_opcodes): New instruction bfl.
793 2019-04-15 Sudakshina Das <sudi.das@arm.com>
795 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
797 2019-04-15 Sudakshina Das <sudi.das@arm.com>
799 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
800 Arm register with r13 and r15 unpredictable.
801 (thumb32_opcodes): New instructions for bfx and bflx.
803 2019-04-15 Sudakshina Das <sudi.das@arm.com>
805 * arm-dis.c (thumb32_opcodes): New instructions for bf.
807 2019-04-15 Sudakshina Das <sudi.das@arm.com>
809 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
811 2019-04-15 Sudakshina Das <sudi.das@arm.com>
813 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
815 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
817 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
819 2019-04-12 John Darrington <john@darrington.wattle.id.au>
821 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
822 "optr". ("operator" is a reserved word in c++).
824 2019-04-11 Sudakshina Das <sudi.das@arm.com>
826 * aarch64-opc.c (aarch64_print_operand): Add case for
828 (verify_constraints): Likewise.
829 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
830 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
831 to accept Rt|SP as first operand.
832 (AARCH64_OPERANDS): Add new Rt_SP.
833 * aarch64-asm-2.c: Regenerated.
834 * aarch64-dis-2.c: Regenerated.
835 * aarch64-opc-2.c: Regenerated.
837 2019-04-11 Sudakshina Das <sudi.das@arm.com>
839 * aarch64-asm-2.c: Regenerated.
840 * aarch64-dis-2.c: Likewise.
841 * aarch64-opc-2.c: Likewise.
842 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
844 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
846 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
848 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
850 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
851 * i386-init.h: Regenerated.
853 2019-04-07 Alan Modra <amodra@gmail.com>
855 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
856 op_separator to control printing of spaces, comma and parens
857 rather than need_comma, need_paren and spaces vars.
859 2019-04-07 Alan Modra <amodra@gmail.com>
862 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
863 (print_insn_neon, print_insn_arm): Likewise.
865 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
867 * i386-dis-evex.h (evex_table): Updated to support BF16
869 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
870 and EVEX_W_0F3872_P_3.
871 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
872 (cpu_flags): Add bitfield for CpuAVX512_BF16.
873 * i386-opc.h (enum): Add CpuAVX512_BF16.
874 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
875 * i386-opc.tbl: Add AVX512 BF16 instructions.
876 * i386-init.h: Regenerated.
877 * i386-tbl.h: Likewise.
879 2019-04-05 Alan Modra <amodra@gmail.com>
881 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
882 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
883 to favour printing of "-" branch hint when using the "y" bit.
884 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
886 2019-04-05 Alan Modra <amodra@gmail.com>
888 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
889 opcode until first operand is output.
891 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
894 * ppc-opc.c (valid_bo_pre_v2): Add comments.
895 (valid_bo_post_v2): Add support for 'at' branch hints.
896 (insert_bo): Only error on branch on ctr.
897 (get_bo_hint_mask): New function.
898 (insert_boe): Add new 'branch_taken' formal argument. Add support
899 for inserting 'at' branch hints.
900 (extract_boe): Add new 'branch_taken' formal argument. Add support
901 for extracting 'at' branch hints.
902 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
903 (BOE): Delete operand.
904 (BOM, BOP): New operands.
906 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
907 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
908 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
909 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
910 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
911 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
912 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
913 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
914 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
915 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
916 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
917 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
918 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
919 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
920 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
921 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
922 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
923 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
924 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
925 bttarl+>: New extended mnemonics.
927 2019-03-28 Alan Modra <amodra@gmail.com>
930 * ppc-opc.c (BTF): Define.
931 (powerpc_opcodes): Use for mtfsb*.
932 * ppc-dis.c (print_insn_powerpc): Print fields with both
933 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
935 2019-03-25 Tamar Christina <tamar.christina@arm.com>
937 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
938 (mapping_symbol_for_insn): Implement new algorithm.
939 (print_insn): Remove duplicate code.
941 2019-03-25 Tamar Christina <tamar.christina@arm.com>
943 * aarch64-dis.c (print_insn_aarch64):
946 2019-03-25 Tamar Christina <tamar.christina@arm.com>
948 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
951 2019-03-25 Tamar Christina <tamar.christina@arm.com>
953 * aarch64-dis.c (last_stop_offset): New.
954 (print_insn_aarch64): Use stop_offset.
956 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
959 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
961 * i386-init.h: Regenerated.
963 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
966 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
967 vmovdqu16, vmovdqu32 and vmovdqu64.
968 * i386-tbl.h: Regenerated.
970 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
972 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
973 from vstrszb, vstrszh, and vstrszf.
975 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
977 * s390-opc.txt: Add instruction descriptions.
979 2019-02-08 Jim Wilson <jimw@sifive.com>
981 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
984 2019-02-07 Tamar Christina <tamar.christina@arm.com>
986 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
988 2019-02-07 Tamar Christina <tamar.christina@arm.com>
991 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
992 * aarch64-opc.c (verify_elem_sd): New.
993 (fields): Add FLD_sz entr.
994 * aarch64-tbl.h (_SIMD_INSN): New.
995 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
996 fmulx scalar and vector by element isns.
998 2019-02-07 Nick Clifton <nickc@redhat.com>
1000 * po/sv.po: Updated Swedish translation.
1002 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1004 * s390-mkopc.c (main): Accept arch13 as cpu string.
1005 * s390-opc.c: Add new instruction formats and instruction opcode
1007 * s390-opc.txt: Add new arch13 instructions.
1009 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1011 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1012 (aarch64_opcode): Change encoding for stg, stzg
1014 * aarch64-asm-2.c: Regenerated.
1015 * aarch64-dis-2.c: Regenerated.
1016 * aarch64-opc-2.c: Regenerated.
1018 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1020 * aarch64-asm-2.c: Regenerated.
1021 * aarch64-dis-2.c: Likewise.
1022 * aarch64-opc-2.c: Likewise.
1023 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1025 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1026 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1028 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1029 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1030 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1031 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1032 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1033 case for ldstgv_indexed.
1034 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1035 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1036 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1037 * aarch64-asm-2.c: Regenerated.
1038 * aarch64-dis-2.c: Regenerated.
1039 * aarch64-opc-2.c: Regenerated.
1041 2019-01-23 Nick Clifton <nickc@redhat.com>
1043 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1045 2019-01-21 Nick Clifton <nickc@redhat.com>
1047 * po/de.po: Updated German translation.
1048 * po/uk.po: Updated Ukranian translation.
1050 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1051 * mips-dis.c (mips_arch_choices): Fix typo in
1052 gs464, gs464e and gs264e descriptors.
1054 2019-01-19 Nick Clifton <nickc@redhat.com>
1056 * configure: Regenerate.
1057 * po/opcodes.pot: Regenerate.
1059 2018-06-24 Nick Clifton <nickc@redhat.com>
1061 2.32 branch created.
1063 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1065 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1067 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1070 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1072 * configure: Regenerate.
1074 2019-01-07 Alan Modra <amodra@gmail.com>
1076 * configure: Regenerate.
1077 * po/POTFILES.in: Regenerate.
1079 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1081 * s12z-opc.c: New file.
1082 * s12z-opc.h: New file.
1083 * s12z-dis.c: Removed all code not directly related to display
1084 of instructions. Used the interface provided by the new files
1086 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1087 * Makefile.in: Regenerate.
1088 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1089 * configure: Regenerate.
1091 2019-01-01 Alan Modra <amodra@gmail.com>
1093 Update year range in copyright notice of all files.
1095 For older changes see ChangeLog-2018
1097 Copyright (C) 2019 Free Software Foundation, Inc.
1099 Copying and distribution of this file, with or without modification,
1100 are permitted in any medium without royalty provided the copyright
1101 notice and this notice are preserved.
1107 version-control: never