1 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
3 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
5 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
6 the AARCH64_MOD_MUL_VL entry.
7 (value_aligned_p): Cope with non-power-of-two alignments.
8 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
9 (print_immediate_offset_address): Likewise.
10 (aarch64_print_operand): Likewise.
11 * aarch64-opc-2.c: Regenerate.
12 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
13 (ins_sve_addr_ri_s9xvl): New inserters.
14 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
15 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
16 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
17 * aarch64-asm-2.c: Regenerate.
18 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
19 (ext_sve_addr_ri_s9xvl): New extractors.
20 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
21 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
22 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
23 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
24 * aarch64-dis-2.c: Regenerate.
26 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
28 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
30 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
31 (FLD_SVE_xs_22): New aarch64_field_kinds.
32 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
33 (get_operand_specific_data): New function.
34 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
35 FLD_SVE_xs_14 and FLD_SVE_xs_22.
36 (operand_general_constraint_met_p): Handle the new SVE address
39 (get_addr_sve_reg_name): New function.
40 (aarch64_print_operand): Handle the new SVE address operands.
41 * aarch64-opc-2.c: Regenerate.
42 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
43 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
44 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
45 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
46 (aarch64_ins_sve_addr_rr_lsl): Likewise.
47 (aarch64_ins_sve_addr_rz_xtw): Likewise.
48 (aarch64_ins_sve_addr_zi_u5): Likewise.
49 (aarch64_ins_sve_addr_zz): Likewise.
50 (aarch64_ins_sve_addr_zz_lsl): Likewise.
51 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
52 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
53 * aarch64-asm-2.c: Regenerate.
54 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
55 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
56 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
57 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
58 (aarch64_ext_sve_addr_ri_u6): Likewise.
59 (aarch64_ext_sve_addr_rr_lsl): Likewise.
60 (aarch64_ext_sve_addr_rz_xtw): Likewise.
61 (aarch64_ext_sve_addr_zi_u5): Likewise.
62 (aarch64_ext_sve_addr_zz): Likewise.
63 (aarch64_ext_sve_addr_zz_lsl): Likewise.
64 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
65 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
66 * aarch64-dis-2.c: Regenerate.
68 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
70 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
71 AARCH64_OPND_SVE_PATTERN_SCALED.
72 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
73 * aarch64-opc.c (fields): Add a corresponding entry.
74 (set_multiplier_out_of_range_error): New function.
75 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
76 (operand_general_constraint_met_p): Handle
77 AARCH64_OPND_SVE_PATTERN_SCALED.
78 (print_register_offset_address): Use PRIi64 to print the
80 (aarch64_print_operand): Likewise. Handle
81 AARCH64_OPND_SVE_PATTERN_SCALED.
82 * aarch64-opc-2.c: Regenerate.
83 * aarch64-asm.h (ins_sve_scale): New inserter.
84 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
85 * aarch64-asm-2.c: Regenerate.
86 * aarch64-dis.h (ext_sve_scale): New inserter.
87 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
88 * aarch64-dis-2.c: Regenerate.
90 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
92 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
93 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
94 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
95 (FLD_SVE_prfop): Likewise.
96 * aarch64-opc.c: Include libiberty.h.
97 (aarch64_sve_pattern_array): New variable.
98 (aarch64_sve_prfop_array): Likewise.
99 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
100 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
101 AARCH64_OPND_SVE_PRFOP.
102 * aarch64-asm-2.c: Regenerate.
103 * aarch64-dis-2.c: Likewise.
104 * aarch64-opc-2.c: Likewise.
106 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
108 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
109 AARCH64_OPND_QLF_P_[ZM].
110 (aarch64_print_operand): Print /z and /m where appropriate.
112 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
114 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
115 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
116 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
117 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
118 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
119 * aarch64-opc.c (fields): Add corresponding entries here.
120 (operand_general_constraint_met_p): Check that SVE register lists
121 have the correct length. Check the ranges of SVE index registers.
122 Check for cases where p8-p15 are used in 3-bit predicate fields.
123 (aarch64_print_operand): Handle the new SVE operands.
124 * aarch64-opc-2.c: Regenerate.
125 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
126 * aarch64-asm.c (aarch64_ins_sve_index): New function.
127 (aarch64_ins_sve_reglist): Likewise.
128 * aarch64-asm-2.c: Regenerate.
129 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
130 * aarch64-dis.c (aarch64_ext_sve_index): New function.
131 (aarch64_ext_sve_reglist): Likewise.
132 * aarch64-dis-2.c: Regenerate.
134 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
136 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
137 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
138 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
139 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
142 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
144 * aarch64-opc.c (get_offset_int_reg_name): New function.
145 (print_immediate_offset_address): Likewise.
146 (print_register_offset_address): Take the base and offset
147 registers as parameters.
148 (aarch64_print_operand): Update caller accordingly. Use
149 print_immediate_offset_address.
151 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
153 * aarch64-opc.c (BANK): New macro.
154 (R32, R64): Take a register number as argument
157 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
159 * aarch64-opc.c (print_register_list): Add a prefix parameter.
160 (aarch64_print_operand): Update accordingly.
162 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
164 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
166 * aarch64-asm.h (ins_fpimm): New inserter.
167 * aarch64-asm.c (aarch64_ins_fpimm): New function.
168 * aarch64-asm-2.c: Regenerate.
169 * aarch64-dis.h (ext_fpimm): New extractor.
170 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
171 (aarch64_ext_fpimm): New function.
172 * aarch64-dis-2.c: Regenerate.
174 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
176 * aarch64-asm.c: Include libiberty.h.
177 (insert_fields): New function.
178 (aarch64_ins_imm): Use it.
179 * aarch64-dis.c (extract_fields): New function.
180 (aarch64_ext_imm): Use it.
182 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
184 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
185 with an esize parameter.
186 (operand_general_constraint_met_p): Update accordingly.
187 Fix misindented code.
188 * aarch64-asm.c (aarch64_ins_limm): Update call to
189 aarch64_logical_immediate_p.
191 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
193 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
195 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
197 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
199 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
201 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
203 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
205 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
206 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
207 xor3>: Delete mnemonics.
208 <cp_abort>: Rename mnemonic from ...
209 <cpabort>: ...to this.
210 <setb>: Change to a X form instruction.
211 <sync>: Change to 1 operand form.
212 <copy>: Delete mnemonic.
213 <copy_first>: Rename mnemonic from ...
215 <paste, paste.>: Delete mnemonics.
216 <paste_last>: Rename mnemonic from ...
217 <paste.>: ...to this.
219 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
221 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
223 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
225 * s390-mkopc.c (main): Support alternate arch strings.
227 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
229 * s390-opc.txt: Fix kmctr instruction type.
231 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
233 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
234 * i386-init.h: Regenerated.
236 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
238 * opcodes/arc-dis.c (print_insn_arc): Changed.
240 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
242 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
245 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
247 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
248 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
249 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
251 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
254 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
255 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
256 PREFIX_MOD_3_0FAE_REG_4.
257 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
258 PREFIX_MOD_3_0FAE_REG_4.
259 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
260 (cpu_flags): Add CpuPTWRITE.
261 * i386-opc.h (CpuPTWRITE): New.
262 (i386_cpu_flags): Add cpuptwrite.
263 * i386-opc.tbl: Add ptwrite instruction.
264 * i386-init.h: Regenerated.
265 * i386-tbl.h: Likewise.
267 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
269 * arc-dis.h: Wrap around in extern "C".
271 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
273 * aarch64-tbl.h (V8_2_INSN): New macro.
274 (aarch64_opcode_table): Use it.
276 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
278 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
279 CORE_INSN, __FP_INSN and SIMD_INSN.
281 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
283 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
284 (aarch64_opcode_table): Update uses accordingly.
286 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
287 Kwok Cheung Yeung <kcy@codesourcery.com>
290 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
291 'e_cmplwi' to 'e_cmpli' instead.
292 (OPVUPRT, OPVUPRT_MASK): Define.
293 (powerpc_opcodes): Add E200Z4 insns.
294 (vle_opcodes): Add context save/restore insns.
296 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
298 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
299 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
302 2016-07-27 Graham Markall <graham.markall@embecosm.com>
304 * arc-nps400-tbl.h: Change block comments to GNU format.
305 * arc-dis.c: Add new globals addrtypenames,
306 addrtypenames_max, and addtypeunknown.
307 (get_addrtype): New function.
308 (print_insn_arc): Print colons and address types when
310 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
311 define insert and extract functions for all address types.
312 (arc_operands): Add operands for colon and all address
314 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
315 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
316 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
317 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
318 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
319 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
321 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
323 * configure: Regenerated.
325 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
327 * arc-dis.c (skipclass): New structure.
328 (decodelist): New variable.
329 (is_compatible_p): New function.
330 (new_element): Likewise.
331 (skip_class_p): Likewise.
332 (find_format_from_table): Use skip_class_p function.
333 (find_format): Decode first the extension instructions.
334 (print_insn_arc): Select either ARCEM or ARCHS based on elf
336 (parse_option): New function.
337 (parse_disassembler_options): Likewise.
338 (print_arc_disassembler_options): Likewise.
339 (print_insn_arc): Use parse_disassembler_options function. Proper
340 select ARCv2 cpu variant.
341 * disassemble.c (disassembler_usage): Add ARC disassembler
344 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
346 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
347 annotation from the "nal" entry and reorder it beyond "bltzal".
349 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
351 * sparc-opc.c (ldtxa): New macro.
352 (sparc_opcodes): Use the macro defined above to add entries for
353 the LDTXA instructions.
354 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
357 2016-07-07 James Bowman <james.bowman@ftdichip.com>
359 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
362 2016-07-01 Jan Beulich <jbeulich@suse.com>
364 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
365 (movzb): Adjust to cover all permitted suffixes.
367 * i386-tbl.h: Re-generate.
369 2016-07-01 Jan Beulich <jbeulich@suse.com>
371 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
372 (lgdt): Remove Tbyte from non-64-bit variant.
373 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
374 xsaves64, xsavec64): Remove Disp16.
375 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
376 Remove Disp32S from non-64-bit variants. Remove Disp16 from
378 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
379 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
380 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
382 * i386-tbl.h: Re-generate.
384 2016-07-01 Jan Beulich <jbeulich@suse.com>
386 * i386-opc.tbl (xlat): Remove RepPrefixOk.
387 * i386-tbl.h: Re-generate.
389 2016-06-30 Yao Qi <yao.qi@linaro.org>
391 * arm-dis.c (print_insn): Fix typo in comment.
393 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
395 * aarch64-opc.c (operand_general_constraint_met_p): Check the
396 range of ldst_elemlist operands.
397 (print_register_list): Use PRIi64 to print the index.
398 (aarch64_print_operand): Likewise.
400 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
402 * mcore-opc.h: Remove sentinal.
403 * mcore-dis.c (print_insn_mcore): Adjust.
405 2016-06-23 Graham Markall <graham.markall@embecosm.com>
407 * arc-opc.c: Correct description of availability of NPS400
410 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
412 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
413 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
414 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
415 xor3>: New mnemonics.
416 <setb>: Change to a VX form instruction.
417 (insert_sh6): Add support for rldixor.
418 (extract_sh6): Likewise.
420 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
422 * arc-ext.h: Wrap in extern C.
424 2016-06-21 Graham Markall <graham.markall@embecosm.com>
426 * arc-dis.c (arc_insn_length): Add comment on instruction length.
427 Use same method for determining instruction length on ARC700 and
429 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
430 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
431 with the NPS400 subclass.
432 * arc-opc.c: Likewise.
434 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
436 * sparc-opc.c (rdasr): New macro.
442 (sparc_opcodes): Use the macros above to fix and expand the
443 definition of read/write instructions from/to
444 asr/privileged/hyperprivileged instructions.
445 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
446 %hva_mask_nz. Prefer softint_set and softint_clear over
447 set_softint and clear_softint.
448 (print_insn_sparc): Support %ver in Rd.
450 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
452 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
453 architecture according to the hardware capabilities they require.
455 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
457 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
458 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
459 bfd_mach_sparc_v9{c,d,e,v,m}.
460 * sparc-opc.c (MASK_V9C): Define.
461 (MASK_V9D): Likewise.
462 (MASK_V9E): Likewise.
463 (MASK_V9V): Likewise.
464 (MASK_V9M): Likewise.
465 (v6): Add MASK_V9{C,D,E,V,M}.
466 (v6notlet): Likewise.
470 (v9andleon): Likewise.
478 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
480 2016-06-15 Nick Clifton <nickc@redhat.com>
482 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
483 constants to match expected behaviour.
484 (nds32_parse_opcode): Likewise. Also for whitespace.
486 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
488 * arc-opc.c (extract_rhv1): Extract value from insn.
490 2016-06-14 Graham Markall <graham.markall@embecosm.com>
492 * arc-nps400-tbl.h: Add ldbit instruction.
493 * arc-opc.c: Add flag classes required for ldbit.
495 2016-06-14 Graham Markall <graham.markall@embecosm.com>
497 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
498 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
499 support the above instructions.
501 2016-06-14 Graham Markall <graham.markall@embecosm.com>
503 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
504 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
505 csma, cbba, zncv, and hofs.
506 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
507 support the above instructions.
509 2016-06-06 Graham Markall <graham.markall@embecosm.com>
511 * arc-nps400-tbl.h: Add andab and orab instructions.
513 2016-06-06 Graham Markall <graham.markall@embecosm.com>
515 * arc-nps400-tbl.h: Add addl-like instructions.
517 2016-06-06 Graham Markall <graham.markall@embecosm.com>
519 * arc-nps400-tbl.h: Add mxb and imxb instructions.
521 2016-06-06 Graham Markall <graham.markall@embecosm.com>
523 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
526 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
528 * s390-dis.c (option_use_insn_len_bits_p): New file scope
530 (init_disasm): Handle new command line option "insnlength".
531 (print_s390_disassembler_options): Mention new option in help
533 (print_insn_s390): Use the encoded insn length when dumping
534 unknown instructions.
536 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
538 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
539 to the address and set as symbol address for LDS/ STS immediate operands.
541 2016-06-07 Alan Modra <amodra@gmail.com>
543 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
544 cpu for "vle" to e500.
545 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
546 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
547 (PPCNONE): Delete, substitute throughout.
548 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
549 except for major opcode 4 and 31.
550 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
552 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
554 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
555 ARM_EXT_RAS in relevant entries.
557 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
560 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
563 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
566 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
568 Add comments for '&'.
569 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
571 (intel_operand_size): Handle indir_v_mode.
572 (OP_E_register): Likewise.
573 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
574 64-bit indirect call/jmp for AMD64.
575 * i386-tbl.h: Regenerated
577 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
579 * arc-dis.c (struct arc_operand_iterator): New structure.
580 (find_format_from_table): All the old content from find_format,
581 with some minor adjustments, and parameter renaming.
582 (find_format_long_instructions): New function.
583 (find_format): Rewritten.
584 (arc_insn_length): Add LSB parameter.
585 (extract_operand_value): New function.
586 (operand_iterator_next): New function.
587 (print_insn_arc): Use new functions to find opcode, and iterator
589 * arc-opc.c (insert_nps_3bit_dst_short): New function.
590 (extract_nps_3bit_dst_short): New function.
591 (insert_nps_3bit_src2_short): New function.
592 (extract_nps_3bit_src2_short): New function.
593 (insert_nps_bitop1_size): New function.
594 (extract_nps_bitop1_size): New function.
595 (insert_nps_bitop2_size): New function.
596 (extract_nps_bitop2_size): New function.
597 (insert_nps_bitop_mod4_msb): New function.
598 (extract_nps_bitop_mod4_msb): New function.
599 (insert_nps_bitop_mod4_lsb): New function.
600 (extract_nps_bitop_mod4_lsb): New function.
601 (insert_nps_bitop_dst_pos3_pos4): New function.
602 (extract_nps_bitop_dst_pos3_pos4): New function.
603 (insert_nps_bitop_ins_ext): New function.
604 (extract_nps_bitop_ins_ext): New function.
605 (arc_operands): Add new operands.
606 (arc_long_opcodes): New global array.
607 (arc_num_long_opcodes): New global.
608 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
610 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
612 * nds32-asm.h: Add extern "C".
613 * sh-opc.h: Likewise.
615 2016-06-01 Graham Markall <graham.markall@embecosm.com>
617 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
618 0,b,limm to the rflt instruction.
620 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
622 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
625 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
628 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
629 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
630 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
631 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
632 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
633 * i386-init.h: Regenerated.
635 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
638 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
639 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
640 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
641 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
642 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
643 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
644 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
645 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
646 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
647 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
648 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
649 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
650 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
651 CpuRegMask for AVX512.
652 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
654 (set_bitfield_from_cpu_flag_init): New function.
655 (set_bitfield): Remove const on f. Call
656 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
657 * i386-opc.h (CpuRegMMX): New.
658 (CpuRegXMM): Likewise.
659 (CpuRegYMM): Likewise.
660 (CpuRegZMM): Likewise.
661 (CpuRegMask): Likewise.
662 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
664 * i386-init.h: Regenerated.
665 * i386-tbl.h: Likewise.
667 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
670 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
671 (opcode_modifiers): Add AMD64 and Intel64.
672 (main): Properly verify CpuMax.
673 * i386-opc.h (CpuAMD64): Removed.
674 (CpuIntel64): Likewise.
675 (CpuMax): Set to CpuNo64.
676 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
679 (i386_opcode_modifier): Add amd64 and intel64.
680 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
682 * i386-init.h: Regenerated.
683 * i386-tbl.h: Likewise.
685 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
688 * i386-gen.c (main): Fail if CpuMax is incorrect.
689 * i386-opc.h (CpuMax): Set to CpuIntel64.
690 * i386-tbl.h: Regenerated.
692 2016-05-27 Nick Clifton <nickc@redhat.com>
695 * msp430-dis.c (msp430dis_read_two_bytes): New function.
696 (msp430dis_opcode_unsigned): New function.
697 (msp430dis_opcode_signed): New function.
698 (msp430_singleoperand): Use the new opcode reading functions.
699 Only disassenmble bytes if they were successfully read.
700 (msp430_doubleoperand): Likewise.
701 (msp430_branchinstr): Likewise.
702 (msp430x_callx_instr): Likewise.
703 (print_insn_msp430): Check that it is safe to read bytes before
704 attempting disassembly. Use the new opcode reading functions.
706 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
708 * ppc-opc.c (CY): New define. Document it.
709 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
711 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
713 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
714 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
715 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
716 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
718 * i386-init.h: Regenerated.
720 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
723 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
724 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
725 * i386-init.h: Regenerated.
727 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
729 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
730 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
731 * i386-init.h: Regenerated.
733 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
735 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
737 (print_insn_arc): Set insn_type information.
738 * arc-opc.c (C_CC): Add F_CLASS_COND.
739 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
740 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
741 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
742 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
743 (brne, brne_s, jeq_s, jne_s): Likewise.
745 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
747 * arc-tbl.h (neg): New instruction variant.
749 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
751 * arc-dis.c (find_format, find_format, get_auxreg)
752 (print_insn_arc): Changed.
753 * arc-ext.h (INSERT_XOP): Likewise.
755 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
757 * tic54x-dis.c (sprint_mmr): Adjust.
758 * tic54x-opc.c: Likewise.
760 2016-05-19 Alan Modra <amodra@gmail.com>
762 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
764 2016-05-19 Alan Modra <amodra@gmail.com>
766 * ppc-opc.c: Formatting.
767 (NSISIGNOPT): Define.
768 (powerpc_opcodes <subis>): Use NSISIGNOPT.
770 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
772 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
773 replacing references to `micromips_ase' throughout.
774 (_print_insn_mips): Don't use file-level microMIPS annotation to
775 determine the disassembly mode with the symbol table.
777 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
779 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
781 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
783 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
785 * mips-opc.c (D34): New macro.
786 (mips_builtin_opcodes): Define bposge32c for DSPr3.
788 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
790 * i386-dis.c (prefix_table): Add RDPID instruction.
791 * i386-gen.c (cpu_flag_init): Add RDPID flag.
792 (cpu_flags): Add RDPID bitfield.
793 * i386-opc.h (enum): Add RDPID element.
794 (i386_cpu_flags): Add RDPID field.
795 * i386-opc.tbl: Add RDPID instruction.
796 * i386-init.h: Regenerate.
797 * i386-tbl.h: Regenerate.
799 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
801 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
802 branch type of a symbol.
803 (print_insn): Likewise.
805 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
807 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
808 Mainline Security Extensions instructions.
809 (thumb_opcodes): Add entries for narrow ARMv8-M Security
810 Extensions instructions.
811 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
813 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
816 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
818 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
820 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
822 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
823 (arcExtMap_genOpcode): Likewise.
824 * arc-opc.c (arg_32bit_rc): Define new variable.
825 (arg_32bit_u6): Likewise.
826 (arg_32bit_limm): Likewise.
828 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
830 * aarch64-gen.c (VERIFIER): Define.
831 * aarch64-opc.c (VERIFIER): Define.
832 (verify_ldpsw): Use static linkage.
833 * aarch64-opc.h (verify_ldpsw): Remove.
834 * aarch64-tbl.h: Use VERIFIER for verifiers.
836 2016-04-28 Nick Clifton <nickc@redhat.com>
839 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
840 * aarch64-opc.c (verify_ldpsw): New function.
841 * aarch64-opc.h (verify_ldpsw): New prototype.
842 * aarch64-tbl.h: Add initialiser for verifier field.
843 (LDPSW): Set verifier to verify_ldpsw.
845 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
849 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
850 smaller than address size.
852 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
854 * alpha-dis.c: Regenerate.
855 * crx-dis.c: Likewise.
856 * disassemble.c: Likewise.
857 * epiphany-opc.c: Likewise.
858 * fr30-opc.c: Likewise.
859 * frv-opc.c: Likewise.
860 * ip2k-opc.c: Likewise.
861 * iq2000-opc.c: Likewise.
862 * lm32-opc.c: Likewise.
863 * lm32-opinst.c: Likewise.
864 * m32c-opc.c: Likewise.
865 * m32r-opc.c: Likewise.
866 * m32r-opinst.c: Likewise.
867 * mep-opc.c: Likewise.
868 * mt-opc.c: Likewise.
869 * or1k-opc.c: Likewise.
870 * or1k-opinst.c: Likewise.
871 * tic80-opc.c: Likewise.
872 * xc16x-opc.c: Likewise.
873 * xstormy16-opc.c: Likewise.
875 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
877 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
878 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
879 calcsd, and calcxd instructions.
880 * arc-opc.c (insert_nps_bitop_size): Delete.
881 (extract_nps_bitop_size): Delete.
882 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
883 (extract_nps_qcmp_m3): Define.
884 (extract_nps_qcmp_m2): Define.
885 (extract_nps_qcmp_m1): Define.
886 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
887 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
888 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
889 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
890 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
893 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
895 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
897 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
899 * Makefile.in: Regenerated with automake 1.11.6.
900 * aclocal.m4: Likewise.
902 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
904 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
906 * arc-opc.c (insert_nps_cmem_uimm16): New function.
907 (extract_nps_cmem_uimm16): New function.
908 (arc_operands): Add NPS_XLDST_UIMM16 operand.
910 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
912 * arc-dis.c (arc_insn_length): New function.
913 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
914 (find_format): Change insnLen parameter to unsigned.
916 2016-04-13 Nick Clifton <nickc@redhat.com>
919 * v850-opc.c (v850_opcodes): Correct masks for long versions of
920 the LD.B and LD.BU instructions.
922 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
924 * arc-dis.c (find_format): Check for extension flags.
925 (print_flags): New function.
926 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
928 * arc-ext.c (arcExtMap_coreRegName): Use
929 LAST_EXTENSION_CORE_REGISTER.
930 (arcExtMap_coreReadWrite): Likewise.
931 (dump_ARC_extmap): Update printing.
932 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
933 (arc_aux_regs): Add cpu field.
934 * arc-regs.h: Add cpu field, lower case name aux registers.
936 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
938 * arc-tbl.h: Add rtsc, sleep with no arguments.
940 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
942 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
944 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
945 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
946 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
947 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
948 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
949 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
950 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
951 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
952 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
953 (arc_opcode arc_opcodes): Null terminate the array.
954 (arc_num_opcodes): Remove.
955 * arc-ext.h (INSERT_XOP): Define.
956 (extInstruction_t): Likewise.
957 (arcExtMap_instName): Delete.
958 (arcExtMap_insn): New function.
959 (arcExtMap_genOpcode): Likewise.
960 * arc-ext.c (ExtInstruction): Remove.
961 (create_map): Zero initialize instruction fields.
962 (arcExtMap_instName): Remove.
963 (arcExtMap_insn): New function.
964 (dump_ARC_extmap): More info while debuging.
965 (arcExtMap_genOpcode): New function.
966 * arc-dis.c (find_format): New function.
967 (print_insn_arc): Use find_format.
968 (arc_get_disassembler): Enable dump_ARC_extmap only when
971 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
973 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
974 instruction bits out.
976 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
978 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
979 * arc-opc.c (arc_flag_operands): Add new flags.
980 (arc_flag_classes): Add new classes.
982 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
984 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
986 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
988 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
989 encode1, rflt, crc16, and crc32 instructions.
990 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
991 (arc_flag_classes): Add C_NPS_R.
992 (insert_nps_bitop_size_2b): New function.
993 (extract_nps_bitop_size_2b): Likewise.
994 (insert_nps_bitop_uimm8): Likewise.
995 (extract_nps_bitop_uimm8): Likewise.
996 (arc_operands): Add new operand entries.
998 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1000 * arc-regs.h: Add a new subclass field. Add double assist
1001 accumulator register values.
1002 * arc-tbl.h: Use DPA subclass to mark the double assist
1003 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1004 * arc-opc.c (RSP): Define instead of SP.
1005 (arc_aux_regs): Add the subclass field.
1007 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1009 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1011 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1013 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1016 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1018 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1019 issues. No functional changes.
1021 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1023 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1024 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1025 (RTT): Remove duplicate.
1026 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1027 (PCT_CONFIG*): Remove.
1028 (D1L, D1H, D2H, D2L): Define.
1030 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1032 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1034 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1036 * arc-tbl.h (invld07): Remove.
1037 * arc-ext-tbl.h: New file.
1038 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1039 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1041 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1043 Fix -Wstack-usage warnings.
1044 * aarch64-dis.c (print_operands): Substitute size.
1045 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1047 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1049 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1050 to get a proper diagnostic when an invalid ASR register is used.
1052 2016-03-22 Nick Clifton <nickc@redhat.com>
1054 * configure: Regenerate.
1056 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1058 * arc-nps400-tbl.h: New file.
1059 * arc-opc.c: Add top level comment.
1060 (insert_nps_3bit_dst): New function.
1061 (extract_nps_3bit_dst): New function.
1062 (insert_nps_3bit_src2): New function.
1063 (extract_nps_3bit_src2): New function.
1064 (insert_nps_bitop_size): New function.
1065 (extract_nps_bitop_size): New function.
1066 (arc_flag_operands): Add nps400 entries.
1067 (arc_flag_classes): Add nps400 entries.
1068 (arc_operands): Add nps400 entries.
1069 (arc_opcodes): Add nps400 include.
1071 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1073 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1074 the new class enum values.
1076 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1078 * arc-dis.c (print_insn_arc): Handle nps400.
1080 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1082 * arc-opc.c (BASE): Delete.
1084 2016-03-18 Nick Clifton <nickc@redhat.com>
1087 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1088 of MOV insn that aliases an ORR insn.
1090 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1092 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1094 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1096 * mcore-opc.h: Add const qualifiers.
1097 * microblaze-opc.h (struct op_code_struct): Likewise.
1098 * sh-opc.h: Likewise.
1099 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1100 (tic4x_print_op): Likewise.
1102 2016-03-02 Alan Modra <amodra@gmail.com>
1104 * or1k-desc.h: Regenerate.
1105 * fr30-ibld.c: Regenerate.
1106 * rl78-decode.c: Regenerate.
1108 2016-03-01 Nick Clifton <nickc@redhat.com>
1111 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1113 2016-02-24 Renlin Li <renlin.li@arm.com>
1115 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1116 (print_insn_coprocessor): Support fp16 instructions.
1118 2016-02-24 Renlin Li <renlin.li@arm.com>
1120 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1121 vminnm, vrint(mpna).
1123 2016-02-24 Renlin Li <renlin.li@arm.com>
1125 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1126 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1128 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386-dis.c (print_insn): Parenthesize expression to prevent
1131 truncated addresses.
1134 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1135 Janek van Oirschot <jvanoirs@synopsys.com>
1137 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1140 2016-02-04 Nick Clifton <nickc@redhat.com>
1143 * msp430-dis.c (print_insn_msp430): Add a special case for
1144 decoding an RRC instruction with the ZC bit set in the extension
1147 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1149 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1150 * epiphany-ibld.c: Regenerate.
1151 * fr30-ibld.c: Regenerate.
1152 * frv-ibld.c: Regenerate.
1153 * ip2k-ibld.c: Regenerate.
1154 * iq2000-ibld.c: Regenerate.
1155 * lm32-ibld.c: Regenerate.
1156 * m32c-ibld.c: Regenerate.
1157 * m32r-ibld.c: Regenerate.
1158 * mep-ibld.c: Regenerate.
1159 * mt-ibld.c: Regenerate.
1160 * or1k-ibld.c: Regenerate.
1161 * xc16x-ibld.c: Regenerate.
1162 * xstormy16-ibld.c: Regenerate.
1164 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1166 * epiphany-dis.c: Regenerated from latest cpu files.
1168 2016-02-01 Michael McConville <mmcco@mykolab.com>
1170 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1173 2016-01-25 Renlin Li <renlin.li@arm.com>
1175 * arm-dis.c (mapping_symbol_for_insn): New function.
1176 (find_ifthen_state): Call mapping_symbol_for_insn().
1178 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1180 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1181 of MSR UAO immediate operand.
1183 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1185 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1186 instruction support.
1188 2016-01-17 Alan Modra <amodra@gmail.com>
1190 * configure: Regenerate.
1192 2016-01-14 Nick Clifton <nickc@redhat.com>
1194 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1195 instructions that can support stack pointer operations.
1196 * rl78-decode.c: Regenerate.
1197 * rl78-dis.c: Fix display of stack pointer in MOVW based
1200 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1202 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1203 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1204 erxtatus_el1 and erxaddr_el1.
1206 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1208 * arm-dis.c (arm_opcodes): Add "esb".
1209 (thumb_opcodes): Likewise.
1211 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1213 * ppc-opc.c <xscmpnedp>: Delete.
1214 <xvcmpnedp>: Likewise.
1215 <xvcmpnedp.>: Likewise.
1216 <xvcmpnesp>: Likewise.
1217 <xvcmpnesp.>: Likewise.
1219 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1222 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1225 2016-01-01 Alan Modra <amodra@gmail.com>
1227 Update year range in copyright notice of all files.
1229 For older changes see ChangeLog-2015
1231 Copyright (C) 2016 Free Software Foundation, Inc.
1233 Copying and distribution of this file, with or without modification,
1234 are permitted in any medium without royalty provided the copyright
1235 notice and this notice are preserved.
1241 version-control: never