1 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
7 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
8 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
10 2015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
12 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
13 and adjust calculation to ignore qualifier for type 2H.
14 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
16 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
18 * aarch64-asm-2.c: Regenerate.
19 * aarch64-dis-2.c: Regenerate.
20 * aarch64-opc-2.c: Regenerate.
21 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
22 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
23 modified immediate group.
25 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
27 * aarch64-asm-2.c: Regenerate.
28 * aarch64-dis-2.c: Regenerate.
29 * aarch64-opc-2.c: Regenerate.
30 * aarch64-tbl.h (QL_XLANES_FP_H): New.
31 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
32 fminnmv, fminv to the Adv.SIMD across lanes group.
34 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Regenerate.
38 * aarch64-opc-2.c: Regenerate.
39 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
40 fmls, fmul and fmulx to the scalar indexed element group.
42 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
44 * aarch64-asm-2.c: Regenerate.
45 * aarch64-dis-2.c: Regenerate.
46 * aarch64-opc-2.c: Regenerate.
47 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
48 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
49 fmulx to the vector indexed element group.
51 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
53 * aarch64-asm-2.c: Regenerate.
54 * aarch64-dis-2.c: Regenerate.
55 * aarch64-opc-2.c: Regenerate.
56 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
58 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
59 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
60 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
61 fcvtzu and frsqrte to the scalar two register misc. group.
63 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
65 * aarch64-asm-2.c: Regenerate.
66 * aarch64-dis-2.c: Regenerate.
67 * aarch64-opc-2.c: Regenerate.
68 * aarch64-tbl.h (QL_V2SAMEH): New.
69 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
70 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
71 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
72 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
73 and fsqrt to the vector register misc. group.
75 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
77 * aarch64-asm-2.c: Regenerate.
78 * aarch64-dis-2.c: Regenerate.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
81 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
82 to the scalar three same group.
84 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
86 * aarch64-asm-2.c: Regenerate.
87 * aarch64-dis-2.c: Regenerate.
88 * aarch64-opc-2.c: Regenerate.
89 * aarch64-tbl.h (QL_V3SAMEH): New.
90 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
91 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
92 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
93 fcmgt, facgt and fminp to the vector three same group.
95 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
97 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
100 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
102 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
104 (aarch64_pstatefield_supported_p): Move feature checks for AT
106 (aarch64_sys_ins_reg_supported_p): .. to here.
108 2015-12-12 Alan Modra <amodra@gmail.com>
111 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
112 (powerpc_opcodes): Remove single-operand mfcr.
114 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
116 * aarch64-asm.c (aarch64_ins_hint): New.
117 * aarch64-asm.h (aarch64_ins_hint): Declare.
118 * aarch64-dis.c (aarch64_ext_hint): New.
119 * aarch64-dis.h (aarch64_ext_hint): Declare.
120 * aarch64-opc-2.c: Regenerate.
121 * aarch64-opc.c (aarch64_hint_options): New.
122 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
124 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
126 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
128 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
130 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
131 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
132 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
134 (aarch64_sys_reg_supported_p): Add architecture feature tests for
137 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
139 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
140 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
141 feature test for "s1e1rp" and "s1e1wp".
143 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
145 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
146 (aarch64_sys_ins_reg_supported_p): New.
148 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
150 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
151 with aarch64_sys_ins_reg_has_xt.
152 (aarch64_ext_sysins_op): Likewise.
153 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
155 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
156 (aarch64_sys_regs_dc): Likewise.
157 (aarch64_sys_regs_at): Likewise.
158 (aarch64_sys_regs_tlbi): Likewise.
159 (aarch64_sys_ins_reg_has_xt): New.
161 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
163 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
164 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
165 (aarch64_pstatefields): Add "uao".
166 (aarch64_pstatefield_supported_p): Add checks for "uao".
168 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
170 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
171 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
172 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
173 (aarch64_sys_reg_supported_p): Add architecture feature tests for
176 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
178 * aarch64-asm-2.c: Regenerate.
179 * aarch64-dis-2.c: Regenerate.
180 * aarch64-tbl.h (aarch64_feature_ras): New.
182 (aarch64_opcode_table): Add "esb".
184 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
186 * i386-dis.c (MOD_0F01_REG_5): New.
187 (RM_0F01_REG_5): Likewise.
188 (reg_table): Use MOD_0F01_REG_5.
189 (mod_table): Add MOD_0F01_REG_5.
190 (rm_table): Add RM_0F01_REG_5.
191 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
192 (cpu_flags): Add CpuOSPKE.
193 * i386-opc.h (CpuOSPKE): New.
194 (i386_cpu_flags): Add cpuospke.
195 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
196 * i386-init.h: Regenerated.
197 * i386-tbl.h: Likewise.
199 2015-12-07 DJ Delorie <dj@redhat.com>
201 * rl78-decode.opc: Enable MULU for all ISAs.
202 * rl78-decode.c: Regenerate.
204 2015-12-07 Alan Modra <amodra@gmail.com>
206 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
209 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
211 * arc-dis.c (special_flag_p): Match full mnemonic.
212 * arc-opc.c (print_insn_arc): Check section size to read
213 appropriate number of bytes. Fix printing.
214 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
217 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
219 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
222 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Regenerate.
226 * aarch64-opc-2.c: Regenerate.
227 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
228 (QL_INT2FP_H, QL_FP2INT_H): New.
229 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
232 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
233 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
234 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
235 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
236 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
237 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
240 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
242 * aarch64-opc.c (half_conv_t): New.
243 (expand_fp_imm): Replace is_dp flag with the parameter size to
244 specify the number of bytes for the required expansion. Treat
245 a 16-bit expansion like a 32-bit expansion. Add check for an
246 unsupported size request. Update comment.
247 (aarch64_print_operand): Update to support 16-bit floating point
248 values. Update for changes to expand_fp_imm.
250 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
252 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
255 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
257 * aarch64-asm-2.c: Regenerate.
258 * aarch64-dis-2.c: Regenerate.
259 * aarch64-opc-2.c: Regenerate.
260 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
263 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
265 * aarch64-asm-2.c: Regenerate.
266 * aarch64-asm.c (convert_bfc_to_bfm): New.
267 (convert_to_real): Add case for OP_BFC.
268 * aarch64-dis-2.c: Regenerate.
269 * aarch64-dis.c: (convert_bfm_to_bfc): New.
270 (convert_to_alias): Add case for OP_BFC.
271 * aarch64-opc-2.c: Regenerate.
272 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
273 to allow width operand in three-operand instructions.
274 * aarch64-tbl.h (QL_BF1): New.
275 (aarch64_feature_v8_2): New.
277 (aarch64_opcode_table): Add "bfc".
279 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
281 * aarch64-asm-2.c: Regenerate.
282 * aarch64-dis-2.c: Regenerate.
283 * aarch64-dis.c: Weaken assert.
284 * aarch64-gen.c: Include the instruction in the list of its
287 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
289 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
290 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
293 2015-11-23 Tristan Gingold <gingold@adacore.com>
295 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
297 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
299 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
300 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
301 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
302 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
303 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
304 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
305 cnthv_ctl_el2, cnthv_cval_el2.
306 (aarch64_sys_reg_supported_p): Update for the new system
309 2015-11-20 Nick Clifton <nickc@redhat.com>
312 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
314 2015-11-20 Nick Clifton <nickc@redhat.com>
316 * po/zh_CN.po: Updated simplified Chinese translation.
318 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
320 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
321 of MSR PAN immediate operand.
323 2015-11-16 Nick Clifton <nickc@redhat.com>
325 * rx-dis.c (condition_names): Replace always and never with
326 invalid, since the always/never conditions can never be legal.
328 2015-11-13 Tristan Gingold <gingold@adacore.com>
330 * configure: Regenerate.
332 2015-11-11 Alan Modra <amodra@gmail.com>
333 Peter Bergner <bergner@vnet.ibm.com>
335 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
336 Add PPC_OPCODE_VSX3 to the vsx entry.
337 (powerpc_init_dialect): Set default dialect to power9.
338 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
339 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
340 extract_l1 insert_xtq6, extract_xtq6): New static functions.
341 (insert_esync): Test for illegal L operand value.
342 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
343 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
344 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
345 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
346 PPCVSX3): New defines.
347 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
348 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
349 <mcrxr>: Use XBFRARB_MASK.
350 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
351 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
352 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
353 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
354 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
355 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
356 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
357 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
358 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
359 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
360 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
361 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
362 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
363 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
364 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
365 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
366 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
367 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
368 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
369 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
370 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
371 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
372 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
373 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
374 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
375 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
376 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
377 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
378 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
379 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
380 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
381 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
383 2015-11-02 Nick Clifton <nickc@redhat.com>
385 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
387 * rx-decode.c: Regenerate.
389 2015-11-02 Nick Clifton <nickc@redhat.com>
391 * rx-decode.opc (rx_disp): If the displacement is zero, set the
392 type to RX_Operand_Zero_Indirect.
393 * rx-decode.c: Regenerate.
394 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
396 2015-10-28 Yao Qi <yao.qi@linaro.org>
398 * aarch64-dis.c (aarch64_decode_insn): Add one argument
399 noaliases_p. Update comments. Pass noaliases_p rather than
400 no_aliases to aarch64_opcode_decode.
401 (print_insn_aarch64_word): Pass no_aliases to
404 2015-10-27 Vinay <Vinay.G@kpit.com>
407 * rl78-decode.opc (MOV): Added offset to DE register in index
409 * rl78-decode.c: Regenerate.
411 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
414 * rl78-decode.opc: Add 's' print operator to instructions that
415 access system registers.
416 * rl78-decode.c: Regenerate.
417 * rl78-dis.c (print_insn_rl78_common): Decode all system
420 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
423 * rl78-decode.opc: Add 'a' print operator to mov instructions
424 using stack pointer plus index addressing.
425 * rl78-decode.c: Regenerate.
427 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
429 * s390-opc.c: Fix comment.
430 * s390-opc.txt: Change instruction type for troo, trot, trto, and
431 trtt to RRF_U0RER since the second parameter does not need to be a
434 2015-10-08 Nick Clifton <nickc@redhat.com>
436 * arc-dis.c (print_insn_arc): Initiallise insn array.
438 2015-10-07 Yao Qi <yao.qi@linaro.org>
440 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
441 'name' rather than 'template'.
442 * aarch64-opc.c (aarch64_print_operand): Likewise.
444 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
446 * arc-dis.c: Revamped file for ARC support
447 * arc-dis.h: Likewise.
448 * arc-ext.c: Likewise.
449 * arc-ext.h: Likewise.
450 * arc-opc.c: Likewise.
451 * arc-fxi.h: New file.
452 * arc-regs.h: Likewise.
453 * arc-tbl.h: Likewise.
455 2015-10-02 Yao Qi <yao.qi@linaro.org>
457 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
458 argument insn type to aarch64_insn. Rename to ...
459 (aarch64_decode_insn): ... it.
460 (print_insn_aarch64_word): Caller updated.
462 2015-10-02 Yao Qi <yao.qi@linaro.org>
464 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
465 (print_insn_aarch64_word): Caller updated.
467 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
469 * s390-mkopc.c (main): Parse htm and vx flag.
470 * s390-opc.txt: Mark instructions from the hardware transactional
471 memory and vector facilities with the "htm"/"vx" flag.
473 2015-09-28 Nick Clifton <nickc@redhat.com>
475 * po/de.po: Updated German translation.
477 2015-09-28 Tom Rix <tom@bumblecow.com>
479 * ppc-opc.c (PPC500): Mark some opcodes as invalid
481 2015-09-23 Nick Clifton <nickc@redhat.com>
483 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
485 * tic30-dis.c (print_branch): Likewise.
486 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
487 value before left shifting.
488 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
489 * hppa-dis.c (print_insn_hppa): Likewise.
490 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
492 * msp430-dis.c (msp430_singleoperand): Likewise.
493 (msp430_doubleoperand): Likewise.
494 (print_insn_msp430): Likewise.
495 * nds32-asm.c (parse_operand): Likewise.
496 * sh-opc.h (MASK): Likewise.
497 * v850-dis.c (get_operand_value): Likewise.
499 2015-09-22 Nick Clifton <nickc@redhat.com>
501 * rx-decode.opc (bwl): Use RX_Bad_Size.
503 (ubwl): Likewise. Rename to ubw.
504 (uBWL): Rename to uBW.
505 Replace all references to uBWL with uBW.
506 * rx-decode.c: Regenerate.
507 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
508 (opsize_names): Likewise.
509 (print_insn_rx): Detect and report RX_Bad_Size.
511 2015-09-22 Anton Blanchard <anton@samba.org>
513 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
515 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
517 * sparc-dis.c (print_insn_sparc): Handle the privileged register
520 2015-08-24 Jan Stancek <jstancek@redhat.com>
522 * i386-dis.c (print_insn): Fix decoding of three byte operands.
524 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
527 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
528 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
529 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
530 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
531 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
532 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
533 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
534 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
535 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
536 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
537 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
538 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
539 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
540 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
541 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
542 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
543 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
544 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
545 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
546 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
547 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
548 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
549 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
550 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
551 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
552 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
553 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
554 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
555 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
556 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
557 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
558 (vex_w_table): Replace terminals with MOD_TABLE entries for
559 most of mask instructions.
561 2015-08-17 Alan Modra <amodra@gmail.com>
563 * cgen.sh: Trim trailing space from cgen output.
564 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
565 (print_dis_table): Likewise.
566 * opc2c.c (dump_lines): Likewise.
567 (orig_filename): Warning fix.
568 * ia64-asmtab.c: Regenerate.
570 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
572 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
573 and higher with ARM instruction set will now mark the 26-bit
574 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
575 (arm_opcodes): Fix for unpredictable nop being recognized as a
578 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
580 * micromips-opc.c (micromips_opcodes): Re-order table so that move
581 based on 'or' is first.
582 * mips-opc.c (mips_builtin_opcodes): Ditto.
584 2015-08-11 Nick Clifton <nickc@redhat.com>
587 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
590 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
592 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
594 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
596 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
597 * i386-init.h: Regenerated.
599 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
602 * i386-dis.c (MOD_0FC3): New.
603 (PREFIX_0FC3): Renamed to ...
604 (PREFIX_MOD_0_0FC3): This.
605 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
606 (prefix_table): Replace Ma with Ev on movntiS.
607 (mod_table): Add MOD_0FC3.
609 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
611 * configure: Regenerated.
613 2015-07-23 Alan Modra <amodra@gmail.com>
616 * i386-dis.c (get64): Avoid signed integer overflow.
618 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
621 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
622 "EXEvexHalfBcstXmmq" for the second operand.
623 (EVEX_W_0F79_P_2): Likewise.
624 (EVEX_W_0F7A_P_2): Likewise.
625 (EVEX_W_0F7B_P_2): Likewise.
627 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
629 * arm-dis.c (print_insn_coprocessor): Added support for quarter
630 float bitfield format.
631 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
632 quarter float bitfield format.
634 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
636 * configure: Regenerated.
638 2015-07-03 Alan Modra <amodra@gmail.com>
640 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
641 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
642 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
644 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
645 Cesar Philippidis <cesar@codesourcery.com>
647 * nios2-dis.c (nios2_extract_opcode): New.
648 (nios2_disassembler_state): New.
649 (nios2_find_opcode_hash): Use mach parameter to select correct
651 (nios2_print_insn_arg): Extend to support new R2 argument letters
653 (print_insn_nios2): Check for 16-bit instruction at end of memory.
654 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
655 (NIOS2_NUM_OPCODES): Rename to...
656 (NIOS2_NUM_R1_OPCODES): This.
657 (nios2_r2_opcodes): New.
658 (NIOS2_NUM_R2_OPCODES): New.
659 (nios2_num_r2_opcodes): New.
660 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
661 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
662 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
663 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
664 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
666 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
668 * i386-dis.c (OP_Mwaitx): New.
669 (rm_table): Add monitorx/mwaitx.
670 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
671 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
672 (operand_type_init): Add CpuMWAITX.
673 * i386-opc.h (CpuMWAITX): New.
674 (i386_cpu_flags): Add cpumwaitx.
675 * i386-opc.tbl: Add monitorx and mwaitx.
676 * i386-init.h: Regenerated.
677 * i386-tbl.h: Likewise.
679 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
681 * ppc-opc.c (insert_ls): Test for invalid LS operands.
682 (insert_esync): New function.
683 (LS, WC): Use insert_ls.
684 (ESYNC): Use insert_esync.
686 2015-06-22 Nick Clifton <nickc@redhat.com>
688 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
689 requested region lies beyond it.
690 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
691 looking for 32-bit insns.
692 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
694 * sh-dis.c (print_insn_sh): Likewise.
695 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
696 blocks of instructions.
697 * vax-dis.c (print_insn_vax): Check that the requested address
698 does not clash with the stop_vma.
700 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
702 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
703 * ppc-opc.c (FXM4): Add non-zero optional value.
706 (insert_fxm): Handle new default operand value.
707 (extract_fxm): Likewise.
708 (insert_tbr): Likewise.
709 (extract_tbr): Likewise.
711 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
713 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
715 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
717 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
719 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
721 * ppc-opc.c: Add comment accidentally removed by old commit.
724 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
726 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
728 2015-06-04 Nick Clifton <nickc@redhat.com>
731 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
733 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
735 * arm-dis.c (arm_opcodes): Add "setpan".
736 (thumb_opcodes): Add "setpan".
738 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
740 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
743 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
745 * aarch64-tbl.h (aarch64_feature_rdma): New.
747 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
748 * aarch64-asm-2.c: Regenerate.
749 * aarch64-dis-2.c: Regenerate.
750 * aarch64-opc-2.c: Regenerate.
752 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
754 * aarch64-tbl.h (aarch64_feature_lor): New.
756 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
758 * aarch64-asm-2.c: Regenerate.
759 * aarch64-dis-2.c: Regenerate.
760 * aarch64-opc-2.c: Regenerate.
762 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
764 * aarch64-opc.c (F_ARCHEXT): New.
765 (aarch64_sys_regs): Add "pan".
766 (aarch64_sys_reg_supported_p): New.
767 (aarch64_pstatefields): Add "pan".
768 (aarch64_pstatefield_supported_p): New.
770 2015-06-01 Jan Beulich <jbeulich@suse.com>
772 * i386-tbl.h: Regenerate.
774 2015-06-01 Jan Beulich <jbeulich@suse.com>
776 * i386-dis.c (print_insn): Swap rounding mode specifier and
777 general purpose register in Intel mode.
779 2015-06-01 Jan Beulich <jbeulich@suse.com>
781 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
782 * i386-tbl.h: Regenerate.
784 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
786 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
787 * i386-init.h: Regenerated.
789 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-dis.c: Add comments for '@'.
793 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
794 (enum x86_64_isa): New.
796 (print_i386_disassembler_options): Add amd64 and intel64.
797 (print_insn): Handle amd64 and intel64.
799 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
800 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
801 * i386-opc.h (AMD64): New.
802 (CpuIntel64): Likewise.
803 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
804 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
805 Mark direct call/jmp without Disp16|Disp32 as Intel64.
806 * i386-init.h: Regenerated.
807 * i386-tbl.h: Likewise.
809 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
811 * ppc-opc.c (IH) New define.
812 (powerpc_opcodes) <wait>: Do not enable for POWER7.
813 <tlbie>: Add RS operand for POWER7.
814 <slbia>: Add IH operand for POWER6.
816 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
818 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
821 * i386-tbl.h: Regenerated.
823 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
825 * configure.ac: Support bfd_iamcu_arch.
826 * disassemble.c (disassembler): Support bfd_iamcu_arch.
827 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
828 CPU_IAMCU_COMPAT_FLAGS.
829 (cpu_flags): Add CpuIAMCU.
830 * i386-opc.h (CpuIAMCU): New.
831 (i386_cpu_flags): Add cpuiamcu.
832 * configure: Regenerated.
833 * i386-init.h: Likewise.
834 * i386-tbl.h: Likewise.
836 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
839 * i386-dis.c (X86_64_E8): New.
840 (X86_64_E9): Likewise.
841 Update comments on 'T', 'U', 'V'. Add comments for '^'.
842 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
843 (x86_64_table): Add X86_64_E8 and X86_64_E9.
844 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
846 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
849 2015-04-30 DJ Delorie <dj@redhat.com>
851 * disassemble.c (disassembler): Choose suitable disassembler based
853 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
854 it to decode mul/div insns.
855 * rl78-decode.c: Regenerate.
856 * rl78-dis.c (print_insn_rl78): Rename to...
857 (print_insn_rl78_common): ...this, take ISA parameter.
858 (print_insn_rl78): New.
859 (print_insn_rl78_g10): New.
860 (print_insn_rl78_g13): New.
861 (print_insn_rl78_g14): New.
862 (rl78_get_disassembler): New.
864 2015-04-29 Nick Clifton <nickc@redhat.com>
866 * po/fr.po: Updated French translation.
868 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
870 * ppc-opc.c (DCBT_EO): New define.
871 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
875 <waitrsv>: Do not enable for POWER7 and later.
876 <waitimpl>: Likewise.
877 <dcbt>: Default to the two operand form of the instruction for all
878 "old" cpus. For "new" cpus, use the operand ordering that matches
879 whether the cpu is server or embedded.
882 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
884 * s390-opc.c: New instruction type VV0UU2.
885 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
888 2015-04-23 Jan Beulich <jbeulich@suse.com>
890 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
891 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
892 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
893 (vfpclasspd, vfpclassps): Add %XZ.
895 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
897 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
898 (PREFIX_UD_REPZ): Likewise.
899 (PREFIX_UD_REPNZ): Likewise.
900 (PREFIX_UD_DATA): Likewise.
901 (PREFIX_UD_ADDR): Likewise.
902 (PREFIX_UD_LOCK): Likewise.
904 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
906 * i386-dis.c (prefix_requirement): Removed.
907 (print_insn): Don't set prefix_requirement. Check
908 dp->prefix_requirement instead of prefix_requirement.
910 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
913 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
914 (PREFIX_MOD_0_0FC7_REG_6): This.
915 (PREFIX_MOD_3_0FC7_REG_6): New.
916 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
917 (prefix_table): Replace PREFIX_0FC7_REG_6 with
918 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
919 PREFIX_MOD_3_0FC7_REG_7.
920 (mod_table): Replace PREFIX_0FC7_REG_6 with
921 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
922 PREFIX_MOD_3_0FC7_REG_7.
924 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
927 (PREFIX_MANDATORY_REPNZ): Likewise.
928 (PREFIX_MANDATORY_DATA): Likewise.
929 (PREFIX_MANDATORY_ADDR): Likewise.
930 (PREFIX_MANDATORY_LOCK): Likewise.
931 (PREFIX_MANDATORY): Likewise.
932 (PREFIX_UD_SHIFT): Set to 8
933 (PREFIX_UD_REPZ): Updated.
934 (PREFIX_UD_REPNZ): Likewise.
935 (PREFIX_UD_DATA): Likewise.
936 (PREFIX_UD_ADDR): Likewise.
937 (PREFIX_UD_LOCK): Likewise.
938 (PREFIX_IGNORED_SHIFT): New.
939 (PREFIX_IGNORED_REPZ): Likewise.
940 (PREFIX_IGNORED_REPNZ): Likewise.
941 (PREFIX_IGNORED_DATA): Likewise.
942 (PREFIX_IGNORED_ADDR): Likewise.
943 (PREFIX_IGNORED_LOCK): Likewise.
944 (PREFIX_OPCODE): Likewise.
945 (PREFIX_IGNORED): Likewise.
946 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
947 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
948 (three_byte_table): Likewise.
949 (mod_table): Likewise.
950 (mandatory_prefix): Renamed to ...
951 (prefix_requirement): This.
952 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
953 Update PREFIX_90 entry.
954 (get_valid_dis386): Check prefix_requirement to see if a prefix
956 (print_insn): Replace mandatory_prefix with prefix_requirement.
958 2015-04-15 Renlin Li <renlin.li@arm.com>
960 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
961 use it for ssat and ssat16.
962 (print_insn_thumb32): Add handle case for 'D' control code.
964 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
965 H.J. Lu <hongjiu.lu@intel.com>
967 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
968 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
969 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
970 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
971 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
972 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
973 Fill prefix_requirement field.
974 (struct dis386): Add prefix_requirement field.
975 (dis386): Fill prefix_requirement field.
976 (dis386_twobyte): Ditto.
977 (twobyte_has_mandatory_prefix_: Remove.
978 (reg_table): Fill prefix_requirement field.
979 (prefix_table): Ditto.
980 (x86_64_table): Ditto.
981 (three_byte_table): Ditto.
984 (vex_len_table): Ditto.
985 (vex_w_table): Ditto.
988 (print_insn): Use prefix_requirement.
989 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
990 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
993 2015-03-30 Mike Frysinger <vapier@gentoo.org>
995 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
997 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
999 * Makefile.in: Regenerated.
1001 2015-03-25 Anton Blanchard <anton@samba.org>
1003 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1004 powerpc_opcd_indices and vle_opcd_indices once.
1006 2015-03-25 Anton Blanchard <anton@samba.org>
1008 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1010 2015-03-24 Terry Guo <terry.guo@arm.com>
1012 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1013 (opcode16): Likewise.
1014 (coprocessor_opcodes): Replace bit with feature struct.
1015 (neon_opcodes): Likewise.
1016 (arm_opcodes): Likewise.
1017 (thumb_opcodes): Likewise.
1018 (thumb32_opcodes): Likewise.
1019 (print_insn_coprocessor): Likewise.
1020 (print_insn_arm): Likewise.
1021 (select_arm_features): Follow new feature struct.
1023 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1025 * i386-dis.c (rm_table): Add clzero.
1026 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1027 Add CPU_CLZERO_FLAGS.
1028 (cpu_flags): Add CpuCLZERO.
1029 * i386-opc.h: Add CpuCLZERO.
1030 * i386-opc.tbl: Add clzero.
1031 * i386-init.h: Re-generated.
1032 * i386-tbl.h: Re-generated.
1034 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1036 * mips-opc.c (decode_mips_operand): Fix constraint issues
1037 with u and y operands.
1039 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1041 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1043 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1045 * s390-opc.c: Add new IBM z13 instructions.
1046 * s390-opc.txt: Likewise.
1048 2015-03-10 Renlin Li <renlin.li@arm.com>
1050 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1051 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1053 * aarch64-asm-2.c: Regenerate.
1054 * aarch64-dis-2.c: Likewise.
1055 * aarch64-opc-2.c: Likewise.
1057 2015-03-03 Jiong Wang <jiong.wang@arm.com>
1059 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1061 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1063 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1065 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1066 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1068 2015-02-23 Vinay <Vinay.G@kpit.com>
1070 * rl78-decode.opc (MOV): Added space between two operands for
1071 'mov' instruction in index addressing mode.
1072 * rl78-decode.c: Regenerate.
1074 2015-02-19 Pedro Alves <palves@redhat.com>
1076 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1078 2015-02-10 Pedro Alves <palves@redhat.com>
1079 Tom Tromey <tromey@redhat.com>
1081 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1082 microblaze_and, microblaze_xor.
1083 * microblaze-opc.h (opcodes): Adjust.
1085 2015-01-28 James Bowman <james.bowman@ftdichip.com>
1087 * Makefile.am: Add FT32 files.
1088 * configure.ac: Handle FT32.
1089 * disassemble.c (disassembler): Call print_insn_ft32.
1090 * ft32-dis.c: New file.
1091 * ft32-opc.c: New file.
1092 * Makefile.in: Regenerate.
1093 * configure: Regenerate.
1094 * po/POTFILES.in: Regenerate.
1096 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1098 * nds32-asm.c (keyword_sr): Add new system registers.
1100 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1102 * s390-dis.c (s390_extract_operand): Support vector register
1104 (s390_print_insn_with_opcode): Support new operands types and add
1105 new handling of optional operands.
1106 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1107 and include opcode/s390.h instead.
1108 (struct op_struct): New field `flags'.
1109 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1110 (dumpTable): Dump flags.
1111 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1113 * s390-opc.c: Add new operands types, instruction formats, and
1115 (s390_opformats): Add new formats for .insn.
1116 * s390-opc.txt: Add new instructions.
1118 2015-01-01 Alan Modra <amodra@gmail.com>
1120 Update year range in copyright notice of all files.
1122 For older changes see ChangeLog-2014
1124 Copyright (C) 2015 Free Software Foundation, Inc.
1126 Copying and distribution of this file, with or without modification,
1127 are permitted in any medium without royalty provided the copyright
1128 notice and this notice are preserved.
1134 version-control: never