1 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-tbl.h (aarch64_feature_ras): New.
7 (aarch64_opcode_table): Add "esb".
9 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
11 * i386-dis.c (MOD_0F01_REG_5): New.
12 (RM_0F01_REG_5): Likewise.
13 (reg_table): Use MOD_0F01_REG_5.
14 (mod_table): Add MOD_0F01_REG_5.
15 (rm_table): Add RM_0F01_REG_5.
16 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
17 (cpu_flags): Add CpuOSPKE.
18 * i386-opc.h (CpuOSPKE): New.
19 (i386_cpu_flags): Add cpuospke.
20 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
21 * i386-init.h: Regenerated.
22 * i386-tbl.h: Likewise.
24 2015-12-07 DJ Delorie <dj@redhat.com>
26 * rl78-decode.opc: Enable MULU for all ISAs.
27 * rl78-decode.c: Regenerate.
29 2015-12-07 Alan Modra <amodra@gmail.com>
31 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
34 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
36 * arc-dis.c (special_flag_p): Match full mnemonic.
37 * arc-opc.c (print_insn_arc): Check section size to read
38 appropriate number of bytes. Fix printing.
39 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
42 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
44 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
47 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
49 * aarch64-asm-2.c: Regenerate.
50 * aarch64-dis-2.c: Regenerate.
51 * aarch64-opc-2.c: Regenerate.
52 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
53 (QL_INT2FP_H, QL_FP2INT_H): New.
54 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
57 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
58 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
59 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
60 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
61 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
62 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
65 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
67 * aarch64-opc.c (half_conv_t): New.
68 (expand_fp_imm): Replace is_dp flag with the parameter size to
69 specify the number of bytes for the required expansion. Treat
70 a 16-bit expansion like a 32-bit expansion. Add check for an
71 unsupported size request. Update comment.
72 (aarch64_print_operand): Update to support 16-bit floating point
73 values. Update for changes to expand_fp_imm.
75 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
77 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
80 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
82 * aarch64-asm-2.c: Regenerate.
83 * aarch64-dis-2.c: Regenerate.
84 * aarch64-opc-2.c: Regenerate.
85 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
88 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
90 * aarch64-asm-2.c: Regenerate.
91 * aarch64-asm.c (convert_bfc_to_bfm): New.
92 (convert_to_real): Add case for OP_BFC.
93 * aarch64-dis-2.c: Regenerate.
94 * aarch64-dis.c: (convert_bfm_to_bfc): New.
95 (convert_to_alias): Add case for OP_BFC.
96 * aarch64-opc-2.c: Regenerate.
97 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
98 to allow width operand in three-operand instructions.
99 * aarch64-tbl.h (QL_BF1): New.
100 (aarch64_feature_v8_2): New.
102 (aarch64_opcode_table): Add "bfc".
104 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
106 * aarch64-asm-2.c: Regenerate.
107 * aarch64-dis-2.c: Regenerate.
108 * aarch64-dis.c: Weaken assert.
109 * aarch64-gen.c: Include the instruction in the list of its
112 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
114 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
115 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
118 2015-11-23 Tristan Gingold <gingold@adacore.com>
120 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
122 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
124 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
125 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
126 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
127 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
128 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
129 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
130 cnthv_ctl_el2, cnthv_cval_el2.
131 (aarch64_sys_reg_supported_p): Update for the new system
134 2015-11-20 Nick Clifton <nickc@redhat.com>
137 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
139 2015-11-20 Nick Clifton <nickc@redhat.com>
141 * po/zh_CN.po: Updated simplified Chinese translation.
143 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
145 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
146 of MSR PAN immediate operand.
148 2015-11-16 Nick Clifton <nickc@redhat.com>
150 * rx-dis.c (condition_names): Replace always and never with
151 invalid, since the always/never conditions can never be legal.
153 2015-11-13 Tristan Gingold <gingold@adacore.com>
155 * configure: Regenerate.
157 2015-11-11 Alan Modra <amodra@gmail.com>
158 Peter Bergner <bergner@vnet.ibm.com>
160 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
161 Add PPC_OPCODE_VSX3 to the vsx entry.
162 (powerpc_init_dialect): Set default dialect to power9.
163 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
164 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
165 extract_l1 insert_xtq6, extract_xtq6): New static functions.
166 (insert_esync): Test for illegal L operand value.
167 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
168 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
169 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
170 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
171 PPCVSX3): New defines.
172 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
173 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
174 <mcrxr>: Use XBFRARB_MASK.
175 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
176 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
177 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
178 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
179 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
180 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
181 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
182 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
183 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
184 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
185 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
186 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
187 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
188 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
189 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
190 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
191 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
192 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
193 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
194 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
195 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
196 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
197 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
198 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
199 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
200 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
201 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
202 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
203 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
204 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
205 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
206 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
208 2015-11-02 Nick Clifton <nickc@redhat.com>
210 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
212 * rx-decode.c: Regenerate.
214 2015-11-02 Nick Clifton <nickc@redhat.com>
216 * rx-decode.opc (rx_disp): If the displacement is zero, set the
217 type to RX_Operand_Zero_Indirect.
218 * rx-decode.c: Regenerate.
219 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
221 2015-10-28 Yao Qi <yao.qi@linaro.org>
223 * aarch64-dis.c (aarch64_decode_insn): Add one argument
224 noaliases_p. Update comments. Pass noaliases_p rather than
225 no_aliases to aarch64_opcode_decode.
226 (print_insn_aarch64_word): Pass no_aliases to
229 2015-10-27 Vinay <Vinay.G@kpit.com>
232 * rl78-decode.opc (MOV): Added offset to DE register in index
234 * rl78-decode.c: Regenerate.
236 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
239 * rl78-decode.opc: Add 's' print operator to instructions that
240 access system registers.
241 * rl78-decode.c: Regenerate.
242 * rl78-dis.c (print_insn_rl78_common): Decode all system
245 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
248 * rl78-decode.opc: Add 'a' print operator to mov instructions
249 using stack pointer plus index addressing.
250 * rl78-decode.c: Regenerate.
252 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
254 * s390-opc.c: Fix comment.
255 * s390-opc.txt: Change instruction type for troo, trot, trto, and
256 trtt to RRF_U0RER since the second parameter does not need to be a
259 2015-10-08 Nick Clifton <nickc@redhat.com>
261 * arc-dis.c (print_insn_arc): Initiallise insn array.
263 2015-10-07 Yao Qi <yao.qi@linaro.org>
265 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
266 'name' rather than 'template'.
267 * aarch64-opc.c (aarch64_print_operand): Likewise.
269 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
271 * arc-dis.c: Revamped file for ARC support
272 * arc-dis.h: Likewise.
273 * arc-ext.c: Likewise.
274 * arc-ext.h: Likewise.
275 * arc-opc.c: Likewise.
276 * arc-fxi.h: New file.
277 * arc-regs.h: Likewise.
278 * arc-tbl.h: Likewise.
280 2015-10-02 Yao Qi <yao.qi@linaro.org>
282 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
283 argument insn type to aarch64_insn. Rename to ...
284 (aarch64_decode_insn): ... it.
285 (print_insn_aarch64_word): Caller updated.
287 2015-10-02 Yao Qi <yao.qi@linaro.org>
289 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
290 (print_insn_aarch64_word): Caller updated.
292 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
294 * s390-mkopc.c (main): Parse htm and vx flag.
295 * s390-opc.txt: Mark instructions from the hardware transactional
296 memory and vector facilities with the "htm"/"vx" flag.
298 2015-09-28 Nick Clifton <nickc@redhat.com>
300 * po/de.po: Updated German translation.
302 2015-09-28 Tom Rix <tom@bumblecow.com>
304 * ppc-opc.c (PPC500): Mark some opcodes as invalid
306 2015-09-23 Nick Clifton <nickc@redhat.com>
308 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
310 * tic30-dis.c (print_branch): Likewise.
311 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
312 value before left shifting.
313 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
314 * hppa-dis.c (print_insn_hppa): Likewise.
315 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
317 * msp430-dis.c (msp430_singleoperand): Likewise.
318 (msp430_doubleoperand): Likewise.
319 (print_insn_msp430): Likewise.
320 * nds32-asm.c (parse_operand): Likewise.
321 * sh-opc.h (MASK): Likewise.
322 * v850-dis.c (get_operand_value): Likewise.
324 2015-09-22 Nick Clifton <nickc@redhat.com>
326 * rx-decode.opc (bwl): Use RX_Bad_Size.
328 (ubwl): Likewise. Rename to ubw.
329 (uBWL): Rename to uBW.
330 Replace all references to uBWL with uBW.
331 * rx-decode.c: Regenerate.
332 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
333 (opsize_names): Likewise.
334 (print_insn_rx): Detect and report RX_Bad_Size.
336 2015-09-22 Anton Blanchard <anton@samba.org>
338 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
340 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
342 * sparc-dis.c (print_insn_sparc): Handle the privileged register
345 2015-08-24 Jan Stancek <jstancek@redhat.com>
347 * i386-dis.c (print_insn): Fix decoding of three byte operands.
349 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
352 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
353 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
354 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
355 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
356 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
357 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
358 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
359 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
360 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
361 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
362 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
363 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
364 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
365 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
366 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
367 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
368 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
369 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
370 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
371 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
372 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
373 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
374 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
375 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
376 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
377 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
378 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
379 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
380 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
381 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
382 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
383 (vex_w_table): Replace terminals with MOD_TABLE entries for
384 most of mask instructions.
386 2015-08-17 Alan Modra <amodra@gmail.com>
388 * cgen.sh: Trim trailing space from cgen output.
389 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
390 (print_dis_table): Likewise.
391 * opc2c.c (dump_lines): Likewise.
392 (orig_filename): Warning fix.
393 * ia64-asmtab.c: Regenerate.
395 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
397 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
398 and higher with ARM instruction set will now mark the 26-bit
399 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
400 (arm_opcodes): Fix for unpredictable nop being recognized as a
403 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
405 * micromips-opc.c (micromips_opcodes): Re-order table so that move
406 based on 'or' is first.
407 * mips-opc.c (mips_builtin_opcodes): Ditto.
409 2015-08-11 Nick Clifton <nickc@redhat.com>
412 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
415 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
417 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
419 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
421 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
422 * i386-init.h: Regenerated.
424 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
427 * i386-dis.c (MOD_0FC3): New.
428 (PREFIX_0FC3): Renamed to ...
429 (PREFIX_MOD_0_0FC3): This.
430 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
431 (prefix_table): Replace Ma with Ev on movntiS.
432 (mod_table): Add MOD_0FC3.
434 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
436 * configure: Regenerated.
438 2015-07-23 Alan Modra <amodra@gmail.com>
441 * i386-dis.c (get64): Avoid signed integer overflow.
443 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
446 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
447 "EXEvexHalfBcstXmmq" for the second operand.
448 (EVEX_W_0F79_P_2): Likewise.
449 (EVEX_W_0F7A_P_2): Likewise.
450 (EVEX_W_0F7B_P_2): Likewise.
452 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
454 * arm-dis.c (print_insn_coprocessor): Added support for quarter
455 float bitfield format.
456 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
457 quarter float bitfield format.
459 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
461 * configure: Regenerated.
463 2015-07-03 Alan Modra <amodra@gmail.com>
465 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
466 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
467 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
469 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
470 Cesar Philippidis <cesar@codesourcery.com>
472 * nios2-dis.c (nios2_extract_opcode): New.
473 (nios2_disassembler_state): New.
474 (nios2_find_opcode_hash): Use mach parameter to select correct
476 (nios2_print_insn_arg): Extend to support new R2 argument letters
478 (print_insn_nios2): Check for 16-bit instruction at end of memory.
479 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
480 (NIOS2_NUM_OPCODES): Rename to...
481 (NIOS2_NUM_R1_OPCODES): This.
482 (nios2_r2_opcodes): New.
483 (NIOS2_NUM_R2_OPCODES): New.
484 (nios2_num_r2_opcodes): New.
485 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
486 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
487 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
488 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
489 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
491 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
493 * i386-dis.c (OP_Mwaitx): New.
494 (rm_table): Add monitorx/mwaitx.
495 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
496 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
497 (operand_type_init): Add CpuMWAITX.
498 * i386-opc.h (CpuMWAITX): New.
499 (i386_cpu_flags): Add cpumwaitx.
500 * i386-opc.tbl: Add monitorx and mwaitx.
501 * i386-init.h: Regenerated.
502 * i386-tbl.h: Likewise.
504 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
506 * ppc-opc.c (insert_ls): Test for invalid LS operands.
507 (insert_esync): New function.
508 (LS, WC): Use insert_ls.
509 (ESYNC): Use insert_esync.
511 2015-06-22 Nick Clifton <nickc@redhat.com>
513 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
514 requested region lies beyond it.
515 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
516 looking for 32-bit insns.
517 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
519 * sh-dis.c (print_insn_sh): Likewise.
520 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
521 blocks of instructions.
522 * vax-dis.c (print_insn_vax): Check that the requested address
523 does not clash with the stop_vma.
525 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
527 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
528 * ppc-opc.c (FXM4): Add non-zero optional value.
531 (insert_fxm): Handle new default operand value.
532 (extract_fxm): Likewise.
533 (insert_tbr): Likewise.
534 (extract_tbr): Likewise.
536 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
538 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
540 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
542 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
544 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
546 * ppc-opc.c: Add comment accidentally removed by old commit.
549 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
551 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
553 2015-06-04 Nick Clifton <nickc@redhat.com>
556 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
558 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
560 * arm-dis.c (arm_opcodes): Add "setpan".
561 (thumb_opcodes): Add "setpan".
563 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
565 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
568 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
570 * aarch64-tbl.h (aarch64_feature_rdma): New.
572 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
573 * aarch64-asm-2.c: Regenerate.
574 * aarch64-dis-2.c: Regenerate.
575 * aarch64-opc-2.c: Regenerate.
577 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
579 * aarch64-tbl.h (aarch64_feature_lor): New.
581 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
583 * aarch64-asm-2.c: Regenerate.
584 * aarch64-dis-2.c: Regenerate.
585 * aarch64-opc-2.c: Regenerate.
587 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
589 * aarch64-opc.c (F_ARCHEXT): New.
590 (aarch64_sys_regs): Add "pan".
591 (aarch64_sys_reg_supported_p): New.
592 (aarch64_pstatefields): Add "pan".
593 (aarch64_pstatefield_supported_p): New.
595 2015-06-01 Jan Beulich <jbeulich@suse.com>
597 * i386-tbl.h: Regenerate.
599 2015-06-01 Jan Beulich <jbeulich@suse.com>
601 * i386-dis.c (print_insn): Swap rounding mode specifier and
602 general purpose register in Intel mode.
604 2015-06-01 Jan Beulich <jbeulich@suse.com>
606 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
607 * i386-tbl.h: Regenerate.
609 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
611 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
612 * i386-init.h: Regenerated.
614 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
617 * i386-dis.c: Add comments for '@'.
618 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
619 (enum x86_64_isa): New.
621 (print_i386_disassembler_options): Add amd64 and intel64.
622 (print_insn): Handle amd64 and intel64.
624 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
625 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
626 * i386-opc.h (AMD64): New.
627 (CpuIntel64): Likewise.
628 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
629 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
630 Mark direct call/jmp without Disp16|Disp32 as Intel64.
631 * i386-init.h: Regenerated.
632 * i386-tbl.h: Likewise.
634 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
636 * ppc-opc.c (IH) New define.
637 (powerpc_opcodes) <wait>: Do not enable for POWER7.
638 <tlbie>: Add RS operand for POWER7.
639 <slbia>: Add IH operand for POWER6.
641 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
643 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
646 * i386-tbl.h: Regenerated.
648 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
650 * configure.ac: Support bfd_iamcu_arch.
651 * disassemble.c (disassembler): Support bfd_iamcu_arch.
652 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
653 CPU_IAMCU_COMPAT_FLAGS.
654 (cpu_flags): Add CpuIAMCU.
655 * i386-opc.h (CpuIAMCU): New.
656 (i386_cpu_flags): Add cpuiamcu.
657 * configure: Regenerated.
658 * i386-init.h: Likewise.
659 * i386-tbl.h: Likewise.
661 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
664 * i386-dis.c (X86_64_E8): New.
665 (X86_64_E9): Likewise.
666 Update comments on 'T', 'U', 'V'. Add comments for '^'.
667 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
668 (x86_64_table): Add X86_64_E8 and X86_64_E9.
669 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
671 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
674 2015-04-30 DJ Delorie <dj@redhat.com>
676 * disassemble.c (disassembler): Choose suitable disassembler based
678 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
679 it to decode mul/div insns.
680 * rl78-decode.c: Regenerate.
681 * rl78-dis.c (print_insn_rl78): Rename to...
682 (print_insn_rl78_common): ...this, take ISA parameter.
683 (print_insn_rl78): New.
684 (print_insn_rl78_g10): New.
685 (print_insn_rl78_g13): New.
686 (print_insn_rl78_g14): New.
687 (rl78_get_disassembler): New.
689 2015-04-29 Nick Clifton <nickc@redhat.com>
691 * po/fr.po: Updated French translation.
693 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
695 * ppc-opc.c (DCBT_EO): New define.
696 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
700 <waitrsv>: Do not enable for POWER7 and later.
701 <waitimpl>: Likewise.
702 <dcbt>: Default to the two operand form of the instruction for all
703 "old" cpus. For "new" cpus, use the operand ordering that matches
704 whether the cpu is server or embedded.
707 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
709 * s390-opc.c: New instruction type VV0UU2.
710 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
713 2015-04-23 Jan Beulich <jbeulich@suse.com>
715 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
716 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
717 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
718 (vfpclasspd, vfpclassps): Add %XZ.
720 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
722 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
723 (PREFIX_UD_REPZ): Likewise.
724 (PREFIX_UD_REPNZ): Likewise.
725 (PREFIX_UD_DATA): Likewise.
726 (PREFIX_UD_ADDR): Likewise.
727 (PREFIX_UD_LOCK): Likewise.
729 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
731 * i386-dis.c (prefix_requirement): Removed.
732 (print_insn): Don't set prefix_requirement. Check
733 dp->prefix_requirement instead of prefix_requirement.
735 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
738 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
739 (PREFIX_MOD_0_0FC7_REG_6): This.
740 (PREFIX_MOD_3_0FC7_REG_6): New.
741 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
742 (prefix_table): Replace PREFIX_0FC7_REG_6 with
743 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
744 PREFIX_MOD_3_0FC7_REG_7.
745 (mod_table): Replace PREFIX_0FC7_REG_6 with
746 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
747 PREFIX_MOD_3_0FC7_REG_7.
749 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
751 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
752 (PREFIX_MANDATORY_REPNZ): Likewise.
753 (PREFIX_MANDATORY_DATA): Likewise.
754 (PREFIX_MANDATORY_ADDR): Likewise.
755 (PREFIX_MANDATORY_LOCK): Likewise.
756 (PREFIX_MANDATORY): Likewise.
757 (PREFIX_UD_SHIFT): Set to 8
758 (PREFIX_UD_REPZ): Updated.
759 (PREFIX_UD_REPNZ): Likewise.
760 (PREFIX_UD_DATA): Likewise.
761 (PREFIX_UD_ADDR): Likewise.
762 (PREFIX_UD_LOCK): Likewise.
763 (PREFIX_IGNORED_SHIFT): New.
764 (PREFIX_IGNORED_REPZ): Likewise.
765 (PREFIX_IGNORED_REPNZ): Likewise.
766 (PREFIX_IGNORED_DATA): Likewise.
767 (PREFIX_IGNORED_ADDR): Likewise.
768 (PREFIX_IGNORED_LOCK): Likewise.
769 (PREFIX_OPCODE): Likewise.
770 (PREFIX_IGNORED): Likewise.
771 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
772 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
773 (three_byte_table): Likewise.
774 (mod_table): Likewise.
775 (mandatory_prefix): Renamed to ...
776 (prefix_requirement): This.
777 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
778 Update PREFIX_90 entry.
779 (get_valid_dis386): Check prefix_requirement to see if a prefix
781 (print_insn): Replace mandatory_prefix with prefix_requirement.
783 2015-04-15 Renlin Li <renlin.li@arm.com>
785 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
786 use it for ssat and ssat16.
787 (print_insn_thumb32): Add handle case for 'D' control code.
789 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
790 H.J. Lu <hongjiu.lu@intel.com>
792 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
793 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
794 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
795 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
796 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
797 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
798 Fill prefix_requirement field.
799 (struct dis386): Add prefix_requirement field.
800 (dis386): Fill prefix_requirement field.
801 (dis386_twobyte): Ditto.
802 (twobyte_has_mandatory_prefix_: Remove.
803 (reg_table): Fill prefix_requirement field.
804 (prefix_table): Ditto.
805 (x86_64_table): Ditto.
806 (three_byte_table): Ditto.
809 (vex_len_table): Ditto.
810 (vex_w_table): Ditto.
813 (print_insn): Use prefix_requirement.
814 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
815 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
818 2015-03-30 Mike Frysinger <vapier@gentoo.org>
820 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
822 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
824 * Makefile.in: Regenerated.
826 2015-03-25 Anton Blanchard <anton@samba.org>
828 * ppc-dis.c (disassemble_init_powerpc): Only initialise
829 powerpc_opcd_indices and vle_opcd_indices once.
831 2015-03-25 Anton Blanchard <anton@samba.org>
833 * ppc-opc.c (powerpc_opcodes): Add slbfee.
835 2015-03-24 Terry Guo <terry.guo@arm.com>
837 * arm-dis.c (opcode32): Updated to use new arm feature struct.
838 (opcode16): Likewise.
839 (coprocessor_opcodes): Replace bit with feature struct.
840 (neon_opcodes): Likewise.
841 (arm_opcodes): Likewise.
842 (thumb_opcodes): Likewise.
843 (thumb32_opcodes): Likewise.
844 (print_insn_coprocessor): Likewise.
845 (print_insn_arm): Likewise.
846 (select_arm_features): Follow new feature struct.
848 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
850 * i386-dis.c (rm_table): Add clzero.
851 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
852 Add CPU_CLZERO_FLAGS.
853 (cpu_flags): Add CpuCLZERO.
854 * i386-opc.h: Add CpuCLZERO.
855 * i386-opc.tbl: Add clzero.
856 * i386-init.h: Re-generated.
857 * i386-tbl.h: Re-generated.
859 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
861 * mips-opc.c (decode_mips_operand): Fix constraint issues
862 with u and y operands.
864 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
866 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
868 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
870 * s390-opc.c: Add new IBM z13 instructions.
871 * s390-opc.txt: Likewise.
873 2015-03-10 Renlin Li <renlin.li@arm.com>
875 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
876 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
878 * aarch64-asm-2.c: Regenerate.
879 * aarch64-dis-2.c: Likewise.
880 * aarch64-opc-2.c: Likewise.
882 2015-03-03 Jiong Wang <jiong.wang@arm.com>
884 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
886 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
888 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
890 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
891 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
893 2015-02-23 Vinay <Vinay.G@kpit.com>
895 * rl78-decode.opc (MOV): Added space between two operands for
896 'mov' instruction in index addressing mode.
897 * rl78-decode.c: Regenerate.
899 2015-02-19 Pedro Alves <palves@redhat.com>
901 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
903 2015-02-10 Pedro Alves <palves@redhat.com>
904 Tom Tromey <tromey@redhat.com>
906 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
907 microblaze_and, microblaze_xor.
908 * microblaze-opc.h (opcodes): Adjust.
910 2015-01-28 James Bowman <james.bowman@ftdichip.com>
912 * Makefile.am: Add FT32 files.
913 * configure.ac: Handle FT32.
914 * disassemble.c (disassembler): Call print_insn_ft32.
915 * ft32-dis.c: New file.
916 * ft32-opc.c: New file.
917 * Makefile.in: Regenerate.
918 * configure: Regenerate.
919 * po/POTFILES.in: Regenerate.
921 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
923 * nds32-asm.c (keyword_sr): Add new system registers.
925 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
927 * s390-dis.c (s390_extract_operand): Support vector register
929 (s390_print_insn_with_opcode): Support new operands types and add
930 new handling of optional operands.
931 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
932 and include opcode/s390.h instead.
933 (struct op_struct): New field `flags'.
934 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
935 (dumpTable): Dump flags.
936 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
938 * s390-opc.c: Add new operands types, instruction formats, and
940 (s390_opformats): Add new formats for .insn.
941 * s390-opc.txt: Add new instructions.
943 2015-01-01 Alan Modra <amodra@gmail.com>
945 Update year range in copyright notice of all files.
947 For older changes see ChangeLog-2014
949 Copyright (C) 2015 Free Software Foundation, Inc.
951 Copying and distribution of this file, with or without modification,
952 are permitted in any medium without royalty provided the copyright
953 notice and this notice are preserved.
959 version-control: never