1 2019-10-12 Nick Clifton <nickc@redhat.com>
4 * configure: Regenerate.
5 * po/opcodes.pot: Regenerate.
7 2019-10-04 Jan Beulich <jbeulich@suse.com>
10 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
12 * i386-tbl.h: Re-generate.
14 2019-09-30 Phil Blundell <pb@pbcl.net>
17 * configure, Makefile.in, po/opcodes.pot: Regenerate.
19 2019-09-16 Phil Blundell <pb@pbcl.net>
21 * configure: Regenerated.
23 2019-09-09 Phil Blundell <pb@pbcl.net>
25 binutils 2.33 branch created.
27 2019-09-03 Nick Clifton <nickc@redhat.com>
30 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
31 greater than zero before indexing via (bufcnt -1).
33 2019-09-03 Nick Clifton <nickc@redhat.com>
36 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
37 (MAX_SPEC_REG_NAME_LEN): Define.
38 (struct mmix_dis_info): Use defined constants for array lengths.
39 (get_reg_name): New function.
40 (get_sprec_reg_name): New function.
41 (print_insn_mmix): Use new functions.
43 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
45 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
46 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
47 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
49 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
51 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
52 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
53 (aarch64_sys_reg_supported_p): Update checks for the above.
55 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
57 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
58 cases MVE_SQRSHRL and MVE_UQRSHLL.
59 (print_insn_mve): Add case for specifier 'k' to check
60 specific bit of the instruction.
62 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
65 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
66 encountering an unknown machine type.
67 (print_insn_arc): Handle arc_insn_length returning 0. In error
68 cases return -1 rather than calling abort.
70 2019-08-07 Jan Beulich <jbeulich@suse.com>
72 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
73 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
75 * i386-tbl.h: Re-generate.
77 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
79 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
82 2019-07-30 Mel Chen <mel.chen@sifive.com>
84 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
85 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
87 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
90 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
92 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
93 and MPY class instructions.
94 (parse_option): Add nps400 option.
95 (print_arc_disassembler_options): Add nps400 info.
97 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
99 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
102 * arc-opc.c (RAD_CHK): Add.
103 * arc-tbl.h: Regenerate.
105 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
107 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
108 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
110 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
112 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
113 instructions as UNPREDICTABLE.
115 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
117 * bpf-desc.c: Regenerated.
119 2019-07-17 Jan Beulich <jbeulich@suse.com>
121 * i386-gen.c (static_assert): Define.
123 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
124 (Opcode_Modifier_Num): ... this.
127 2019-07-16 Jan Beulich <jbeulich@suse.com>
129 * i386-gen.c (operand_types): Move RegMem ...
130 (opcode_modifiers): ... here.
131 * i386-opc.h (RegMem): Move to opcode modifer enum.
132 (union i386_operand_type): Move regmem field ...
133 (struct i386_opcode_modifier): ... here.
134 * i386-opc.tbl (RegMem): Define.
135 (mov, movq): Move RegMem on segment, control, debug, and test
137 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
138 to non-SSE2AVX flavor.
139 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
140 Move RegMem on register only flavors. Drop IgnoreSize from
141 legacy encoding flavors.
142 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
144 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
145 register only flavors.
146 (vmovd): Move RegMem and drop IgnoreSize on register only
147 flavor. Change opcode and operand order to store form.
148 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
150 2019-07-16 Jan Beulich <jbeulich@suse.com>
152 * i386-gen.c (operand_type_init, operand_types): Replace SReg
154 * i386-opc.h (SReg2, SReg3): Replace by ...
156 (union i386_operand_type): Replace sreg fields.
157 * i386-opc.tbl (mov, ): Use SReg.
158 (push, pop): Likewies. Drop i386 and x86-64 specific segment
160 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
161 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
163 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
165 * bpf-desc.c: Regenerate.
166 * bpf-opc.c: Likewise.
167 * bpf-opc.h: Likewise.
169 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
171 * bpf-desc.c: Regenerate.
172 * bpf-opc.c: Likewise.
174 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
176 * arm-dis.c (print_insn_coprocessor): Rename index to
179 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
181 * riscv-opc.c (riscv_insn_types): Add r4 type.
183 * riscv-opc.c (riscv_insn_types): Add b and j type.
185 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
186 format for sb type and correct s type.
188 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
190 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
191 SVE FMOV alias of FCPY.
193 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
195 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
196 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
198 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
200 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
201 registers in an instruction prefixed by MOVPRFX.
203 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
205 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
206 sve_size_13 icode to account for variant behaviour of
208 * aarch64-dis-2.c: Regenerate.
209 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
210 sve_size_13 icode to account for variant behaviour of
212 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
213 (OP_SVE_VVV_Q_D): Add new qualifier.
214 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
215 (struct aarch64_opcode): Split pmull{t,b} into those requiring
218 2019-07-01 Jan Beulich <jbeulich@suse.com>
220 * opcodes/i386-gen.c (operand_type_init): Remove
221 OPERAND_TYPE_VEC_IMM4 entry.
222 (operand_types): Remove Vec_Imm4.
223 * opcodes/i386-opc.h (Vec_Imm4): Delete.
224 (union i386_operand_type): Remove vec_imm4.
225 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
226 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
228 2019-07-01 Jan Beulich <jbeulich@suse.com>
230 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
231 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
232 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
233 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
234 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
235 monitorx, mwaitx): Drop ImmExt from operand-less forms.
236 * i386-tbl.h: Re-generate.
238 2019-07-01 Jan Beulich <jbeulich@suse.com>
240 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
242 * i386-tbl.h: Re-generate.
244 2019-07-01 Jan Beulich <jbeulich@suse.com>
246 * i386-opc.tbl (C): New.
247 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
248 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
249 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
250 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
251 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
252 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
253 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
254 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
255 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
256 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
257 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
258 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
259 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
260 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
261 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
262 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
263 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
264 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
265 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
266 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
267 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
268 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
269 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
270 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
271 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
272 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
274 * i386-tbl.h: Re-generate.
276 2019-07-01 Jan Beulich <jbeulich@suse.com>
278 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
280 * i386-tbl.h: Re-generate.
282 2019-07-01 Jan Beulich <jbeulich@suse.com>
284 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
285 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
286 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
287 * i386-tbl.h: Re-generate.
289 2019-07-01 Jan Beulich <jbeulich@suse.com>
291 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
292 Disp8MemShift from register only templates.
293 * i386-tbl.h: Re-generate.
295 2019-07-01 Jan Beulich <jbeulich@suse.com>
297 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
298 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
299 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
300 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
301 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
302 EVEX_W_0F11_P_3_M_1): Delete.
303 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
304 EVEX_W_0F11_P_3): New.
305 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
306 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
307 MOD_EVEX_0F11_PREFIX_3 table entries.
308 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
309 PREFIX_EVEX_0F11 table entries.
310 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
311 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
312 EVEX_W_0F11_P_3_M_{0,1} table entries.
314 2019-07-01 Jan Beulich <jbeulich@suse.com>
316 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
319 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
322 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
323 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
324 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
325 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
326 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
327 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
328 EVEX_LEN_0F38C7_R_6_P_2_W_1.
329 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
330 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
331 PREFIX_EVEX_0F38C6_REG_6 entries.
332 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
333 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
334 EVEX_W_0F38C7_R_6_P_2 entries.
335 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
336 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
337 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
338 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
339 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
340 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
341 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
343 2019-06-27 Jan Beulich <jbeulich@suse.com>
345 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
346 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
347 VEX_LEN_0F2D_P_3): Delete.
348 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
349 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
350 (prefix_table): ... here.
352 2019-06-27 Jan Beulich <jbeulich@suse.com>
354 * i386-dis.c (Iq): Delete.
356 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
358 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
359 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
360 (OP_E_memory): Also honor needindex when deciding whether an
361 address size prefix needs printing.
362 (OP_I): Remove handling of q_mode. Add handling of d_mode.
364 2019-06-26 Jim Wilson <jimw@sifive.com>
367 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
368 Set info->display_endian to info->endian_code.
370 2019-06-25 Jan Beulich <jbeulich@suse.com>
372 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
373 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
374 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
375 OPERAND_TYPE_ACC64 entries.
376 * i386-init.h: Re-generate.
378 2019-06-25 Jan Beulich <jbeulich@suse.com>
380 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
382 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
384 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
386 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
387 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
389 2019-06-25 Jan Beulich <jbeulich@suse.com>
391 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
394 2019-06-25 Jan Beulich <jbeulich@suse.com>
396 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
397 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
399 * i386-opc.tbl (movnti): Add IgnoreSize.
400 * i386-tbl.h: Re-generate.
402 2019-06-25 Jan Beulich <jbeulich@suse.com>
404 * i386-opc.tbl (and): Mark Imm8S form for optimization.
405 * i386-tbl.h: Re-generate.
407 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
409 * i386-dis-evex.h: Break into ...
410 * i386-dis-evex-len.h: New file.
411 * i386-dis-evex-mod.h: Likewise.
412 * i386-dis-evex-prefix.h: Likewise.
413 * i386-dis-evex-reg.h: Likewise.
414 * i386-dis-evex-w.h: Likewise.
415 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
416 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
419 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
422 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
423 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
425 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
426 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
427 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
428 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
429 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
430 EVEX_LEN_0F385B_P_2_W_1.
431 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
432 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
433 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
434 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
435 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
436 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
437 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
438 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
439 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
440 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
442 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
445 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
446 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
447 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
448 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
449 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
450 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
451 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
452 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
453 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
454 EVEX_LEN_0F3A43_P_2_W_1.
455 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
456 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
457 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
458 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
459 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
460 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
461 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
462 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
463 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
464 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
465 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
466 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
468 2019-06-14 Nick Clifton <nickc@redhat.com>
470 * po/fr.po; Updated French translation.
472 2019-06-13 Stafford Horne <shorne@gmail.com>
474 * or1k-asm.c: Regenerated.
475 * or1k-desc.c: Regenerated.
476 * or1k-desc.h: Regenerated.
477 * or1k-dis.c: Regenerated.
478 * or1k-ibld.c: Regenerated.
479 * or1k-opc.c: Regenerated.
480 * or1k-opc.h: Regenerated.
481 * or1k-opinst.c: Regenerated.
483 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
485 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
487 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
490 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
491 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
492 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
493 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
494 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
495 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
496 EVEX_LEN_0F3A1B_P_2_W_1.
497 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
498 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
499 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
500 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
501 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
502 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
503 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
504 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
506 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
509 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
510 EVEX.vvvv when disassembling VEX and EVEX instructions.
511 (OP_VEX): Set vex.register_specifier to 0 after readding
512 vex.register_specifier.
513 (OP_Vex_2src_1): Likewise.
514 (OP_Vex_2src_2): Likewise.
515 (OP_LWP_E): Likewise.
516 (OP_EX_Vex): Don't check vex.register_specifier.
517 (OP_XMM_Vex): Likewise.
519 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
520 Lili Cui <lili.cui@intel.com>
522 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
523 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
525 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
526 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
527 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
528 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
529 (i386_cpu_flags): Add cpuavx512_vp2intersect.
530 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
531 * i386-init.h: Regenerated.
532 * i386-tbl.h: Likewise.
534 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
535 Lili Cui <lili.cui@intel.com>
537 * doc/c-i386.texi: Document enqcmd.
538 * testsuite/gas/i386/enqcmd-intel.d: New file.
539 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
540 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
541 * testsuite/gas/i386/enqcmd.d: Likewise.
542 * testsuite/gas/i386/enqcmd.s: Likewise.
543 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
544 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
545 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
546 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
547 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
548 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
549 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
552 2019-06-04 Alan Hayward <alan.hayward@arm.com>
554 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
556 2019-06-03 Alan Modra <amodra@gmail.com>
558 * ppc-dis.c (prefix_opcd_indices): Correct size.
560 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
563 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
565 * i386-tbl.h: Regenerated.
567 2019-05-24 Alan Modra <amodra@gmail.com>
569 * po/POTFILES.in: Regenerate.
571 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
572 Alan Modra <amodra@gmail.com>
574 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
575 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
576 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
577 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
578 XTOP>): Define and add entries.
579 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
580 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
581 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
582 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
584 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
585 Alan Modra <amodra@gmail.com>
587 * ppc-dis.c (ppc_opts): Add "future" entry.
588 (PREFIX_OPCD_SEGS): Define.
589 (prefix_opcd_indices): New array.
590 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
591 (lookup_prefix): New function.
592 (print_insn_powerpc): Handle 64-bit prefix instructions.
593 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
594 (PMRR, POWERXX): Define.
595 (prefix_opcodes): New instruction table.
596 (prefix_num_opcodes): New constant.
598 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
600 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
601 * configure: Regenerated.
602 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
604 (HFILES): Add bpf-desc.h and bpf-opc.h.
605 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
606 bpf-ibld.c and bpf-opc.c.
608 * Makefile.in: Regenerated.
609 * disassemble.c (ARCH_bpf): Define.
610 (disassembler): Add case for bfd_arch_bpf.
611 (disassemble_init_for_target): Likewise.
612 (enum epbf_isa_attr): Define.
613 * disassemble.h: extern print_insn_bpf.
614 * bpf-asm.c: Generated.
615 * bpf-opc.h: Likewise.
616 * bpf-opc.c: Likewise.
617 * bpf-ibld.c: Likewise.
618 * bpf-dis.c: Likewise.
619 * bpf-desc.h: Likewise.
620 * bpf-desc.c: Likewise.
622 2019-05-21 Sudakshina Das <sudi.das@arm.com>
624 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
625 and VMSR with the new operands.
627 2019-05-21 Sudakshina Das <sudi.das@arm.com>
629 * arm-dis.c (enum mve_instructions): New enum
630 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
632 (mve_opcodes): New instructions as above.
633 (is_mve_encoding_conflict): Add cases for csinc, csinv,
635 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
637 2019-05-21 Sudakshina Das <sudi.das@arm.com>
639 * arm-dis.c (emun mve_instructions): Updated for new instructions.
640 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
641 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
642 uqshl, urshrl and urshr.
643 (is_mve_okay_in_it): Add new instructions to TRUE list.
644 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
645 (print_insn_mve): Updated to accept new %j,
646 %<bitfield>m and %<bitfield>n patterns.
648 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
650 * mips-opc.c (mips_builtin_opcodes): Change source register
653 2019-05-20 Nick Clifton <nickc@redhat.com>
655 * po/fr.po: Updated French translation.
657 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
658 Michael Collison <michael.collison@arm.com>
660 * arm-dis.c (thumb32_opcodes): Add new instructions.
661 (enum mve_instructions): Likewise.
662 (enum mve_undefined): Add new reasons.
663 (is_mve_encoding_conflict): Handle new instructions.
664 (is_mve_undefined): Likewise.
665 (is_mve_unpredictable): Likewise.
666 (print_mve_undefined): Likewise.
667 (print_mve_size): Likewise.
669 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
670 Michael Collison <michael.collison@arm.com>
672 * arm-dis.c (thumb32_opcodes): Add new instructions.
673 (enum mve_instructions): Likewise.
674 (is_mve_encoding_conflict): Handle new instructions.
675 (is_mve_undefined): Likewise.
676 (is_mve_unpredictable): Likewise.
677 (print_mve_size): Likewise.
679 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
680 Michael Collison <michael.collison@arm.com>
682 * arm-dis.c (thumb32_opcodes): Add new instructions.
683 (enum mve_instructions): Likewise.
684 (is_mve_encoding_conflict): Likewise.
685 (is_mve_unpredictable): Likewise.
686 (print_mve_size): Likewise.
688 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
689 Michael Collison <michael.collison@arm.com>
691 * arm-dis.c (thumb32_opcodes): Add new instructions.
692 (enum mve_instructions): Likewise.
693 (is_mve_encoding_conflict): Handle new instructions.
694 (is_mve_undefined): Likewise.
695 (is_mve_unpredictable): Likewise.
696 (print_mve_size): Likewise.
698 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
699 Michael Collison <michael.collison@arm.com>
701 * arm-dis.c (thumb32_opcodes): Add new instructions.
702 (enum mve_instructions): Likewise.
703 (is_mve_encoding_conflict): Handle new instructions.
704 (is_mve_undefined): Likewise.
705 (is_mve_unpredictable): Likewise.
706 (print_mve_size): Likewise.
707 (print_insn_mve): Likewise.
709 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
710 Michael Collison <michael.collison@arm.com>
712 * arm-dis.c (thumb32_opcodes): Add new instructions.
713 (print_insn_thumb32): Handle new instructions.
715 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
716 Michael Collison <michael.collison@arm.com>
718 * arm-dis.c (enum mve_instructions): Add new instructions.
719 (enum mve_undefined): Add new reasons.
720 (is_mve_encoding_conflict): Handle new instructions.
721 (is_mve_undefined): Likewise.
722 (is_mve_unpredictable): Likewise.
723 (print_mve_undefined): Likewise.
724 (print_mve_size): Likewise.
725 (print_mve_shift_n): Likewise.
726 (print_insn_mve): Likewise.
728 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
729 Michael Collison <michael.collison@arm.com>
731 * arm-dis.c (enum mve_instructions): Add new instructions.
732 (is_mve_encoding_conflict): Handle new instructions.
733 (is_mve_unpredictable): Likewise.
734 (print_mve_rotate): Likewise.
735 (print_mve_size): Likewise.
736 (print_insn_mve): Likewise.
738 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
739 Michael Collison <michael.collison@arm.com>
741 * arm-dis.c (enum mve_instructions): Add new instructions.
742 (is_mve_encoding_conflict): Handle new instructions.
743 (is_mve_unpredictable): Likewise.
744 (print_mve_size): Likewise.
745 (print_insn_mve): Likewise.
747 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
748 Michael Collison <michael.collison@arm.com>
750 * arm-dis.c (enum mve_instructions): Add new instructions.
751 (enum mve_undefined): Add new reasons.
752 (is_mve_encoding_conflict): Handle new instructions.
753 (is_mve_undefined): Likewise.
754 (is_mve_unpredictable): Likewise.
755 (print_mve_undefined): Likewise.
756 (print_mve_size): Likewise.
757 (print_insn_mve): Likewise.
759 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
760 Michael Collison <michael.collison@arm.com>
762 * arm-dis.c (enum mve_instructions): Add new instructions.
763 (is_mve_encoding_conflict): Handle new instructions.
764 (is_mve_undefined): Likewise.
765 (is_mve_unpredictable): Likewise.
766 (print_mve_size): Likewise.
767 (print_insn_mve): Likewise.
769 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
770 Michael Collison <michael.collison@arm.com>
772 * arm-dis.c (enum mve_instructions): Add new instructions.
773 (enum mve_unpredictable): Add new reasons.
774 (enum mve_undefined): Likewise.
775 (is_mve_okay_in_it): Handle new isntructions.
776 (is_mve_encoding_conflict): Likewise.
777 (is_mve_undefined): Likewise.
778 (is_mve_unpredictable): Likewise.
779 (print_mve_vmov_index): Likewise.
780 (print_simd_imm8): Likewise.
781 (print_mve_undefined): Likewise.
782 (print_mve_unpredictable): Likewise.
783 (print_mve_size): Likewise.
784 (print_insn_mve): Likewise.
786 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
787 Michael Collison <michael.collison@arm.com>
789 * arm-dis.c (enum mve_instructions): Add new instructions.
790 (enum mve_unpredictable): Add new reasons.
791 (enum mve_undefined): Likewise.
792 (is_mve_encoding_conflict): Handle new instructions.
793 (is_mve_undefined): Likewise.
794 (is_mve_unpredictable): Likewise.
795 (print_mve_undefined): Likewise.
796 (print_mve_unpredictable): Likewise.
797 (print_mve_rounding_mode): Likewise.
798 (print_mve_vcvt_size): Likewise.
799 (print_mve_size): Likewise.
800 (print_insn_mve): Likewise.
802 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
803 Michael Collison <michael.collison@arm.com>
805 * arm-dis.c (enum mve_instructions): Add new instructions.
806 (enum mve_unpredictable): Add new reasons.
807 (enum mve_undefined): Likewise.
808 (is_mve_undefined): Handle new instructions.
809 (is_mve_unpredictable): Likewise.
810 (print_mve_undefined): Likewise.
811 (print_mve_unpredictable): Likewise.
812 (print_mve_size): Likewise.
813 (print_insn_mve): Likewise.
815 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
816 Michael Collison <michael.collison@arm.com>
818 * arm-dis.c (enum mve_instructions): Add new instructions.
819 (enum mve_undefined): Add new reasons.
820 (insns): Add new instructions.
821 (is_mve_encoding_conflict):
822 (print_mve_vld_str_addr): New print function.
823 (is_mve_undefined): Handle new instructions.
824 (is_mve_unpredictable): Likewise.
825 (print_mve_undefined): Likewise.
826 (print_mve_size): Likewise.
827 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
828 (print_insn_mve): Handle new operands.
830 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
831 Michael Collison <michael.collison@arm.com>
833 * arm-dis.c (enum mve_instructions): Add new instructions.
834 (enum mve_unpredictable): Add new reasons.
835 (is_mve_encoding_conflict): Handle new instructions.
836 (is_mve_unpredictable): Likewise.
837 (mve_opcodes): Add new instructions.
838 (print_mve_unpredictable): Handle new reasons.
839 (print_mve_register_blocks): New print function.
840 (print_mve_size): Handle new instructions.
841 (print_insn_mve): Likewise.
843 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
844 Michael Collison <michael.collison@arm.com>
846 * arm-dis.c (enum mve_instructions): Add new instructions.
847 (enum mve_unpredictable): Add new reasons.
848 (enum mve_undefined): Likewise.
849 (is_mve_encoding_conflict): Handle new instructions.
850 (is_mve_undefined): Likewise.
851 (is_mve_unpredictable): Likewise.
852 (coprocessor_opcodes): Move NEON VDUP from here...
853 (neon_opcodes): ... to here.
854 (mve_opcodes): Add new instructions.
855 (print_mve_undefined): Handle new reasons.
856 (print_mve_unpredictable): Likewise.
857 (print_mve_size): Handle new instructions.
858 (print_insn_neon): Handle vdup.
859 (print_insn_mve): Handle new operands.
861 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
862 Michael Collison <michael.collison@arm.com>
864 * arm-dis.c (enum mve_instructions): Add new instructions.
865 (enum mve_unpredictable): Add new values.
866 (mve_opcodes): Add new instructions.
867 (vec_condnames): New array with vector conditions.
868 (mve_predicatenames): New array with predicate suffixes.
869 (mve_vec_sizename): New array with vector sizes.
870 (enum vpt_pred_state): New enum with vector predication states.
871 (struct vpt_block): New struct type for vpt blocks.
872 (vpt_block_state): Global struct to keep track of state.
873 (mve_extract_pred_mask): New helper function.
874 (num_instructions_vpt_block): Likewise.
875 (mark_outside_vpt_block): Likewise.
876 (mark_inside_vpt_block): Likewise.
877 (invert_next_predicate_state): Likewise.
878 (update_next_predicate_state): Likewise.
879 (update_vpt_block_state): Likewise.
880 (is_vpt_instruction): Likewise.
881 (is_mve_encoding_conflict): Add entries for new instructions.
882 (is_mve_unpredictable): Likewise.
883 (print_mve_unpredictable): Handle new cases.
884 (print_instruction_predicate): Likewise.
885 (print_mve_size): New function.
886 (print_vec_condition): New function.
887 (print_insn_mve): Handle vpt blocks and new print operands.
889 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
891 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
892 8, 14 and 15 for Armv8.1-M Mainline.
894 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
895 Michael Collison <michael.collison@arm.com>
897 * arm-dis.c (enum mve_instructions): New enum.
898 (enum mve_unpredictable): Likewise.
899 (enum mve_undefined): Likewise.
900 (struct mopcode32): New struct.
901 (is_mve_okay_in_it): New function.
902 (is_mve_architecture): Likewise.
903 (arm_decode_field): Likewise.
904 (arm_decode_field_multiple): Likewise.
905 (is_mve_encoding_conflict): Likewise.
906 (is_mve_undefined): Likewise.
907 (is_mve_unpredictable): Likewise.
908 (print_mve_undefined): Likewise.
909 (print_mve_unpredictable): Likewise.
910 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
911 (print_insn_mve): New function.
912 (print_insn_thumb32): Handle MVE architecture.
913 (select_arm_features): Force thumb for Armv8.1-m Mainline.
915 2019-05-10 Nick Clifton <nickc@redhat.com>
918 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
919 end of the table prematurely.
921 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
923 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
926 2019-05-11 Alan Modra <amodra@gmail.com>
928 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
929 when -Mraw is in effect.
931 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
933 * aarch64-dis-2.c: Regenerate.
934 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
935 (OP_SVE_BBB): New variant set.
936 (OP_SVE_DDDD): New variant set.
937 (OP_SVE_HHH): New variant set.
938 (OP_SVE_HHHU): New variant set.
939 (OP_SVE_SSS): New variant set.
940 (OP_SVE_SSSU): New variant set.
941 (OP_SVE_SHH): New variant set.
942 (OP_SVE_SBBU): New variant set.
943 (OP_SVE_DSS): New variant set.
944 (OP_SVE_DHHU): New variant set.
945 (OP_SVE_VMV_HSD_BHS): New variant set.
946 (OP_SVE_VVU_HSD_BHS): New variant set.
947 (OP_SVE_VVVU_SD_BH): New variant set.
948 (OP_SVE_VVVU_BHSD): New variant set.
949 (OP_SVE_VVV_QHD_DBS): New variant set.
950 (OP_SVE_VVV_HSD_BHS): New variant set.
951 (OP_SVE_VVV_HSD_BHS2): New variant set.
952 (OP_SVE_VVV_BHS_HSD): New variant set.
953 (OP_SVE_VV_BHS_HSD): New variant set.
954 (OP_SVE_VVV_SD): New variant set.
955 (OP_SVE_VVU_BHS_HSD): New variant set.
956 (OP_SVE_VZVV_SD): New variant set.
957 (OP_SVE_VZVV_BH): New variant set.
958 (OP_SVE_VZV_SD): New variant set.
959 (aarch64_opcode_table): Add sve2 instructions.
961 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
963 * aarch64-asm-2.c: Regenerated.
964 * aarch64-dis-2.c: Regenerated.
965 * aarch64-opc-2.c: Regenerated.
966 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
967 for SVE_SHLIMM_UNPRED_22.
968 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
969 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
972 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
974 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
975 sve_size_tsz_bhs iclass encode.
976 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
977 sve_size_tsz_bhs iclass decode.
979 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
981 * aarch64-asm-2.c: Regenerated.
982 * aarch64-dis-2.c: Regenerated.
983 * aarch64-opc-2.c: Regenerated.
984 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
985 for SVE_Zm4_11_INDEX.
986 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
987 (fields): Handle SVE_i2h field.
988 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
989 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
991 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
993 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
994 sve_shift_tsz_bhsd iclass encode.
995 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
996 sve_shift_tsz_bhsd iclass decode.
998 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1000 * aarch64-asm-2.c: Regenerated.
1001 * aarch64-dis-2.c: Regenerated.
1002 * aarch64-opc-2.c: Regenerated.
1003 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1004 (aarch64_encode_variant_using_iclass): Handle
1005 sve_shift_tsz_hsd iclass encode.
1006 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1007 sve_shift_tsz_hsd iclass decode.
1008 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1009 for SVE_SHRIMM_UNPRED_22.
1010 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1011 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1014 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1016 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1017 sve_size_013 iclass encode.
1018 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1019 sve_size_013 iclass decode.
1021 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1023 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1024 sve_size_bh iclass encode.
1025 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1026 sve_size_bh iclass decode.
1028 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1030 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1031 sve_size_sd2 iclass encode.
1032 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1033 sve_size_sd2 iclass decode.
1034 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1035 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1037 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1039 * aarch64-asm-2.c: Regenerated.
1040 * aarch64-dis-2.c: Regenerated.
1041 * aarch64-opc-2.c: Regenerated.
1042 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1044 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1045 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1047 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1049 * aarch64-asm-2.c: Regenerated.
1050 * aarch64-dis-2.c: Regenerated.
1051 * aarch64-opc-2.c: Regenerated.
1052 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1053 for SVE_Zm3_11_INDEX.
1054 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1055 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1056 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1058 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1060 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1062 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1063 sve_size_hsd2 iclass encode.
1064 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1065 sve_size_hsd2 iclass decode.
1066 * aarch64-opc.c (fields): Handle SVE_size field.
1067 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1069 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1071 * aarch64-asm-2.c: Regenerated.
1072 * aarch64-dis-2.c: Regenerated.
1073 * aarch64-opc-2.c: Regenerated.
1074 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1076 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1077 (fields): Handle SVE_rot3 field.
1078 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1079 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1081 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1083 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1086 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1089 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1090 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1091 aarch64_feature_sve2bitperm): New feature sets.
1092 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1093 for feature set addresses.
1094 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1095 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1097 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1098 Faraz Shahbazker <fshahbazker@wavecomp.com>
1100 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1101 argument and set ASE_EVA_R6 appropriately.
1102 (set_default_mips_dis_options): Pass ISA to above.
1103 (parse_mips_dis_option): Likewise.
1104 * mips-opc.c (EVAR6): New macro.
1105 (mips_builtin_opcodes): Add llwpe, scwpe.
1107 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1109 * aarch64-asm-2.c: Regenerated.
1110 * aarch64-dis-2.c: Regenerated.
1111 * aarch64-opc-2.c: Regenerated.
1112 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1113 AARCH64_OPND_TME_UIMM16.
1114 (aarch64_print_operand): Likewise.
1115 * aarch64-tbl.h (QL_IMM_NIL): New.
1118 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1120 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1122 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1124 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1125 Faraz Shahbazker <fshahbazker@wavecomp.com>
1127 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1129 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1131 * s12z-opc.h: Add extern "C" bracketing to help
1132 users who wish to use this interface in c++ code.
1134 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1136 * s12z-opc.c (bm_decode): Handle bit map operations with the
1139 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1141 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1142 specifier. Add entries for VLDR and VSTR of system registers.
1143 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1144 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1145 of %J and %K format specifier.
1147 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1149 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1150 Add new entries for VSCCLRM instruction.
1151 (print_insn_coprocessor): Handle new %C format control code.
1153 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1155 * arm-dis.c (enum isa): New enum.
1156 (struct sopcode32): New structure.
1157 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1158 set isa field of all current entries to ANY.
1159 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1160 Only match an entry if its isa field allows the current mode.
1162 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1164 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1166 (print_insn_thumb32): Add logic to print %n CLRM register list.
1168 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1170 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1173 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1175 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1176 (print_insn_thumb32): Edit the switch case for %Z.
1178 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1180 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1182 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1184 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1186 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1188 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1190 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1192 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1193 Arm register with r13 and r15 unpredictable.
1194 (thumb32_opcodes): New instructions for bfx and bflx.
1196 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1198 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1200 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1202 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1204 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1206 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1208 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1210 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1212 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1214 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1215 "optr". ("operator" is a reserved word in c++).
1217 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1219 * aarch64-opc.c (aarch64_print_operand): Add case for
1221 (verify_constraints): Likewise.
1222 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1223 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1224 to accept Rt|SP as first operand.
1225 (AARCH64_OPERANDS): Add new Rt_SP.
1226 * aarch64-asm-2.c: Regenerated.
1227 * aarch64-dis-2.c: Regenerated.
1228 * aarch64-opc-2.c: Regenerated.
1230 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1232 * aarch64-asm-2.c: Regenerated.
1233 * aarch64-dis-2.c: Likewise.
1234 * aarch64-opc-2.c: Likewise.
1235 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1237 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1239 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1241 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1243 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1244 * i386-init.h: Regenerated.
1246 2019-04-07 Alan Modra <amodra@gmail.com>
1248 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1249 op_separator to control printing of spaces, comma and parens
1250 rather than need_comma, need_paren and spaces vars.
1252 2019-04-07 Alan Modra <amodra@gmail.com>
1255 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1256 (print_insn_neon, print_insn_arm): Likewise.
1258 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1260 * i386-dis-evex.h (evex_table): Updated to support BF16
1262 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1263 and EVEX_W_0F3872_P_3.
1264 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1265 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1266 * i386-opc.h (enum): Add CpuAVX512_BF16.
1267 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1268 * i386-opc.tbl: Add AVX512 BF16 instructions.
1269 * i386-init.h: Regenerated.
1270 * i386-tbl.h: Likewise.
1272 2019-04-05 Alan Modra <amodra@gmail.com>
1274 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1275 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1276 to favour printing of "-" branch hint when using the "y" bit.
1277 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1279 2019-04-05 Alan Modra <amodra@gmail.com>
1281 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1282 opcode until first operand is output.
1284 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1287 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1288 (valid_bo_post_v2): Add support for 'at' branch hints.
1289 (insert_bo): Only error on branch on ctr.
1290 (get_bo_hint_mask): New function.
1291 (insert_boe): Add new 'branch_taken' formal argument. Add support
1292 for inserting 'at' branch hints.
1293 (extract_boe): Add new 'branch_taken' formal argument. Add support
1294 for extracting 'at' branch hints.
1295 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1296 (BOE): Delete operand.
1297 (BOM, BOP): New operands.
1299 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1300 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1301 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1302 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1303 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1304 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1305 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1306 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1307 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1308 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1309 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1310 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1311 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1312 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1313 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1314 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1315 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1316 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1317 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1318 bttarl+>: New extended mnemonics.
1320 2019-03-28 Alan Modra <amodra@gmail.com>
1323 * ppc-opc.c (BTF): Define.
1324 (powerpc_opcodes): Use for mtfsb*.
1325 * ppc-dis.c (print_insn_powerpc): Print fields with both
1326 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1328 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1330 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1331 (mapping_symbol_for_insn): Implement new algorithm.
1332 (print_insn): Remove duplicate code.
1334 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1336 * aarch64-dis.c (print_insn_aarch64):
1339 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1341 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1344 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1346 * aarch64-dis.c (last_stop_offset): New.
1347 (print_insn_aarch64): Use stop_offset.
1349 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1352 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1354 * i386-init.h: Regenerated.
1356 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1359 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1360 vmovdqu16, vmovdqu32 and vmovdqu64.
1361 * i386-tbl.h: Regenerated.
1363 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1365 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1366 from vstrszb, vstrszh, and vstrszf.
1368 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1370 * s390-opc.txt: Add instruction descriptions.
1372 2019-02-08 Jim Wilson <jimw@sifive.com>
1374 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1377 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1379 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1381 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1384 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1385 * aarch64-opc.c (verify_elem_sd): New.
1386 (fields): Add FLD_sz entr.
1387 * aarch64-tbl.h (_SIMD_INSN): New.
1388 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1389 fmulx scalar and vector by element isns.
1391 2019-02-07 Nick Clifton <nickc@redhat.com>
1393 * po/sv.po: Updated Swedish translation.
1395 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1397 * s390-mkopc.c (main): Accept arch13 as cpu string.
1398 * s390-opc.c: Add new instruction formats and instruction opcode
1400 * s390-opc.txt: Add new arch13 instructions.
1402 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1404 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1405 (aarch64_opcode): Change encoding for stg, stzg
1407 * aarch64-asm-2.c: Regenerated.
1408 * aarch64-dis-2.c: Regenerated.
1409 * aarch64-opc-2.c: Regenerated.
1411 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1413 * aarch64-asm-2.c: Regenerated.
1414 * aarch64-dis-2.c: Likewise.
1415 * aarch64-opc-2.c: Likewise.
1416 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1418 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1419 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1421 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1422 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1423 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1424 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1425 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1426 case for ldstgv_indexed.
1427 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1428 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1429 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1430 * aarch64-asm-2.c: Regenerated.
1431 * aarch64-dis-2.c: Regenerated.
1432 * aarch64-opc-2.c: Regenerated.
1434 2019-01-23 Nick Clifton <nickc@redhat.com>
1436 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1438 2019-01-21 Nick Clifton <nickc@redhat.com>
1440 * po/de.po: Updated German translation.
1441 * po/uk.po: Updated Ukranian translation.
1443 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1444 * mips-dis.c (mips_arch_choices): Fix typo in
1445 gs464, gs464e and gs264e descriptors.
1447 2019-01-19 Nick Clifton <nickc@redhat.com>
1449 * configure: Regenerate.
1450 * po/opcodes.pot: Regenerate.
1452 2018-06-24 Nick Clifton <nickc@redhat.com>
1454 2.32 branch created.
1456 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1458 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1460 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1463 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1465 * configure: Regenerate.
1467 2019-01-07 Alan Modra <amodra@gmail.com>
1469 * configure: Regenerate.
1470 * po/POTFILES.in: Regenerate.
1472 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1474 * s12z-opc.c: New file.
1475 * s12z-opc.h: New file.
1476 * s12z-dis.c: Removed all code not directly related to display
1477 of instructions. Used the interface provided by the new files
1479 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1480 * Makefile.in: Regenerate.
1481 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1482 * configure: Regenerate.
1484 2019-01-01 Alan Modra <amodra@gmail.com>
1486 Update year range in copyright notice of all files.
1488 For older changes see ChangeLog-2018
1490 Copyright (C) 2019 Free Software Foundation, Inc.
1492 Copying and distribution of this file, with or without modification,
1493 are permitted in any medium without royalty provided the copyright
1494 notice and this notice are preserved.
1500 version-control: never