1 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
3 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
5 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
6 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
7 (cpu_flags): Add CpuAVX512VBMI.
8 * i386-opc.h (enum): Add CpuAVX512VBMI.
9 (i386_cpu_flags): Add cpuavx512vbmi.
10 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
12 * i386-init.h: Regenerated.
13 * i386-tbl.h: Likewise.
15 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
17 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
18 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
20 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
21 (cpu_flags): Add CpuAVX512IFMA.
22 * i386-opc.h (enum): Add CpuAVX512IFMA.
23 (i386_cpu_flags): Add cpuavx512ifma.
24 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
25 * i386-init.h: Regenerated.
26 * i386-tbl.h: Likewise.
28 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
30 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
31 (prefix_table): Add pcommit.
32 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
33 (cpu_flags): Add CpuPCOMMIT.
34 * i386-opc.h (enum): Add CpuPCOMMIT.
35 (i386_cpu_flags): Add cpupcommit.
36 * i386-opc.tbl: Add pcommit.
37 * i386-init.h: Regenerated.
38 * i386-tbl.h: Likewise.
40 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
42 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
43 (prefix_table): Add clwb.
44 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
45 (cpu_flags): Add CpuCLWB.
46 * i386-opc.h (enum): Add CpuCLWB.
47 (i386_cpu_flags): Add cpuclwb.
48 * i386-opc.tbl: Add clwb.
49 * i386-init.h: Regenerated.
50 * i386-tbl.h: Likewise.
52 2014-11-03 Nick Clifton <nickc@redhat.com>
54 * po/fi.po: Updated Finnish translation.
56 2014-10-29 Nick Clifton <nickc@redhat.com>
58 * po/de.po: Updated German translation.
60 2014-10-28 Alan Modra <amodra@gmail.com>
63 2014-10-21 Jan Beulich <jbeulich@suse.com>
64 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
66 2014-10-15 Tristan Gingold <gingold@adacore.com>
68 * configure: Regenerate.
70 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
72 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
73 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
74 Annotate table with HWCAP2 bits.
75 Add instructions xmontmul, xmontsqr, xmpmul.
76 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
77 r,i,%mwait' and `rd %mwait,r' instructions.
78 Add rd/wr instructions for accessing the %mcdper ancillary state
80 (sparc-opcodes): Add sparc5/vis4.0 instructions:
81 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
82 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
83 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
84 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
85 fpsubus16, and faligndatai.
86 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
87 ancillary state register to the table.
88 (print_insn_sparc): Handle the %mcdper ancillary state register.
89 (print_insn_sparc): Handle new operand type '}'.
91 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-dis.c (MOD_0F20): Removed.
97 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
99 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
100 (OP_R): Check mod/rm byte and call OP_E_register.
102 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
104 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
105 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
106 keyword_aridxi): Add audio ISA extension.
107 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
108 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
109 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
110 for nds32-dis.c using.
111 (build_opcode_syntax): Remove dead code.
112 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
113 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
114 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
116 * nds32-asm.h: Declare.
117 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
120 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
121 Matthew Fortune <matthew.fortune@imgtec.com>
123 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
125 (parse_mips_dis_option): Allow MSA and virtualization support for
127 (mips_print_arg_state): Add fields dest_regno and seen_dest.
128 (mips_seen_register): New function.
129 (print_insn_arg): Refactored code to use mips_seen_register
130 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
131 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
132 the register rather than aborting.
133 (print_insn_args): Add length argument. Add code to correctly
134 calculate the instruction address for pc relative instructions.
135 (validate_insn_args): New static function.
136 (print_insn_mips): Prevent jalx disassembling for r6. Use
138 (print_insn_micromips): Use validate_insn_args.
139 all the arguments are valid.
140 * mips-formats.h (PREV_CHECK): New define.
141 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
142 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
147 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
148 MIPS R6 instructions from MIPS R2 instructions.
150 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
152 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
153 (putop): Handle "%LP".
155 2014-09-03 Jiong Wang <jiong.wang@arm.com>
157 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
158 * aarch64-dis-2.c: Update auto-generated file.
160 2014-09-03 Jiong Wang <jiong.wang@arm.com>
162 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
163 (aarch64_feature_lse): New feature added.
165 (aarch64_opcode_table): New LSE instructions added. Improve
166 descriptions for ldarb/ldarh/ldar.
167 (aarch64_opcode_table): Describe PAIRREG.
168 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
169 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
170 (aarch64_print_operand): Recognize PAIRREG.
171 (operand_general_constraint_met_p): Check reg pair constraints for CASP
173 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
174 (do_special_decoding): Recognize F_LSE_SZ.
175 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
177 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
179 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
180 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
181 "sdbbp", "syscall" and "wait".
183 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
184 Maciej W. Rozycki <macro@codesourcery.com>
186 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
187 returned if the U bit is set.
189 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
191 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
192 48-bit "li" encoding.
194 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
196 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
197 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
198 static functions, code was moved from...
199 (print_insn_s390): ...here.
200 (s390_extract_operand): Adjust comment. Change type of first
201 parameter from 'unsigned char *' to 'const bfd_byte *'.
202 (union operand_value): New.
203 (s390_extract_operand): Change return type to union operand_value.
204 Also avoid integer overflow in sign-extension.
205 (s390_print_insn_with_opcode): Adjust to changed return value from
206 s390_extract_operand(). Change "%i" printf format to "%u" for
208 (init_disasm): Simplify initialization of opc_index[]. This also
209 fixes an access after the last element of s390_opcodes[].
210 (print_insn_s390): Simplify the opcode search loop.
211 Check architecture mask against all searched opcodes, not just the
213 (s390_print_insn_with_opcode): Drop function pointer dereferences
215 (print_insn_s390): Likewise.
216 (s390_insn_length): Simplify formula for return value.
217 (s390_print_insn_with_opcode): Avoid special handling for the
218 separator before the first operand. Use new local variable
219 'flags' in place of 'operand->flags'.
221 2014-08-14 Mike Frysinger <vapier@gentoo.org>
223 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
224 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
225 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
226 Change assignment of 1 to priv->comment to TRUE.
227 (print_insn_bfin): Change legal to a bfd_boolean. Change
228 assignment of 0/1 with priv comment and parallel and legal
231 2014-08-14 Mike Frysinger <vapier@gentoo.org>
233 * bfin-dis.c (OUT): Define.
234 (decode_CC2stat_0): Declare new op_names array.
235 Replace multiple if statements with a single one.
237 2014-08-14 Mike Frysinger <vapier@gentoo.org>
239 * bfin-dis.c (struct private): Add iw0.
240 (_print_insn_bfin): Assign iw0 to priv.iw0.
241 (print_insn_bfin): Drop ifetch and use priv.iw0.
243 2014-08-13 Mike Frysinger <vapier@gentoo.org>
245 * bfin-dis.c (comment, parallel): Move from global scope ...
246 (struct private): ... to this new struct.
247 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
248 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
249 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
250 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
251 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
252 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
253 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
254 print_insn_bfin): Declare private struct. Use priv's comment and
257 2014-08-13 Mike Frysinger <vapier@gentoo.org>
259 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
260 (_print_insn_bfin): Add check for unaligned pc.
262 2014-08-13 Mike Frysinger <vapier@gentoo.org>
264 * bfin-dis.c (ifetch): New function.
265 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
268 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
270 * micromips-opc.c (COD): Rename throughout to...
271 (CM): New define, update to use INSN_COPROC_MOVE.
272 (LCD): Rename throughout to...
273 (LC): New define, update to use INSN_LOAD_COPROC.
274 * mips-opc.c: Likewise.
276 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
278 * micromips-opc.c (COD, LCD) New macros.
279 (cfc1, ctc1): Remove FP_S attribute.
280 (dmfc1, mfc1, mfhc1): Add LCD attribute.
281 (dmtc1, mtc1, mthc1): Add COD attribute.
282 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
284 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
285 Alexander Ivchenko <alexander.ivchenko@intel.com>
286 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
287 Sergey Lega <sergey.s.lega@intel.com>
288 Anna Tikhonova <anna.tikhonova@intel.com>
289 Ilya Tocar <ilya.tocar@intel.com>
290 Andrey Turetskiy <andrey.turetskiy@intel.com>
291 Ilya Verbin <ilya.verbin@intel.com>
292 Kirill Yukhin <kirill.yukhin@intel.com>
293 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
295 * i386-dis-evex.h: Updated.
296 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
297 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
298 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
299 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
301 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
302 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
303 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
304 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
305 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
306 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
307 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
308 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
309 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
310 (prefix_table): Add entries for new instructions.
311 (vex_len_table): Ditto.
312 (vex_w_table): Ditto.
313 (OP_E_memory): Update xmmq_mode handling.
314 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
315 (cpu_flags): Add CpuAVX512DQ.
316 * i386-init.h: Regenerared.
317 * i386-opc.h (CpuAVX512DQ): New.
318 (i386_cpu_flags): Add cpuavx512dq.
319 * i386-opc.tbl: Add AVX512DQ instructions.
320 * i386-tbl.h: Regenerate.
322 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
323 Alexander Ivchenko <alexander.ivchenko@intel.com>
324 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
325 Sergey Lega <sergey.s.lega@intel.com>
326 Anna Tikhonova <anna.tikhonova@intel.com>
327 Ilya Tocar <ilya.tocar@intel.com>
328 Andrey Turetskiy <andrey.turetskiy@intel.com>
329 Ilya Verbin <ilya.verbin@intel.com>
330 Kirill Yukhin <kirill.yukhin@intel.com>
331 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
333 * i386-dis-evex.h: Add new instructions (prefixes bellow).
334 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
335 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
336 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
337 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
338 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
339 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
340 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
341 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
342 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
343 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
344 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
345 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
346 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
347 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
348 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
349 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
350 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
351 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
352 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
353 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
354 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
355 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
356 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
357 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
358 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
359 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
360 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
361 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
362 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
363 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
364 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
365 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
366 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
367 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
368 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
369 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
370 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
371 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
372 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
373 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
374 (prefix_table): Add entries for new instructions.
376 (vex_len_table): Ditto.
377 (vex_w_table): Ditto.
378 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
379 mask_bd_mode handling.
380 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
382 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
384 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
385 (OP_EX): Add dqw_swap_mode handling.
386 (OP_VEX): Add mask_bd_mode handling.
387 (OP_Mask): Add mask_bd_mode handling.
388 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
389 (cpu_flags): Add CpuAVX512BW.
390 * i386-init.h: Regenerated.
391 * i386-opc.h (CpuAVX512BW): New.
392 (i386_cpu_flags): Add cpuavx512bw.
393 * i386-opc.tbl: Add AVX512BW instructions.
394 * i386-tbl.h: Regenerate.
396 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
397 Alexander Ivchenko <alexander.ivchenko@intel.com>
398 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
399 Sergey Lega <sergey.s.lega@intel.com>
400 Anna Tikhonova <anna.tikhonova@intel.com>
401 Ilya Tocar <ilya.tocar@intel.com>
402 Andrey Turetskiy <andrey.turetskiy@intel.com>
403 Ilya Verbin <ilya.verbin@intel.com>
404 Kirill Yukhin <kirill.yukhin@intel.com>
405 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
407 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
408 * i386-tbl.h: Regenerate.
410 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
411 Alexander Ivchenko <alexander.ivchenko@intel.com>
412 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
413 Sergey Lega <sergey.s.lega@intel.com>
414 Anna Tikhonova <anna.tikhonova@intel.com>
415 Ilya Tocar <ilya.tocar@intel.com>
416 Andrey Turetskiy <andrey.turetskiy@intel.com>
417 Ilya Verbin <ilya.verbin@intel.com>
418 Kirill Yukhin <kirill.yukhin@intel.com>
419 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
421 * i386-dis.c (intel_operand_size): Support 128/256 length in
422 vex_vsib_q_w_dq_mode.
423 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
424 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
425 (cpu_flags): Add CpuAVX512VL.
426 * i386-init.h: Regenerated.
427 * i386-opc.h (CpuAVX512VL): New.
428 (i386_cpu_flags): Add cpuavx512vl.
429 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
430 * i386-opc.tbl: Add AVX512VL instructions.
431 * i386-tbl.h: Regenerate.
433 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
435 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
436 * or1k-opinst.c: Regenerate.
438 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
440 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
441 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
443 2014-07-04 Alan Modra <amodra@gmail.com>
445 * configure.ac: Rename from configure.in.
446 * Makefile.in: Regenerate.
447 * config.in: Regenerate.
449 2014-07-04 Alan Modra <amodra@gmail.com>
451 * configure.in: Include bfd/version.m4.
452 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
453 (BFD_VERSION): Delete.
454 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
455 * configure: Regenerate.
456 * Makefile.in: Regenerate.
458 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
459 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
460 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
461 Soundararajan <Sounderarajan.D@atmel.com>
463 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
464 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
465 machine is not avrtiny.
467 2014-06-26 Philippe De Muyter <phdm@macqel.be>
469 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
472 2014-06-12 Alan Modra <amodra@gmail.com>
474 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
475 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
477 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
479 * i386-dis.c (fwait_prefix): New.
480 (ckprefix): Set fwait_prefix.
481 (print_insn): Properly print prefixes before fwait.
483 2014-06-07 Alan Modra <amodra@gmail.com>
485 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
487 2014-06-05 Joel Brobecker <brobecker@adacore.com>
489 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
490 bfd's development.sh.
491 * Makefile.in, configure: Regenerate.
493 2014-06-03 Nick Clifton <nickc@redhat.com>
495 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
496 decide when extended addressing is being used.
498 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
500 * sparc-opc.c (cas): Disable for LEON.
503 2014-05-20 Alan Modra <amodra@gmail.com>
505 * m68k-dis.c: Don't include setjmp.h.
507 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
509 * i386-dis.c (ADDR16_PREFIX): Removed.
510 (ADDR32_PREFIX): Likewise.
511 (DATA16_PREFIX): Likewise.
512 (DATA32_PREFIX): Likewise.
513 (prefix_name): Updated.
514 (print_insn): Simplify data and address size prefixes processing.
516 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
518 * or1k-desc.c: Regenerated.
519 * or1k-desc.h: Likewise.
520 * or1k-opc.c: Likewise.
521 * or1k-opc.h: Likewise.
522 * or1k-opinst.c: Likewise.
524 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
526 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
531 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
533 (parse_mips_dis_option): Update MSA and virtualization support to
534 allow mips64r3 and mips64r5.
536 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
538 * mips-opc.c (G3): Remove I4.
540 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
543 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
544 (end_codep): Likewise.
545 (mandatory_prefix): Likewise.
546 (active_seg_prefix): Likewise.
547 (ckprefix): Set active_seg_prefix to the active segment register
549 (seg_prefix): Removed.
550 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
551 for prefix index. Ignore the index if it is invalid and the
552 mandatory prefix isn't required.
553 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
554 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
555 in used_prefixes here. Don't print unused prefixes. Check
556 active_seg_prefix for the active segment register prefix.
557 Restore the DFLAG bit in sizeflag if the data size prefix is
558 unused. Check the unused mandatory PREFIX_XXX prefixes
559 (append_seg): Only print the segment register which gets used.
560 (OP_E_memory): Check active_seg_prefix for the segment register
563 (OP_OFF64): Likewise.
564 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
566 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
569 * config.in: Regenerated.
570 * configure: Likewise.
571 * configure.in: Check if sigsetjmp is available.
572 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
573 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
574 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
575 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
576 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
577 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
578 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
579 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
580 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
581 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
582 (OPCODES_SIGSETJMP): Likewise.
583 (OPCODES_SIGLONGJMP): Likewise.
584 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
585 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
586 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
587 * xtensa-dis.c (dis_private): Replace jmp_buf with
589 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
590 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
591 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
592 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
593 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
595 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
598 * i386-dis.c (print_insn): Handle prefixes before fwait.
600 2014-04-26 Alan Modra <amodra@gmail.com>
602 * po/POTFILES.in: Regenerate.
604 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
606 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
607 to allow the MIPS XPA ASE.
608 (parse_mips_dis_option): Process the -Mxpa option.
609 * mips-opc.c (XPA): New define.
610 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
611 locations of the ctc0 and cfc0 instructions.
613 2014-04-22 Christian Svensson <blue@cmd.nu>
615 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
616 * configure.in: Likewise.
617 * disassemble.c: Likewise.
618 * or1k-asm.c: New file.
619 * or1k-desc.c: New file.
620 * or1k-desc.h: New file.
621 * or1k-dis.c: New file.
622 * or1k-ibld.c: New file.
623 * or1k-opc.c: New file.
624 * or1k-opc.h: New file.
625 * or1k-opinst.c: New file.
626 * Makefile.in: Regenerate.
627 * configure: Regenerate.
628 * openrisc-asm.c: Delete.
629 * openrisc-desc.c: Delete.
630 * openrisc-desc.h: Delete.
631 * openrisc-dis.c: Delete.
632 * openrisc-ibld.c: Delete.
633 * openrisc-opc.c: Delete.
634 * openrisc-opc.h: Delete.
635 * or32-dis.c: Delete.
636 * or32-opc.c: Delete.
638 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
640 * i386-dis.c (rm_table): Add encls, enclu.
641 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
642 (cpu_flags): Add CpuSE1.
643 * i386-opc.h (enum): Add CpuSE1.
644 (i386_cpu_flags): Add cpuse1.
645 * i386-opc.tbl: Add encls, enclu.
646 * i386-init.h: Regenerated.
647 * i386-tbl.h: Likewise.
649 2014-04-02 Anthony Green <green@moxielogic.com>
651 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
652 instructions, sex.b and sex.s.
654 2014-03-26 Jiong Wang <jiong.wang@arm.com>
656 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
659 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
661 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
662 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
664 * i386-tbl.h: Regenerate.
666 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
668 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
669 %hstick_enable added.
671 2014-03-19 Nick Clifton <nickc@redhat.com>
673 * rx-decode.opc (bwl): Allow for bogus instructions with a size
675 (sbwl, ubwl, SCALE): Likewise.
676 * rx-decode.c: Regenerate.
678 2014-03-12 Alan Modra <amodra@gmail.com>
680 * Makefile.in: Regenerate.
682 2014-03-05 Alan Modra <amodra@gmail.com>
684 Update copyright years.
686 2014-03-04 Heiher <r@hev.cc>
688 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
690 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
692 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
693 so that they come after the Loongson extensions.
695 2014-03-03 Alan Modra <amodra@gmail.com>
697 * i386-gen.c (process_copyright): Emit copyright notice on one line.
699 2014-02-28 Alan Modra <amodra@gmail.com>
701 * msp430-decode.c: Regenerate.
703 2014-02-27 Jiong Wang <jiong.wang@arm.com>
705 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
706 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
708 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
710 * aarch64-opc.c (print_register_offset_address): Call
711 get_int_reg_name to prepare the register name.
713 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
715 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
716 * i386-tbl.h: Regenerate.
718 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
720 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
721 (cpu_flags): Add CpuPREFETCHWT1.
722 * i386-init.h: Regenerate.
723 * i386-opc.h (CpuPREFETCHWT1): New.
724 (i386_cpu_flags): Add cpuprefetchwt1.
725 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
726 * i386-tbl.h: Regenerate.
728 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
730 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
732 * i386-tbl.h: Regenerate.
734 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
736 * i386-gen.c (output_cpu_flags): Don't output trailing space.
737 (output_opcode_modifier): Likewise.
738 (output_operand_type): Likewise.
739 * i386-init.h: Regenerated.
740 * i386-tbl.h: Likewise.
742 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
744 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
746 (PREFIX enum): Add PREFIX_0FAE_REG_7.
747 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
748 (prefix_table): Add clflusopt.
749 (mod_table): Add xrstors, xsavec, xsaves.
750 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
751 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
752 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
753 * i386-init.h: Regenerate.
754 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
755 xsaves64, xsavec, xsavec64.
756 * i386-tbl.h: Regenerate.
758 2014-02-10 Alan Modra <amodra@gmail.com>
760 * po/POTFILES.in: Regenerate.
761 * po/opcodes.pot: Regenerate.
763 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
764 Jan Beulich <jbeulich@suse.com>
767 * i386-dis.c (OP_E_memory): Fix shift computation for
768 vex_vsib_q_w_dq_mode.
770 2014-01-09 Bradley Nelson <bradnelson@google.com>
771 Roland McGrath <mcgrathr@google.com>
773 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
774 last_rex_prefix is -1.
776 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
778 * i386-gen.c (process_copyright): Update copyright year to 2014.
780 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
782 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
784 For older changes see ChangeLog-2013
786 Copyright (C) 2014 Free Software Foundation, Inc.
788 Copying and distribution of this file, with or without modification,
789 are permitted in any medium without royalty provided the copyright
790 notice and this notice are preserved.
796 version-control: never