1 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
3 * aarch64-tbl.h (QL_X1NIL): New.
4 (arch64_opcode_table): Add ldraa, ldrab.
5 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
6 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
7 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
8 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
9 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
10 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
11 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
12 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
13 (aarch64_print_operand): Likewise.
14 * aarch64-asm-2.c: Regenerate.
15 * aarch64-dis-2.c: Regenerate.
16 * aarch64-opc-2.c: Regenerate.
18 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
20 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
21 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
22 * aarch64-asm-2.c: Regenerate.
23 * aarch64-dis-2.c: Regenerate.
24 * aarch64-opc-2.c: Regenerate.
26 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
28 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
29 (AARCH64_OPERANDS): Add Rm_SP.
30 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
31 * aarch64-asm-2.c: Regenerate.
32 * aarch64-dis-2.c: Regenerate.
33 * aarch64-opc-2.c: Regenerate.
35 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
37 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
38 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
40 * aarch64-asm-2.c: Regenerate.
41 * aarch64-dis-2.c: Regenerate.
42 * aarch64-opc-2.c: Regenerate.
44 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
46 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
47 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
48 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
49 (aarch64_sys_reg_supported_p): Add feature test for new registers.
51 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
53 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
54 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
55 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
57 * aarch64-asm-2.c: Regenerate.
58 * aarch64-dis-2.c: Regenerate.
60 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
62 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
64 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
67 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
68 * i386-dis.c (EdqwS): Removed.
69 (dqw_swap_mode): Likewise.
70 (intel_operand_size): Don't check dqw_swap_mode.
71 (OP_E_register): Likewise.
72 (OP_E_memory): Likewise.
75 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
76 * i386-tbl.h: Regerated.
78 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
80 * i386-opc.tbl: Merge AVX512F vmovq.
81 * i386-tbl.h: Regerated.
83 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
86 * i386-dis.c (THREE_BYTE_0F7A): Removed.
87 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
88 (three_byte_table): Remove THREE_BYTE_0F7A.
90 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
94 (FGRPd9_4): Replace 1 with 2.
95 (FGRPd9_5): Replace 2 with 3.
96 (FGRPd9_6): Replace 3 with 4.
97 (FGRPd9_7): Replace 4 with 5.
98 (FGRPda_5): Replace 5 with 6.
99 (FGRPdb_4): Replace 6 with 7.
100 (FGRPde_3): Replace 7 with 8.
101 (FGRPdf_4): Replace 8 with 9.
102 (fgrps): Add an entry for Bad_Opcode.
104 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
106 * arc-opc.c (arc_flag_operands): Add F_DI14.
107 (arc_flag_classes): Add C_DI14.
108 * arc-nps400-tbl.h: Add new exc instructions.
110 2016-11-03 Graham Markall <graham.markall@embecosm.com>
112 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
114 * arc-nps-400-tbl.h: Add dcmac instruction.
115 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
116 (insert_nps_rbdouble_64): Added.
117 (extract_nps_rbdouble_64): Added.
118 (insert_nps_proto_size): Added.
119 (extract_nps_proto_size): Added.
121 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
123 * arc-dis.c (struct arc_operand_iterator): Remove all fields
124 relating to long instruction processing, add new limm field.
125 (OPCODE): Rename to...
126 (OPCODE_32BIT_INSN): ...this.
128 (skip_this_opcode): Handle different instruction lengths, update
130 (special_flag_p): Update parameter type.
131 (find_format_from_table): Update for more instruction lengths.
132 (find_format_long_instructions): Delete.
133 (find_format): Update for more instruction lengths.
134 (arc_insn_length): Likewise.
135 (extract_operand_value): Update for more instruction lengths.
136 (operand_iterator_next): Remove code relating to long
138 (arc_opcode_to_insn_type): New function.
139 (print_insn_arc):Update for more instructions lengths.
140 * arc-ext.c (extInstruction_t): Change argument type.
141 * arc-ext.h (extInstruction_t): Change argument type.
142 * arc-fxi.h: Change type unsigned to unsigned long long
143 extensively throughout.
144 * arc-nps400-tbl.h: Add long instructions taken from
145 arc_long_opcodes table in arc-opc.c.
146 * arc-opc.c: Update parameter types on insert/extract handlers.
147 (arc_long_opcodes): Delete.
148 (arc_num_long_opcodes): Delete.
149 (arc_opcode_len): Update for more instruction lengths.
151 2016-11-03 Graham Markall <graham.markall@embecosm.com>
153 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
155 2016-11-03 Graham Markall <graham.markall@embecosm.com>
157 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
159 (find_format_long_instructions): Likewise.
160 * arc-opc.c (arc_opcode_len): New function.
162 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
164 * arc-nps400-tbl.h: Fix some instruction masks.
166 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
168 * i386-dis.c (REG_82): Removed.
169 (X86_64_82_REG_0): Likewise.
170 (X86_64_82_REG_1): Likewise.
171 (X86_64_82_REG_2): Likewise.
172 (X86_64_82_REG_3): Likewise.
173 (X86_64_82_REG_4): Likewise.
174 (X86_64_82_REG_5): Likewise.
175 (X86_64_82_REG_6): Likewise.
176 (X86_64_82_REG_7): Likewise.
178 (dis386): Use X86_64_82 instead of REG_82.
179 (reg_table): Remove REG_82.
180 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
181 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
182 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
185 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
188 * i386-dis.c (REG_82): New.
189 (X86_64_82_REG_0): Likewise.
190 (X86_64_82_REG_1): Likewise.
191 (X86_64_82_REG_2): Likewise.
192 (X86_64_82_REG_3): Likewise.
193 (X86_64_82_REG_4): Likewise.
194 (X86_64_82_REG_5): Likewise.
195 (X86_64_82_REG_6): Likewise.
196 (X86_64_82_REG_7): Likewise.
197 (dis386): Use REG_82.
198 (reg_table): Add REG_82.
199 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
200 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
201 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
203 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
205 * i386-dis.c (REG_82): Renamed to ...
208 (reg_table): Likewise.
210 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
212 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
213 * i386-dis-evex.h (evex_table): Updated.
214 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
215 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
216 (cpu_flags): Add CpuAVX512_4VNNIW.
217 * i386-opc.h (enum): (AVX512_4VNNIW): New.
218 (i386_cpu_flags): Add cpuavx512_4vnniw.
219 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
220 * i386-init.h: Regenerate.
223 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
225 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
226 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
227 * i386-dis-evex.h (evex_table): Updated.
228 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
229 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
230 (cpu_flags): Add CpuAVX512_4FMAPS.
231 (opcode_modifiers): Add ImplicitQuadGroup modifier.
232 * i386-opc.h (AVX512_4FMAP): New.
233 (i386_cpu_flags): Add cpuavx512_4fmaps.
234 (ImplicitQuadGroup): New.
235 (i386_opcode_modifier): Add implicitquadgroup.
236 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
237 * i386-init.h: Regenerate.
240 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
241 Andrew Waterman <andrew@sifive.com>
243 Add support for RISC-V architecture.
244 * configure.ac: Add entry for bfd_riscv_arch.
245 * configure: Regenerate.
246 * disassemble.c (disassembler): Add support for riscv.
247 (disassembler_usage): Likewise.
248 * riscv-dis.c: New file.
249 * riscv-opc.c: New file.
251 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
254 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
255 (rm_table): Update the RM_0FAE_REG_7 entry.
256 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
257 (cpu_flags): Remove CpuPCOMMIT.
258 * i386-opc.h (CpuPCOMMIT): Removed.
259 (i386_cpu_flags): Remove cpupcommit.
260 * i386-opc.tbl: Remove pcommit.
261 * i386-init.h: Regenerated.
262 * i386-tbl.h: Likewise.
264 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
267 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
268 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
269 32-bit mode. Don't check vex.register_specifier in 32-bit
271 (OP_VEX): Check for invalid mask registers.
273 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
276 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
279 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
282 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
284 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
286 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
287 local variable to `index_regno'.
289 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
291 * arc-tbl.h: Removed any "inv.+" instructions from the table.
293 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
295 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
298 2016-10-11 Jiong Wang <jiong.wang@arm.com>
301 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
303 2016-10-07 Jiong Wang <jiong.wang@arm.com>
306 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
309 2016-10-07 Alan Modra <amodra@gmail.com>
311 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
313 2016-10-06 Alan Modra <amodra@gmail.com>
315 * aarch64-opc.c: Spell fall through comments consistently.
316 * i386-dis.c: Likewise.
317 * aarch64-dis.c: Add missing fall through comments.
318 * aarch64-opc.c: Likewise.
319 * arc-dis.c: Likewise.
320 * arm-dis.c: Likewise.
321 * i386-dis.c: Likewise.
322 * m68k-dis.c: Likewise.
323 * mep-asm.c: Likewise.
324 * ns32k-dis.c: Likewise.
325 * sh-dis.c: Likewise.
326 * tic4x-dis.c: Likewise.
327 * tic6x-dis.c: Likewise.
328 * vax-dis.c: Likewise.
330 2016-10-06 Alan Modra <amodra@gmail.com>
332 * arc-ext.c (create_map): Add missing break.
333 * msp430-decode.opc (encode_as): Likewise.
334 * msp430-decode.c: Regenerate.
336 2016-10-06 Alan Modra <amodra@gmail.com>
338 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
339 * crx-dis.c (print_insn_crx): Likewise.
341 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
344 * i386-dis.c (putop): Don't assign alt twice.
346 2016-09-29 Jiong Wang <jiong.wang@arm.com>
349 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
351 2016-09-29 Alan Modra <amodra@gmail.com>
353 * ppc-opc.c (L): Make compulsory.
354 (LOPT): New, optional form of L.
355 (HTM_R): Define as LOPT.
357 (L32OPT): New, optional for 32-bit L.
358 (L2OPT): New, 2-bit L for dcbf.
361 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
362 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
364 <tlbiel, tlbie>: Use LOPT.
365 <wclr, wclrall>: Use L2.
367 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
369 * Makefile.in: Regenerate.
370 * configure: Likewise.
372 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
374 * arc-ext-tbl.h (EXTINSN2OPF): Define.
375 (EXTINSN2OP): Use EXTINSN2OPF.
376 (bspeekm, bspop, modapp): New extension instructions.
377 * arc-opc.c (F_DNZ_ND): Define.
382 * arc-tbl.h (dbnz): New instruction.
383 (prealloc): Allow it for ARC EM.
386 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
388 * aarch64-opc.c (print_immediate_offset_address): Print spaces
389 after commas in addresses.
390 (aarch64_print_operand): Likewise.
392 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
394 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
395 rather than "should be" or "expected to be" in error messages.
397 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
399 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
400 (print_mnemonic_name): ...here.
401 (print_comment): New function.
402 (print_aarch64_insn): Call it.
403 * aarch64-opc.c (aarch64_conds): Add SVE names.
404 (aarch64_print_operand): Print alternative condition names in
407 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
409 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
410 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
411 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
412 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
413 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
414 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
415 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
416 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
417 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
418 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
419 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
420 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
421 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
422 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
423 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
424 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
425 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
426 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
427 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
428 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
429 (OP_SVE_XWU, OP_SVE_XXU): New macros.
430 (aarch64_feature_sve): New variable.
432 (_SVE_INSN): Likewise.
433 (aarch64_opcode_table): Add SVE instructions.
434 * aarch64-opc.h (extract_fields): Declare.
435 * aarch64-opc-2.c: Regenerate.
436 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
437 * aarch64-asm-2.c: Regenerate.
438 * aarch64-dis.c (extract_fields): Make global.
439 (do_misc_decoding): Handle the new SVE aarch64_ops.
440 * aarch64-dis-2.c: Regenerate.
442 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
444 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
445 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
447 * aarch64-opc.c (fields): Add corresponding entries.
448 * aarch64-asm.c (aarch64_get_variant): New function.
449 (aarch64_encode_variant_using_iclass): Likewise.
450 (aarch64_opcode_encode): Call it.
451 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
452 (aarch64_opcode_decode): Call it.
454 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
456 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
457 and FP register operands.
458 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
459 (FLD_SVE_Vn): New aarch64_field_kinds.
460 * aarch64-opc.c (fields): Add corresponding entries.
461 (aarch64_print_operand): Handle the new SVE core and FP register
463 * aarch64-opc-2.c: Regenerate.
464 * aarch64-asm-2.c: Likewise.
465 * aarch64-dis-2.c: Likewise.
467 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
469 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
471 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
472 * aarch64-opc.c (fields): Add corresponding entry.
473 (operand_general_constraint_met_p): Handle the new SVE FP immediate
475 (aarch64_print_operand): Likewise.
476 * aarch64-opc-2.c: Regenerate.
477 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
478 (ins_sve_float_zero_one): New inserters.
479 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
480 (aarch64_ins_sve_float_half_two): Likewise.
481 (aarch64_ins_sve_float_zero_one): Likewise.
482 * aarch64-asm-2.c: Regenerate.
483 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
484 (ext_sve_float_zero_one): New extractors.
485 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
486 (aarch64_ext_sve_float_half_two): Likewise.
487 (aarch64_ext_sve_float_zero_one): Likewise.
488 * aarch64-dis-2.c: Regenerate.
490 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
492 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
493 integer immediate operands.
494 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
495 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
496 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
497 * aarch64-opc.c (fields): Add corresponding entries.
498 (operand_general_constraint_met_p): Handle the new SVE integer
500 (aarch64_print_operand): Likewise.
501 (aarch64_sve_dupm_mov_immediate_p): New function.
502 * aarch64-opc-2.c: Regenerate.
503 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
504 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
505 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
506 (aarch64_ins_limm): ...here.
507 (aarch64_ins_inv_limm): New function.
508 (aarch64_ins_sve_aimm): Likewise.
509 (aarch64_ins_sve_asimm): Likewise.
510 (aarch64_ins_sve_limm_mov): Likewise.
511 (aarch64_ins_sve_shlimm): Likewise.
512 (aarch64_ins_sve_shrimm): Likewise.
513 * aarch64-asm-2.c: Regenerate.
514 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
515 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
516 * aarch64-dis.c (decode_limm): New function, split out from...
517 (aarch64_ext_limm): ...here.
518 (aarch64_ext_inv_limm): New function.
519 (decode_sve_aimm): Likewise.
520 (aarch64_ext_sve_aimm): Likewise.
521 (aarch64_ext_sve_asimm): Likewise.
522 (aarch64_ext_sve_limm_mov): Likewise.
523 (aarch64_top_bit): Likewise.
524 (aarch64_ext_sve_shlimm): Likewise.
525 (aarch64_ext_sve_shrimm): Likewise.
526 * aarch64-dis-2.c: Regenerate.
528 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
530 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
532 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
533 the AARCH64_MOD_MUL_VL entry.
534 (value_aligned_p): Cope with non-power-of-two alignments.
535 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
536 (print_immediate_offset_address): Likewise.
537 (aarch64_print_operand): Likewise.
538 * aarch64-opc-2.c: Regenerate.
539 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
540 (ins_sve_addr_ri_s9xvl): New inserters.
541 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
542 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
543 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
544 * aarch64-asm-2.c: Regenerate.
545 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
546 (ext_sve_addr_ri_s9xvl): New extractors.
547 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
548 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
549 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
550 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
551 * aarch64-dis-2.c: Regenerate.
553 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
555 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
557 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
558 (FLD_SVE_xs_22): New aarch64_field_kinds.
559 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
560 (get_operand_specific_data): New function.
561 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
562 FLD_SVE_xs_14 and FLD_SVE_xs_22.
563 (operand_general_constraint_met_p): Handle the new SVE address
565 (sve_reg): New array.
566 (get_addr_sve_reg_name): New function.
567 (aarch64_print_operand): Handle the new SVE address operands.
568 * aarch64-opc-2.c: Regenerate.
569 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
570 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
571 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
572 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
573 (aarch64_ins_sve_addr_rr_lsl): Likewise.
574 (aarch64_ins_sve_addr_rz_xtw): Likewise.
575 (aarch64_ins_sve_addr_zi_u5): Likewise.
576 (aarch64_ins_sve_addr_zz): Likewise.
577 (aarch64_ins_sve_addr_zz_lsl): Likewise.
578 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
579 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
580 * aarch64-asm-2.c: Regenerate.
581 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
582 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
583 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
584 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
585 (aarch64_ext_sve_addr_ri_u6): Likewise.
586 (aarch64_ext_sve_addr_rr_lsl): Likewise.
587 (aarch64_ext_sve_addr_rz_xtw): Likewise.
588 (aarch64_ext_sve_addr_zi_u5): Likewise.
589 (aarch64_ext_sve_addr_zz): Likewise.
590 (aarch64_ext_sve_addr_zz_lsl): Likewise.
591 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
592 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
593 * aarch64-dis-2.c: Regenerate.
595 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
597 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
598 AARCH64_OPND_SVE_PATTERN_SCALED.
599 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
600 * aarch64-opc.c (fields): Add a corresponding entry.
601 (set_multiplier_out_of_range_error): New function.
602 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
603 (operand_general_constraint_met_p): Handle
604 AARCH64_OPND_SVE_PATTERN_SCALED.
605 (print_register_offset_address): Use PRIi64 to print the
607 (aarch64_print_operand): Likewise. Handle
608 AARCH64_OPND_SVE_PATTERN_SCALED.
609 * aarch64-opc-2.c: Regenerate.
610 * aarch64-asm.h (ins_sve_scale): New inserter.
611 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
612 * aarch64-asm-2.c: Regenerate.
613 * aarch64-dis.h (ext_sve_scale): New inserter.
614 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
615 * aarch64-dis-2.c: Regenerate.
617 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
619 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
620 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
621 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
622 (FLD_SVE_prfop): Likewise.
623 * aarch64-opc.c: Include libiberty.h.
624 (aarch64_sve_pattern_array): New variable.
625 (aarch64_sve_prfop_array): Likewise.
626 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
627 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
628 AARCH64_OPND_SVE_PRFOP.
629 * aarch64-asm-2.c: Regenerate.
630 * aarch64-dis-2.c: Likewise.
631 * aarch64-opc-2.c: Likewise.
633 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
635 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
636 AARCH64_OPND_QLF_P_[ZM].
637 (aarch64_print_operand): Print /z and /m where appropriate.
639 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
641 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
642 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
643 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
644 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
645 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
646 * aarch64-opc.c (fields): Add corresponding entries here.
647 (operand_general_constraint_met_p): Check that SVE register lists
648 have the correct length. Check the ranges of SVE index registers.
649 Check for cases where p8-p15 are used in 3-bit predicate fields.
650 (aarch64_print_operand): Handle the new SVE operands.
651 * aarch64-opc-2.c: Regenerate.
652 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
653 * aarch64-asm.c (aarch64_ins_sve_index): New function.
654 (aarch64_ins_sve_reglist): Likewise.
655 * aarch64-asm-2.c: Regenerate.
656 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
657 * aarch64-dis.c (aarch64_ext_sve_index): New function.
658 (aarch64_ext_sve_reglist): Likewise.
659 * aarch64-dis-2.c: Regenerate.
661 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
663 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
664 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
665 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
666 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
669 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
671 * aarch64-opc.c (get_offset_int_reg_name): New function.
672 (print_immediate_offset_address): Likewise.
673 (print_register_offset_address): Take the base and offset
674 registers as parameters.
675 (aarch64_print_operand): Update caller accordingly. Use
676 print_immediate_offset_address.
678 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
680 * aarch64-opc.c (BANK): New macro.
681 (R32, R64): Take a register number as argument
684 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
686 * aarch64-opc.c (print_register_list): Add a prefix parameter.
687 (aarch64_print_operand): Update accordingly.
689 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
691 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
693 * aarch64-asm.h (ins_fpimm): New inserter.
694 * aarch64-asm.c (aarch64_ins_fpimm): New function.
695 * aarch64-asm-2.c: Regenerate.
696 * aarch64-dis.h (ext_fpimm): New extractor.
697 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
698 (aarch64_ext_fpimm): New function.
699 * aarch64-dis-2.c: Regenerate.
701 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
703 * aarch64-asm.c: Include libiberty.h.
704 (insert_fields): New function.
705 (aarch64_ins_imm): Use it.
706 * aarch64-dis.c (extract_fields): New function.
707 (aarch64_ext_imm): Use it.
709 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
711 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
712 with an esize parameter.
713 (operand_general_constraint_met_p): Update accordingly.
714 Fix misindented code.
715 * aarch64-asm.c (aarch64_ins_limm): Update call to
716 aarch64_logical_immediate_p.
718 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
720 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
722 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
724 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
726 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
728 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
730 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
732 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
733 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
734 xor3>: Delete mnemonics.
735 <cp_abort>: Rename mnemonic from ...
736 <cpabort>: ...to this.
737 <setb>: Change to a X form instruction.
738 <sync>: Change to 1 operand form.
739 <copy>: Delete mnemonic.
740 <copy_first>: Rename mnemonic from ...
742 <paste, paste.>: Delete mnemonics.
743 <paste_last>: Rename mnemonic from ...
744 <paste.>: ...to this.
746 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
748 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
750 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
752 * s390-mkopc.c (main): Support alternate arch strings.
754 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
756 * s390-opc.txt: Fix kmctr instruction type.
758 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
760 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
761 * i386-init.h: Regenerated.
763 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
765 * opcodes/arc-dis.c (print_insn_arc): Changed.
767 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
769 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
772 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
774 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
775 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
776 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
778 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
780 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
781 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
782 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
783 PREFIX_MOD_3_0FAE_REG_4.
784 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
785 PREFIX_MOD_3_0FAE_REG_4.
786 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
787 (cpu_flags): Add CpuPTWRITE.
788 * i386-opc.h (CpuPTWRITE): New.
789 (i386_cpu_flags): Add cpuptwrite.
790 * i386-opc.tbl: Add ptwrite instruction.
791 * i386-init.h: Regenerated.
792 * i386-tbl.h: Likewise.
794 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
796 * arc-dis.h: Wrap around in extern "C".
798 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
800 * aarch64-tbl.h (V8_2_INSN): New macro.
801 (aarch64_opcode_table): Use it.
803 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
805 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
806 CORE_INSN, __FP_INSN and SIMD_INSN.
808 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
810 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
811 (aarch64_opcode_table): Update uses accordingly.
813 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
814 Kwok Cheung Yeung <kcy@codesourcery.com>
817 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
818 'e_cmplwi' to 'e_cmpli' instead.
819 (OPVUPRT, OPVUPRT_MASK): Define.
820 (powerpc_opcodes): Add E200Z4 insns.
821 (vle_opcodes): Add context save/restore insns.
823 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
825 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
826 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
829 2016-07-27 Graham Markall <graham.markall@embecosm.com>
831 * arc-nps400-tbl.h: Change block comments to GNU format.
832 * arc-dis.c: Add new globals addrtypenames,
833 addrtypenames_max, and addtypeunknown.
834 (get_addrtype): New function.
835 (print_insn_arc): Print colons and address types when
837 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
838 define insert and extract functions for all address types.
839 (arc_operands): Add operands for colon and all address
841 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
842 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
843 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
844 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
845 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
846 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
848 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
850 * configure: Regenerated.
852 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
854 * arc-dis.c (skipclass): New structure.
855 (decodelist): New variable.
856 (is_compatible_p): New function.
857 (new_element): Likewise.
858 (skip_class_p): Likewise.
859 (find_format_from_table): Use skip_class_p function.
860 (find_format): Decode first the extension instructions.
861 (print_insn_arc): Select either ARCEM or ARCHS based on elf
863 (parse_option): New function.
864 (parse_disassembler_options): Likewise.
865 (print_arc_disassembler_options): Likewise.
866 (print_insn_arc): Use parse_disassembler_options function. Proper
867 select ARCv2 cpu variant.
868 * disassemble.c (disassembler_usage): Add ARC disassembler
871 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
873 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
874 annotation from the "nal" entry and reorder it beyond "bltzal".
876 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
878 * sparc-opc.c (ldtxa): New macro.
879 (sparc_opcodes): Use the macro defined above to add entries for
880 the LDTXA instructions.
881 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
884 2016-07-07 James Bowman <james.bowman@ftdichip.com>
886 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
889 2016-07-01 Jan Beulich <jbeulich@suse.com>
891 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
892 (movzb): Adjust to cover all permitted suffixes.
894 * i386-tbl.h: Re-generate.
896 2016-07-01 Jan Beulich <jbeulich@suse.com>
898 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
899 (lgdt): Remove Tbyte from non-64-bit variant.
900 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
901 xsaves64, xsavec64): Remove Disp16.
902 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
903 Remove Disp32S from non-64-bit variants. Remove Disp16 from
905 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
906 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
907 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
909 * i386-tbl.h: Re-generate.
911 2016-07-01 Jan Beulich <jbeulich@suse.com>
913 * i386-opc.tbl (xlat): Remove RepPrefixOk.
914 * i386-tbl.h: Re-generate.
916 2016-06-30 Yao Qi <yao.qi@linaro.org>
918 * arm-dis.c (print_insn): Fix typo in comment.
920 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
922 * aarch64-opc.c (operand_general_constraint_met_p): Check the
923 range of ldst_elemlist operands.
924 (print_register_list): Use PRIi64 to print the index.
925 (aarch64_print_operand): Likewise.
927 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
929 * mcore-opc.h: Remove sentinal.
930 * mcore-dis.c (print_insn_mcore): Adjust.
932 2016-06-23 Graham Markall <graham.markall@embecosm.com>
934 * arc-opc.c: Correct description of availability of NPS400
937 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
939 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
940 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
941 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
942 xor3>: New mnemonics.
943 <setb>: Change to a VX form instruction.
944 (insert_sh6): Add support for rldixor.
945 (extract_sh6): Likewise.
947 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
949 * arc-ext.h: Wrap in extern C.
951 2016-06-21 Graham Markall <graham.markall@embecosm.com>
953 * arc-dis.c (arc_insn_length): Add comment on instruction length.
954 Use same method for determining instruction length on ARC700 and
956 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
957 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
958 with the NPS400 subclass.
959 * arc-opc.c: Likewise.
961 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
963 * sparc-opc.c (rdasr): New macro.
969 (sparc_opcodes): Use the macros above to fix and expand the
970 definition of read/write instructions from/to
971 asr/privileged/hyperprivileged instructions.
972 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
973 %hva_mask_nz. Prefer softint_set and softint_clear over
974 set_softint and clear_softint.
975 (print_insn_sparc): Support %ver in Rd.
977 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
979 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
980 architecture according to the hardware capabilities they require.
982 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
984 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
985 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
986 bfd_mach_sparc_v9{c,d,e,v,m}.
987 * sparc-opc.c (MASK_V9C): Define.
988 (MASK_V9D): Likewise.
989 (MASK_V9E): Likewise.
990 (MASK_V9V): Likewise.
991 (MASK_V9M): Likewise.
992 (v6): Add MASK_V9{C,D,E,V,M}.
993 (v6notlet): Likewise.
997 (v9andleon): Likewise.
1005 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1007 2016-06-15 Nick Clifton <nickc@redhat.com>
1009 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1010 constants to match expected behaviour.
1011 (nds32_parse_opcode): Likewise. Also for whitespace.
1013 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1015 * arc-opc.c (extract_rhv1): Extract value from insn.
1017 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1019 * arc-nps400-tbl.h: Add ldbit instruction.
1020 * arc-opc.c: Add flag classes required for ldbit.
1022 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1024 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1025 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1026 support the above instructions.
1028 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1030 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1031 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1032 csma, cbba, zncv, and hofs.
1033 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1034 support the above instructions.
1036 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1038 * arc-nps400-tbl.h: Add andab and orab instructions.
1040 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1042 * arc-nps400-tbl.h: Add addl-like instructions.
1044 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1046 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1048 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1050 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1053 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1055 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1057 (init_disasm): Handle new command line option "insnlength".
1058 (print_s390_disassembler_options): Mention new option in help
1060 (print_insn_s390): Use the encoded insn length when dumping
1061 unknown instructions.
1063 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1065 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1066 to the address and set as symbol address for LDS/ STS immediate operands.
1068 2016-06-07 Alan Modra <amodra@gmail.com>
1070 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1071 cpu for "vle" to e500.
1072 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1073 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1074 (PPCNONE): Delete, substitute throughout.
1075 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1076 except for major opcode 4 and 31.
1077 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1079 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1081 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1082 ARM_EXT_RAS in relevant entries.
1084 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1087 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1090 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1093 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1094 (indir_v_mode): New.
1095 Add comments for '&'.
1096 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1097 (putop): Handle '&'.
1098 (intel_operand_size): Handle indir_v_mode.
1099 (OP_E_register): Likewise.
1100 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1101 64-bit indirect call/jmp for AMD64.
1102 * i386-tbl.h: Regenerated
1104 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1106 * arc-dis.c (struct arc_operand_iterator): New structure.
1107 (find_format_from_table): All the old content from find_format,
1108 with some minor adjustments, and parameter renaming.
1109 (find_format_long_instructions): New function.
1110 (find_format): Rewritten.
1111 (arc_insn_length): Add LSB parameter.
1112 (extract_operand_value): New function.
1113 (operand_iterator_next): New function.
1114 (print_insn_arc): Use new functions to find opcode, and iterator
1116 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1117 (extract_nps_3bit_dst_short): New function.
1118 (insert_nps_3bit_src2_short): New function.
1119 (extract_nps_3bit_src2_short): New function.
1120 (insert_nps_bitop1_size): New function.
1121 (extract_nps_bitop1_size): New function.
1122 (insert_nps_bitop2_size): New function.
1123 (extract_nps_bitop2_size): New function.
1124 (insert_nps_bitop_mod4_msb): New function.
1125 (extract_nps_bitop_mod4_msb): New function.
1126 (insert_nps_bitop_mod4_lsb): New function.
1127 (extract_nps_bitop_mod4_lsb): New function.
1128 (insert_nps_bitop_dst_pos3_pos4): New function.
1129 (extract_nps_bitop_dst_pos3_pos4): New function.
1130 (insert_nps_bitop_ins_ext): New function.
1131 (extract_nps_bitop_ins_ext): New function.
1132 (arc_operands): Add new operands.
1133 (arc_long_opcodes): New global array.
1134 (arc_num_long_opcodes): New global.
1135 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1137 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1139 * nds32-asm.h: Add extern "C".
1140 * sh-opc.h: Likewise.
1142 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1144 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1145 0,b,limm to the rflt instruction.
1147 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1149 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1152 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1155 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1156 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1157 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1158 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1159 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1160 * i386-init.h: Regenerated.
1162 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1165 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1166 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1167 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1168 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1169 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1170 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1171 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1172 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1173 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1174 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1175 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1176 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1177 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1178 CpuRegMask for AVX512.
1179 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1181 (set_bitfield_from_cpu_flag_init): New function.
1182 (set_bitfield): Remove const on f. Call
1183 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1184 * i386-opc.h (CpuRegMMX): New.
1185 (CpuRegXMM): Likewise.
1186 (CpuRegYMM): Likewise.
1187 (CpuRegZMM): Likewise.
1188 (CpuRegMask): Likewise.
1189 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1191 * i386-init.h: Regenerated.
1192 * i386-tbl.h: Likewise.
1194 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1197 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1198 (opcode_modifiers): Add AMD64 and Intel64.
1199 (main): Properly verify CpuMax.
1200 * i386-opc.h (CpuAMD64): Removed.
1201 (CpuIntel64): Likewise.
1202 (CpuMax): Set to CpuNo64.
1203 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1205 (Intel64): Likewise.
1206 (i386_opcode_modifier): Add amd64 and intel64.
1207 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1209 * i386-init.h: Regenerated.
1210 * i386-tbl.h: Likewise.
1212 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1215 * i386-gen.c (main): Fail if CpuMax is incorrect.
1216 * i386-opc.h (CpuMax): Set to CpuIntel64.
1217 * i386-tbl.h: Regenerated.
1219 2016-05-27 Nick Clifton <nickc@redhat.com>
1222 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1223 (msp430dis_opcode_unsigned): New function.
1224 (msp430dis_opcode_signed): New function.
1225 (msp430_singleoperand): Use the new opcode reading functions.
1226 Only disassenmble bytes if they were successfully read.
1227 (msp430_doubleoperand): Likewise.
1228 (msp430_branchinstr): Likewise.
1229 (msp430x_callx_instr): Likewise.
1230 (print_insn_msp430): Check that it is safe to read bytes before
1231 attempting disassembly. Use the new opcode reading functions.
1233 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1235 * ppc-opc.c (CY): New define. Document it.
1236 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1238 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1240 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1241 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1242 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1243 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1245 * i386-init.h: Regenerated.
1247 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1250 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1251 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1252 * i386-init.h: Regenerated.
1254 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1256 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1257 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1258 * i386-init.h: Regenerated.
1260 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1262 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1264 (print_insn_arc): Set insn_type information.
1265 * arc-opc.c (C_CC): Add F_CLASS_COND.
1266 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1267 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1268 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1269 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1270 (brne, brne_s, jeq_s, jne_s): Likewise.
1272 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1274 * arc-tbl.h (neg): New instruction variant.
1276 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1278 * arc-dis.c (find_format, find_format, get_auxreg)
1279 (print_insn_arc): Changed.
1280 * arc-ext.h (INSERT_XOP): Likewise.
1282 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1284 * tic54x-dis.c (sprint_mmr): Adjust.
1285 * tic54x-opc.c: Likewise.
1287 2016-05-19 Alan Modra <amodra@gmail.com>
1289 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1291 2016-05-19 Alan Modra <amodra@gmail.com>
1293 * ppc-opc.c: Formatting.
1294 (NSISIGNOPT): Define.
1295 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1297 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1299 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1300 replacing references to `micromips_ase' throughout.
1301 (_print_insn_mips): Don't use file-level microMIPS annotation to
1302 determine the disassembly mode with the symbol table.
1304 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1306 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1308 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1310 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1312 * mips-opc.c (D34): New macro.
1313 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1315 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1317 * i386-dis.c (prefix_table): Add RDPID instruction.
1318 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1319 (cpu_flags): Add RDPID bitfield.
1320 * i386-opc.h (enum): Add RDPID element.
1321 (i386_cpu_flags): Add RDPID field.
1322 * i386-opc.tbl: Add RDPID instruction.
1323 * i386-init.h: Regenerate.
1324 * i386-tbl.h: Regenerate.
1326 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1328 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1329 branch type of a symbol.
1330 (print_insn): Likewise.
1332 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1334 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1335 Mainline Security Extensions instructions.
1336 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1337 Extensions instructions.
1338 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1340 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1343 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1345 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1347 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1349 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1350 (arcExtMap_genOpcode): Likewise.
1351 * arc-opc.c (arg_32bit_rc): Define new variable.
1352 (arg_32bit_u6): Likewise.
1353 (arg_32bit_limm): Likewise.
1355 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1357 * aarch64-gen.c (VERIFIER): Define.
1358 * aarch64-opc.c (VERIFIER): Define.
1359 (verify_ldpsw): Use static linkage.
1360 * aarch64-opc.h (verify_ldpsw): Remove.
1361 * aarch64-tbl.h: Use VERIFIER for verifiers.
1363 2016-04-28 Nick Clifton <nickc@redhat.com>
1366 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1367 * aarch64-opc.c (verify_ldpsw): New function.
1368 * aarch64-opc.h (verify_ldpsw): New prototype.
1369 * aarch64-tbl.h: Add initialiser for verifier field.
1370 (LDPSW): Set verifier to verify_ldpsw.
1372 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1376 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1377 smaller than address size.
1379 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1381 * alpha-dis.c: Regenerate.
1382 * crx-dis.c: Likewise.
1383 * disassemble.c: Likewise.
1384 * epiphany-opc.c: Likewise.
1385 * fr30-opc.c: Likewise.
1386 * frv-opc.c: Likewise.
1387 * ip2k-opc.c: Likewise.
1388 * iq2000-opc.c: Likewise.
1389 * lm32-opc.c: Likewise.
1390 * lm32-opinst.c: Likewise.
1391 * m32c-opc.c: Likewise.
1392 * m32r-opc.c: Likewise.
1393 * m32r-opinst.c: Likewise.
1394 * mep-opc.c: Likewise.
1395 * mt-opc.c: Likewise.
1396 * or1k-opc.c: Likewise.
1397 * or1k-opinst.c: Likewise.
1398 * tic80-opc.c: Likewise.
1399 * xc16x-opc.c: Likewise.
1400 * xstormy16-opc.c: Likewise.
1402 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1404 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1405 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1406 calcsd, and calcxd instructions.
1407 * arc-opc.c (insert_nps_bitop_size): Delete.
1408 (extract_nps_bitop_size): Delete.
1409 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1410 (extract_nps_qcmp_m3): Define.
1411 (extract_nps_qcmp_m2): Define.
1412 (extract_nps_qcmp_m1): Define.
1413 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1414 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1415 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1416 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1417 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1420 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1422 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1424 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1426 * Makefile.in: Regenerated with automake 1.11.6.
1427 * aclocal.m4: Likewise.
1429 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1431 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1433 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1434 (extract_nps_cmem_uimm16): New function.
1435 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1437 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1439 * arc-dis.c (arc_insn_length): New function.
1440 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1441 (find_format): Change insnLen parameter to unsigned.
1443 2016-04-13 Nick Clifton <nickc@redhat.com>
1446 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1447 the LD.B and LD.BU instructions.
1449 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1451 * arc-dis.c (find_format): Check for extension flags.
1452 (print_flags): New function.
1453 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1455 * arc-ext.c (arcExtMap_coreRegName): Use
1456 LAST_EXTENSION_CORE_REGISTER.
1457 (arcExtMap_coreReadWrite): Likewise.
1458 (dump_ARC_extmap): Update printing.
1459 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1460 (arc_aux_regs): Add cpu field.
1461 * arc-regs.h: Add cpu field, lower case name aux registers.
1463 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1465 * arc-tbl.h: Add rtsc, sleep with no arguments.
1467 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1469 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1471 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1472 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1473 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1474 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1475 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1476 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1477 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1478 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1479 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1480 (arc_opcode arc_opcodes): Null terminate the array.
1481 (arc_num_opcodes): Remove.
1482 * arc-ext.h (INSERT_XOP): Define.
1483 (extInstruction_t): Likewise.
1484 (arcExtMap_instName): Delete.
1485 (arcExtMap_insn): New function.
1486 (arcExtMap_genOpcode): Likewise.
1487 * arc-ext.c (ExtInstruction): Remove.
1488 (create_map): Zero initialize instruction fields.
1489 (arcExtMap_instName): Remove.
1490 (arcExtMap_insn): New function.
1491 (dump_ARC_extmap): More info while debuging.
1492 (arcExtMap_genOpcode): New function.
1493 * arc-dis.c (find_format): New function.
1494 (print_insn_arc): Use find_format.
1495 (arc_get_disassembler): Enable dump_ARC_extmap only when
1498 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1500 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1501 instruction bits out.
1503 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1505 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1506 * arc-opc.c (arc_flag_operands): Add new flags.
1507 (arc_flag_classes): Add new classes.
1509 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1511 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1513 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1515 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1516 encode1, rflt, crc16, and crc32 instructions.
1517 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1518 (arc_flag_classes): Add C_NPS_R.
1519 (insert_nps_bitop_size_2b): New function.
1520 (extract_nps_bitop_size_2b): Likewise.
1521 (insert_nps_bitop_uimm8): Likewise.
1522 (extract_nps_bitop_uimm8): Likewise.
1523 (arc_operands): Add new operand entries.
1525 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1527 * arc-regs.h: Add a new subclass field. Add double assist
1528 accumulator register values.
1529 * arc-tbl.h: Use DPA subclass to mark the double assist
1530 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1531 * arc-opc.c (RSP): Define instead of SP.
1532 (arc_aux_regs): Add the subclass field.
1534 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1536 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1538 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1540 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1543 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1545 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1546 issues. No functional changes.
1548 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1550 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1551 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1552 (RTT): Remove duplicate.
1553 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1554 (PCT_CONFIG*): Remove.
1555 (D1L, D1H, D2H, D2L): Define.
1557 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1559 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1561 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1563 * arc-tbl.h (invld07): Remove.
1564 * arc-ext-tbl.h: New file.
1565 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1566 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1568 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1570 Fix -Wstack-usage warnings.
1571 * aarch64-dis.c (print_operands): Substitute size.
1572 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1574 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1576 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1577 to get a proper diagnostic when an invalid ASR register is used.
1579 2016-03-22 Nick Clifton <nickc@redhat.com>
1581 * configure: Regenerate.
1583 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1585 * arc-nps400-tbl.h: New file.
1586 * arc-opc.c: Add top level comment.
1587 (insert_nps_3bit_dst): New function.
1588 (extract_nps_3bit_dst): New function.
1589 (insert_nps_3bit_src2): New function.
1590 (extract_nps_3bit_src2): New function.
1591 (insert_nps_bitop_size): New function.
1592 (extract_nps_bitop_size): New function.
1593 (arc_flag_operands): Add nps400 entries.
1594 (arc_flag_classes): Add nps400 entries.
1595 (arc_operands): Add nps400 entries.
1596 (arc_opcodes): Add nps400 include.
1598 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1600 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1601 the new class enum values.
1603 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1605 * arc-dis.c (print_insn_arc): Handle nps400.
1607 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1609 * arc-opc.c (BASE): Delete.
1611 2016-03-18 Nick Clifton <nickc@redhat.com>
1614 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1615 of MOV insn that aliases an ORR insn.
1617 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1619 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1621 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1623 * mcore-opc.h: Add const qualifiers.
1624 * microblaze-opc.h (struct op_code_struct): Likewise.
1625 * sh-opc.h: Likewise.
1626 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1627 (tic4x_print_op): Likewise.
1629 2016-03-02 Alan Modra <amodra@gmail.com>
1631 * or1k-desc.h: Regenerate.
1632 * fr30-ibld.c: Regenerate.
1633 * rl78-decode.c: Regenerate.
1635 2016-03-01 Nick Clifton <nickc@redhat.com>
1638 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1640 2016-02-24 Renlin Li <renlin.li@arm.com>
1642 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1643 (print_insn_coprocessor): Support fp16 instructions.
1645 2016-02-24 Renlin Li <renlin.li@arm.com>
1647 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1648 vminnm, vrint(mpna).
1650 2016-02-24 Renlin Li <renlin.li@arm.com>
1652 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1653 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1655 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1657 * i386-dis.c (print_insn): Parenthesize expression to prevent
1658 truncated addresses.
1661 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1662 Janek van Oirschot <jvanoirs@synopsys.com>
1664 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1667 2016-02-04 Nick Clifton <nickc@redhat.com>
1670 * msp430-dis.c (print_insn_msp430): Add a special case for
1671 decoding an RRC instruction with the ZC bit set in the extension
1674 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1676 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1677 * epiphany-ibld.c: Regenerate.
1678 * fr30-ibld.c: Regenerate.
1679 * frv-ibld.c: Regenerate.
1680 * ip2k-ibld.c: Regenerate.
1681 * iq2000-ibld.c: Regenerate.
1682 * lm32-ibld.c: Regenerate.
1683 * m32c-ibld.c: Regenerate.
1684 * m32r-ibld.c: Regenerate.
1685 * mep-ibld.c: Regenerate.
1686 * mt-ibld.c: Regenerate.
1687 * or1k-ibld.c: Regenerate.
1688 * xc16x-ibld.c: Regenerate.
1689 * xstormy16-ibld.c: Regenerate.
1691 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1693 * epiphany-dis.c: Regenerated from latest cpu files.
1695 2016-02-01 Michael McConville <mmcco@mykolab.com>
1697 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1700 2016-01-25 Renlin Li <renlin.li@arm.com>
1702 * arm-dis.c (mapping_symbol_for_insn): New function.
1703 (find_ifthen_state): Call mapping_symbol_for_insn().
1705 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1707 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1708 of MSR UAO immediate operand.
1710 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1712 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1713 instruction support.
1715 2016-01-17 Alan Modra <amodra@gmail.com>
1717 * configure: Regenerate.
1719 2016-01-14 Nick Clifton <nickc@redhat.com>
1721 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1722 instructions that can support stack pointer operations.
1723 * rl78-decode.c: Regenerate.
1724 * rl78-dis.c: Fix display of stack pointer in MOVW based
1727 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1729 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1730 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1731 erxtatus_el1 and erxaddr_el1.
1733 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1735 * arm-dis.c (arm_opcodes): Add "esb".
1736 (thumb_opcodes): Likewise.
1738 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1740 * ppc-opc.c <xscmpnedp>: Delete.
1741 <xvcmpnedp>: Likewise.
1742 <xvcmpnedp.>: Likewise.
1743 <xvcmpnesp>: Likewise.
1744 <xvcmpnesp.>: Likewise.
1746 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1749 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1752 2016-01-01 Alan Modra <amodra@gmail.com>
1754 Update year range in copyright notice of all files.
1756 For older changes see ChangeLog-2015
1758 Copyright (C) 2016 Free Software Foundation, Inc.
1760 Copying and distribution of this file, with or without modification,
1761 are permitted in any medium without royalty provided the copyright
1762 notice and this notice are preserved.
1768 version-control: never