1 2018-09-13 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
4 * i386-tbl.h: Re-generate.
6 2018-09-13 Jan Beulich <jbeulich@suse.com>
8 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
9 * i386-tbl.h: Re-generate.
11 2018-09-13 Jan Beulich <jbeulich@suse.com>
13 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
15 * i386-tbl.h: Re-generate.
17 2018-09-13 Jan Beulich <jbeulich@suse.com>
19 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
21 * i386-tbl.h: Re-generate.
23 2018-09-13 Jan Beulich <jbeulich@suse.com>
25 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
26 * i386-tbl.h: Re-generate.
28 2018-09-13 Jan Beulich <jbeulich@suse.com>
30 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
31 * i386-tbl.h: Re-generate.
33 2018-09-13 Jan Beulich <jbeulich@suse.com>
35 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
36 * i386-tbl.h: Re-generate.
38 2018-09-13 Jan Beulich <jbeulich@suse.com>
40 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
42 * i386-tbl.h: Re-generate.
44 2018-09-13 Jan Beulich <jbeulich@suse.com>
46 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
48 * i386-tbl.h: Re-generate.
50 2018-09-13 Jan Beulich <jbeulich@suse.com>
52 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
54 * i386-tbl.h: Re-generate.
56 2018-09-13 Jan Beulich <jbeulich@suse.com>
58 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
59 * i386-tbl.h: Re-generate.
61 2018-09-13 Jan Beulich <jbeulich@suse.com>
63 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
64 * i386-tbl.h: Re-generate.
66 2018-09-13 Jan Beulich <jbeulich@suse.com>
68 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
69 * i386-tbl.h: Re-generate.
71 2018-09-13 Jan Beulich <jbeulich@suse.com>
73 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
74 (vpbroadcastw, rdpid): Drop NoRex64.
75 * i386-tbl.h: Re-generate.
77 2018-09-13 Jan Beulich <jbeulich@suse.com>
79 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
80 store templates, adding D.
81 * i386-tbl.h: Re-generate.
83 2018-09-13 Jan Beulich <jbeulich@suse.com>
85 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
86 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
87 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
88 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
89 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
90 Fold load and store templates where possible, adding D. Drop
91 IgnoreSize where it was pointlessly present. Drop redundant
93 * i386-tbl.h: Re-generate.
95 2018-09-13 Jan Beulich <jbeulich@suse.com>
97 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
98 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
99 (intel_operand_size): Handle v_bndmk_mode.
100 (OP_E_memory): Likewise. Produce (bad) when also riprel.
102 2018-09-08 John Darrington <john@darrington.wattle.id.au>
104 * disassemble.c (ARCH_s12z): Define if ARCH_all.
106 2018-08-31 Kito Cheng <kito@andestech.com>
108 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
109 compressed floating point instructions.
111 2018-08-30 Kito Cheng <kito@andestech.com>
113 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
114 riscv_opcode.xlen_requirement.
115 * riscv-opc.c (riscv_opcodes): Update for struct change.
117 2018-08-29 Martin Aberg <maberg@gaisler.com>
119 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
120 psr (PWRPSR) instruction.
122 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
124 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
126 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
128 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
130 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
132 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
133 loongson3a as an alias of gs464 for compatibility.
134 * mips-opc.c (mips_opcodes): Change Comments.
136 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
138 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
140 (print_mips_disassembler_options): Document -M loongson-ext.
141 * mips-opc.c (LEXT2): New macro.
142 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
144 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
146 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
148 (parse_mips_ase_option): Handle -M loongson-ext option.
149 (print_mips_disassembler_options): Document -M loongson-ext.
150 * mips-opc.c (IL3A): Delete.
151 * mips-opc.c (LEXT): New macro.
152 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
155 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
157 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
159 (parse_mips_ase_option): Handle -M loongson-cam option.
160 (print_mips_disassembler_options): Document -M loongson-cam.
161 * mips-opc.c (LCAM): New macro.
162 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
165 2018-08-21 Alan Modra <amodra@gmail.com>
167 * ppc-dis.c (operand_value_powerpc): Init "invalid".
168 (skip_optional_operands): Count optional operands, and update
169 ppc_optional_operand_value call.
170 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
171 (extract_vlensi): Likewise.
172 (extract_fxm): Return default value for missing optional operand.
173 (extract_ls, extract_raq, extract_tbr): Likewise.
174 (insert_sxl, extract_sxl): New functions.
175 (insert_esync, extract_esync): Remove Power9 handling and simplify.
176 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
177 flag and extra entry.
178 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
181 2018-08-20 Alan Modra <amodra@gmail.com>
183 * sh-opc.h (MASK): Simplify.
185 2018-08-18 John Darrington <john@darrington.wattle.id.au>
187 * s12z-dis.c (bm_decode): Deal with cases where the mode is
188 BM_RESERVED0 or BM_RESERVED1
189 (bm_rel_decode, bm_n_bytes): Ditto.
191 2018-08-18 John Darrington <john@darrington.wattle.id.au>
195 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
197 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
198 address with the addr32 prefix and without base nor index
201 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
203 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
204 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
205 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
206 (cpu_flags): Add CpuCMOV and CpuFXSR.
207 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
208 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
209 * i386-init.h: Regenerated.
210 * i386-tbl.h: Likewise.
212 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
214 * arc-regs.h: Update auxiliary registers.
216 2018-08-06 Jan Beulich <jbeulich@suse.com>
218 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
219 (RegIP, RegIZ): Define.
220 * i386-reg.tbl: Adjust comments.
221 (rip): Use Qword instead of BaseIndex. Use RegIP.
222 (eip): Use Dword instead of BaseIndex. Use RegIP.
223 (riz): Add Qword. Use RegIZ.
224 (eiz): Add Dword. Use RegIZ.
225 * i386-tbl.h: Re-generate.
227 2018-08-03 Jan Beulich <jbeulich@suse.com>
229 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
230 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
231 vpmovzxdq, vpmovzxwd): Remove NoRex64.
232 * i386-tbl.h: Re-generate.
234 2018-08-03 Jan Beulich <jbeulich@suse.com>
236 * i386-gen.c (operand_types): Remove Mem field.
237 * i386-opc.h (union i386_operand_type): Remove mem field.
238 * i386-init.h, i386-tbl.h: Re-generate.
240 2018-08-01 Alan Modra <amodra@gmail.com>
242 * po/POTFILES.in: Regenerate.
244 2018-07-31 Nick Clifton <nickc@redhat.com>
246 * po/sv.po: Updated Swedish translation.
248 2018-07-31 Jan Beulich <jbeulich@suse.com>
250 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
251 * i386-init.h, i386-tbl.h: Re-generate.
253 2018-07-31 Jan Beulich <jbeulich@suse.com>
255 * i386-opc.h (ZEROING_MASKING) Rename to ...
256 (DYNAMIC_MASKING): ... this. Adjust comment.
257 * i386-opc.tbl (MaskingMorZ): Define.
258 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
259 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
260 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
261 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
262 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
263 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
264 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
265 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
266 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
268 2018-07-31 Jan Beulich <jbeulich@suse.com>
270 * i386-opc.tbl: Use element rather than vector size for AVX512*
271 scatter/gather insns.
272 * i386-tbl.h: Re-generate.
274 2018-07-31 Jan Beulich <jbeulich@suse.com>
276 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
277 (cpu_flags): Drop CpuVREX.
278 * i386-opc.h (CpuVREX): Delete.
279 (union i386_cpu_flags): Remove cpuvrex.
280 * i386-init.h, i386-tbl.h: Re-generate.
282 2018-07-30 Jim Wilson <jimw@sifive.com>
284 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
286 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
288 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
290 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
291 * Makefile.in: Regenerated.
292 * configure.ac: Add C-SKY.
293 * configure: Regenerated.
294 * csky-dis.c: New file.
295 * csky-opc.h: New file.
296 * disassemble.c (ARCH_csky): Define.
297 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
298 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
300 2018-07-27 Alan Modra <amodra@gmail.com>
302 * ppc-opc.c (insert_sprbat): Correct function parameter and
304 (extract_sprbat): Likewise, variable too.
306 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
307 Alan Modra <amodra@gmail.com>
309 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
310 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
311 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
312 support disjointed BAT.
313 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
314 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
315 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
317 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
318 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
320 * i386-gen.c (adjust_broadcast_modifier): New function.
321 (process_i386_opcode_modifier): Add an argument for operands.
322 Adjust the Broadcast value based on operands.
323 (output_i386_opcode): Pass operand_types to
324 process_i386_opcode_modifier.
325 (process_i386_opcodes): Pass NULL as operands to
326 process_i386_opcode_modifier.
327 * i386-opc.h (BYTE_BROADCAST): New.
328 (WORD_BROADCAST): Likewise.
329 (DWORD_BROADCAST): Likewise.
330 (QWORD_BROADCAST): Likewise.
331 (i386_opcode_modifier): Expand broadcast to 3 bits.
332 * i386-tbl.h: Regenerated.
334 2018-07-24 Alan Modra <amodra@gmail.com>
337 * or1k-desc.h: Regenerate.
339 2018-07-24 Jan Beulich <jbeulich@suse.com>
341 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
342 vcvtusi2ss, and vcvtusi2sd.
343 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
344 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
345 * i386-tbl.h: Re-generate.
347 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
349 * arc-opc.c (extract_w6): Fix extending the sign.
351 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
353 * arc-tbl.h (vewt): Allow it for ARC EM family.
355 2018-07-23 Alan Modra <amodra@gmail.com>
358 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
359 opcode variants for mtspr/mfspr encodings.
361 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
362 Maciej W. Rozycki <macro@mips.com>
364 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
365 loongson3a descriptors.
366 (parse_mips_ase_option): Handle -M loongson-mmi option.
367 (print_mips_disassembler_options): Document -M loongson-mmi.
368 * mips-opc.c (LMMI): New macro.
369 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
372 2018-07-19 Jan Beulich <jbeulich@suse.com>
374 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
375 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
376 IgnoreSize and [XYZ]MMword where applicable.
377 * i386-tbl.h: Re-generate.
379 2018-07-19 Jan Beulich <jbeulich@suse.com>
381 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
382 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
383 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
384 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
385 * i386-tbl.h: Re-generate.
387 2018-07-19 Jan Beulich <jbeulich@suse.com>
389 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
390 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
391 VPCLMULQDQ templates into their respective AVX512VL counterparts
392 where possible, using Disp8ShiftVL and CheckRegSize instead of
393 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
394 * i386-tbl.h: Re-generate.
396 2018-07-19 Jan Beulich <jbeulich@suse.com>
398 * i386-opc.tbl: Fold AVX512DQ templates into their respective
399 AVX512VL counterparts where possible, using Disp8ShiftVL and
400 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
401 IgnoreSize) as appropriate.
402 * i386-tbl.h: Re-generate.
404 2018-07-19 Jan Beulich <jbeulich@suse.com>
406 * i386-opc.tbl: Fold AVX512BW templates into their respective
407 AVX512VL counterparts where possible, using Disp8ShiftVL and
408 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
409 IgnoreSize) as appropriate.
410 * i386-tbl.h: Re-generate.
412 2018-07-19 Jan Beulich <jbeulich@suse.com>
414 * i386-opc.tbl: Fold AVX512CD templates into their respective
415 AVX512VL counterparts where possible, using Disp8ShiftVL and
416 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
417 IgnoreSize) as appropriate.
418 * i386-tbl.h: Re-generate.
420 2018-07-19 Jan Beulich <jbeulich@suse.com>
422 * i386-opc.h (DISP8_SHIFT_VL): New.
423 * i386-opc.tbl (Disp8ShiftVL): Define.
424 (various): Fold AVX512VL templates into their respective
425 AVX512F counterparts where possible, using Disp8ShiftVL and
426 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
427 IgnoreSize) as appropriate.
428 * i386-tbl.h: Re-generate.
430 2018-07-19 Jan Beulich <jbeulich@suse.com>
432 * Makefile.am: Change dependencies and rule for
433 $(srcdir)/i386-init.h.
434 * Makefile.in: Re-generate.
435 * i386-gen.c (process_i386_opcodes): New local variable
436 "marker". Drop opening of input file. Recognize marker and line
438 * i386-opc.tbl (OPCODE_I386_H): Define.
439 (i386-opc.h): Include it.
442 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
445 * i386-opc.h (Byte): Update comments.
454 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
456 * i386-tbl.h: Regenerated.
458 2018-07-12 Sudakshina Das <sudi.das@arm.com>
460 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
461 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
462 * aarch64-asm-2.c: Regenerate.
463 * aarch64-dis-2.c: Regenerate.
464 * aarch64-opc-2.c: Regenerate.
466 2018-07-12 Tamar Christina <tamar.christina@arm.com>
469 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
470 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
471 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
472 sqdmulh, sqrdmulh): Use Em16.
474 2018-07-11 Sudakshina Das <sudi.das@arm.com>
476 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
477 csdb together with them.
478 (thumb32_opcodes): Likewise.
480 2018-07-11 Jan Beulich <jbeulich@suse.com>
482 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
483 requiring 32-bit registers as operands 2 and 3. Improve
485 (mwait, mwaitx): Fold templates. Improve comments.
486 OPERAND_TYPE_INOUTPORTREG.
487 * i386-tbl.h: Re-generate.
489 2018-07-11 Jan Beulich <jbeulich@suse.com>
491 * i386-gen.c (operand_type_init): Remove
492 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
493 OPERAND_TYPE_INOUTPORTREG.
494 * i386-init.h: Re-generate.
496 2018-07-11 Jan Beulich <jbeulich@suse.com>
498 * i386-opc.tbl (wrssd, wrussd): Add Dword.
499 (wrssq, wrussq): Add Qword.
500 * i386-tbl.h: Re-generate.
502 2018-07-11 Jan Beulich <jbeulich@suse.com>
504 * i386-opc.h: Rename OTMax to OTNum.
505 (OTNumOfUints): Adjust calculation.
506 (OTUnused): Directly alias to OTNum.
508 2018-07-09 Maciej W. Rozycki <macro@mips.com>
510 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
512 (lea_reg_xys): Likewise.
513 (print_insn_loop_primitive): Rename `reg' local variable to
516 2018-07-06 Tamar Christina <tamar.christina@arm.com>
519 * aarch64-tbl.h (ldarh): Fix disassembly mask.
521 2018-07-06 Tamar Christina <tamar.christina@arm.com>
524 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
525 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
527 2018-07-02 Maciej W. Rozycki <macro@mips.com>
530 * mips-dis.c (mips_option_arg_t): New enumeration.
531 (mips_options): New variable.
532 (disassembler_options_mips): New function.
533 (print_mips_disassembler_options): Reimplement in terms of
534 `disassembler_options_mips'.
535 * arm-dis.c (disassembler_options_arm): Adapt to using the
536 `disasm_options_and_args_t' structure.
537 * ppc-dis.c (disassembler_options_powerpc): Likewise.
538 * s390-dis.c (disassembler_options_s390): Likewise.
540 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
542 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
544 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
545 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
546 * testsuite/ld-arm/tls-longplt.d: Likewise.
548 2018-06-29 Tamar Christina <tamar.christina@arm.com>
551 * aarch64-asm-2.c: Regenerate.
552 * aarch64-dis-2.c: Likewise.
553 * aarch64-opc-2.c: Likewise.
554 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
555 * aarch64-opc.c (operand_general_constraint_met_p,
556 aarch64_print_operand): Likewise.
557 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
558 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
560 (AARCH64_OPERANDS): Add Em2.
562 2018-06-26 Nick Clifton <nickc@redhat.com>
564 * po/uk.po: Updated Ukranian translation.
565 * po/de.po: Updated German translation.
566 * po/pt_BR.po: Updated Brazilian Portuguese translation.
568 2018-06-26 Nick Clifton <nickc@redhat.com>
570 * nfp-dis.c: Fix spelling mistake.
572 2018-06-24 Nick Clifton <nickc@redhat.com>
574 * configure: Regenerate.
575 * po/opcodes.pot: Regenerate.
577 2018-06-24 Nick Clifton <nickc@redhat.com>
581 2018-06-19 Tamar Christina <tamar.christina@arm.com>
583 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
584 * aarch64-asm-2.c: Regenerate.
585 * aarch64-dis-2.c: Likewise.
587 2018-06-21 Maciej W. Rozycki <macro@mips.com>
589 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
590 `-M ginv' option description.
592 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
595 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
598 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
600 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
601 * configure.ac: Remove AC_PREREQ.
602 * Makefile.in: Re-generate.
603 * aclocal.m4: Re-generate.
604 * configure: Re-generate.
606 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
608 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
609 mips64r6 descriptors.
610 (parse_mips_ase_option): Handle -Mginv option.
611 (print_mips_disassembler_options): Document -Mginv.
612 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
614 (mips_opcodes): Define ginvi and ginvt.
616 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
617 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
619 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
620 * mips-opc.c (CRC, CRC64): New macros.
621 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
622 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
625 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
628 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
629 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
631 2018-06-06 Alan Modra <amodra@gmail.com>
633 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
634 setjmp. Move init for some other vars later too.
636 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
638 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
639 (dis_private): Add new fields for property section tracking.
640 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
641 (xtensa_instruction_fits): New functions.
642 (fetch_data): Bump minimal fetch size to 4.
643 (print_insn_xtensa): Make struct dis_private static.
644 Load and prepare property table on section change.
645 Don't disassemble literals. Don't disassemble instructions that
646 cross property table boundaries.
648 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
650 * configure: Regenerated.
652 2018-06-01 Jan Beulich <jbeulich@suse.com>
654 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
655 * i386-tbl.h: Re-generate.
657 2018-06-01 Jan Beulich <jbeulich@suse.com>
659 * i386-opc.tbl (sldt, str): Add NoRex64.
660 * i386-tbl.h: Re-generate.
662 2018-06-01 Jan Beulich <jbeulich@suse.com>
664 * i386-opc.tbl (invpcid): Add Oword.
665 * i386-tbl.h: Re-generate.
667 2018-06-01 Alan Modra <amodra@gmail.com>
669 * sysdep.h (_bfd_error_handler): Don't declare.
670 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
671 * rl78-decode.opc: Likewise.
672 * msp430-decode.c: Regenerate.
673 * rl78-decode.c: Regenerate.
675 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
677 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
678 * i386-init.h : Regenerated.
680 2018-05-25 Alan Modra <amodra@gmail.com>
682 * Makefile.in: Regenerate.
683 * po/POTFILES.in: Regenerate.
685 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
687 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
688 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
689 (insert_bab, extract_bab, insert_btab, extract_btab,
690 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
691 (BAT, BBA VBA RBS XB6S): Delete macros.
692 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
693 (BB, BD, RBX, XC6): Update for new macros.
694 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
695 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
696 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
697 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
699 2018-05-18 John Darrington <john@darrington.wattle.id.au>
701 * Makefile.am: Add support for s12z architecture.
702 * configure.ac: Likewise.
703 * disassemble.c: Likewise.
704 * disassemble.h: Likewise.
705 * Makefile.in: Regenerate.
706 * configure: Regenerate.
707 * s12z-dis.c: New file.
710 2018-05-18 Alan Modra <amodra@gmail.com>
712 * nfp-dis.c: Don't #include libbfd.h.
713 (init_nfp3200_priv): Use bfd_get_section_contents.
714 (nit_nfp6000_mecsr_sec): Likewise.
716 2018-05-17 Nick Clifton <nickc@redhat.com>
718 * po/zh_CN.po: Updated simplified Chinese translation.
720 2018-05-16 Tamar Christina <tamar.christina@arm.com>
723 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
724 * aarch64-dis-2.c: Regenerate.
726 2018-05-15 Tamar Christina <tamar.christina@arm.com>
729 * aarch64-asm.c (opintl.h): Include.
730 (aarch64_ins_sysreg): Enforce read/write constraints.
731 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
732 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
733 (F_REG_READ, F_REG_WRITE): New.
734 * aarch64-opc.c (aarch64_print_operand): Generate notes for
736 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
737 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
738 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
739 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
740 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
741 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
742 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
743 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
744 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
745 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
746 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
747 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
748 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
749 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
750 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
751 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
752 msr (F_SYS_WRITE), mrs (F_SYS_READ).
754 2018-05-15 Tamar Christina <tamar.christina@arm.com>
757 * aarch64-dis.c (no_notes: New.
758 (parse_aarch64_dis_option): Support notes.
759 (aarch64_decode_insn, print_operands): Likewise.
760 (print_aarch64_disassembler_options): Document notes.
761 * aarch64-opc.c (aarch64_print_operand): Support notes.
763 2018-05-15 Tamar Christina <tamar.christina@arm.com>
766 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
767 and take error struct.
768 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
769 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
770 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
771 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
772 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
773 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
774 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
775 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
776 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
777 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
778 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
779 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
780 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
781 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
782 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
783 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
784 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
785 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
786 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
787 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
788 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
789 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
790 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
791 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
792 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
793 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
794 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
795 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
796 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
797 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
798 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
799 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
800 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
801 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
802 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
803 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
804 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
805 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
806 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
807 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
808 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
809 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
810 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
811 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
812 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
813 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
814 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
815 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
816 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
817 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
818 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
819 (determine_disassembling_preference, aarch64_decode_insn,
820 print_insn_aarch64_word, print_insn_data): Take errors struct.
821 (print_insn_aarch64): Use errors.
822 * aarch64-asm-2.c: Regenerate.
823 * aarch64-dis-2.c: Regenerate.
824 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
825 boolean in aarch64_insert_operan.
826 (print_operand_extractor): Likewise.
827 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
829 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
831 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
833 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
835 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
837 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
839 * cr16-opc.c (cr16_instruction): Comment typo fix.
840 * hppa-dis.c (print_insn_hppa): Likewise.
842 2018-05-08 Jim Wilson <jimw@sifive.com>
844 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
845 (match_c_slli64, match_srxi_as_c_srxi): New.
846 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
847 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
848 <c.slli, c.srli, c.srai>: Use match_s_slli.
849 <c.slli64, c.srli64, c.srai64>: New.
851 2018-05-08 Alan Modra <amodra@gmail.com>
853 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
854 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
855 partition opcode space for index lookup.
857 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
859 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
860 <insn_length>: ...with this. Update usage.
861 Remove duplicate call to *info->memory_error_func.
863 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
864 H.J. Lu <hongjiu.lu@intel.com>
866 * i386-dis.c (Gva): New.
867 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
868 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
869 (prefix_table): New instructions (see prefix above).
870 (mod_table): New instructions (see prefix above).
871 (OP_G): Handle va_mode.
872 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
874 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
875 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
876 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
877 * i386-opc.tbl: Add movidir{i,64b}.
878 * i386-init.h: Regenerated.
879 * i386-tbl.h: Likewise.
881 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
883 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
885 * i386-opc.h (AddrPrefixOp0): Renamed to ...
886 (AddrPrefixOpReg): This.
887 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
888 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
890 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
892 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
893 (vle_num_opcodes): Likewise.
894 (spe2_num_opcodes): Likewise.
895 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
897 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
898 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
901 2018-05-01 Tamar Christina <tamar.christina@arm.com>
903 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
905 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
907 Makefile.am: Added nfp-dis.c.
908 configure.ac: Added bfd_nfp_arch.
909 disassemble.h: Added print_insn_nfp prototype.
910 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
911 nfp-dis.c: New, for NFP support.
912 po/POTFILES.in: Added nfp-dis.c to the list.
913 Makefile.in: Regenerate.
914 configure: Regenerate.
916 2018-04-26 Jan Beulich <jbeulich@suse.com>
918 * i386-opc.tbl: Fold various non-memory operand AVX512VL
919 templates into their base ones.
920 * i386-tlb.h: Re-generate.
922 2018-04-26 Jan Beulich <jbeulich@suse.com>
924 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
925 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
926 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
927 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
928 * i386-init.h: Re-generate.
930 2018-04-26 Jan Beulich <jbeulich@suse.com>
932 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
933 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
934 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
935 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
937 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
939 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
941 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
942 cpuregzmm, and cpuregmask.
943 * i386-init.h: Re-generate.
944 * i386-tbl.h: Re-generate.
946 2018-04-26 Jan Beulich <jbeulich@suse.com>
948 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
949 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
950 * i386-init.h: Re-generate.
952 2018-04-26 Jan Beulich <jbeulich@suse.com>
954 * i386-gen.c (VexImmExt): Delete.
955 * i386-opc.h (VexImmExt, veximmext): Delete.
956 * i386-opc.tbl: Drop all VexImmExt uses.
957 * i386-tlb.h: Re-generate.
959 2018-04-25 Jan Beulich <jbeulich@suse.com>
961 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
963 * i386-tlb.h: Re-generate.
965 2018-04-25 Tamar Christina <tamar.christina@arm.com>
967 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
969 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
971 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
973 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
974 (cpu_flags): Add CpuCLDEMOTE.
975 * i386-init.h: Regenerate.
976 * i386-opc.h (enum): Add CpuCLDEMOTE,
977 (i386_cpu_flags): Add cpucldemote.
978 * i386-opc.tbl: Add cldemote.
979 * i386-tbl.h: Regenerate.
981 2018-04-16 Alan Modra <amodra@gmail.com>
983 * Makefile.am: Remove sh5 and sh64 support.
984 * configure.ac: Likewise.
985 * disassemble.c: Likewise.
986 * disassemble.h: Likewise.
987 * sh-dis.c: Likewise.
988 * sh64-dis.c: Delete.
989 * sh64-opc.c: Delete.
990 * sh64-opc.h: Delete.
991 * Makefile.in: Regenerate.
992 * configure: Regenerate.
993 * po/POTFILES.in: Regenerate.
995 2018-04-16 Alan Modra <amodra@gmail.com>
997 * Makefile.am: Remove w65 support.
998 * configure.ac: Likewise.
999 * disassemble.c: Likewise.
1000 * disassemble.h: Likewise.
1001 * w65-dis.c: Delete.
1002 * w65-opc.h: Delete.
1003 * Makefile.in: Regenerate.
1004 * configure: Regenerate.
1005 * po/POTFILES.in: Regenerate.
1007 2018-04-16 Alan Modra <amodra@gmail.com>
1009 * configure.ac: Remove we32k support.
1010 * configure: Regenerate.
1012 2018-04-16 Alan Modra <amodra@gmail.com>
1014 * Makefile.am: Remove m88k support.
1015 * configure.ac: Likewise.
1016 * disassemble.c: Likewise.
1017 * disassemble.h: Likewise.
1018 * m88k-dis.c: Delete.
1019 * Makefile.in: Regenerate.
1020 * configure: Regenerate.
1021 * po/POTFILES.in: Regenerate.
1023 2018-04-16 Alan Modra <amodra@gmail.com>
1025 * Makefile.am: Remove i370 support.
1026 * configure.ac: Likewise.
1027 * disassemble.c: Likewise.
1028 * disassemble.h: Likewise.
1029 * i370-dis.c: Delete.
1030 * i370-opc.c: Delete.
1031 * Makefile.in: Regenerate.
1032 * configure: Regenerate.
1033 * po/POTFILES.in: Regenerate.
1035 2018-04-16 Alan Modra <amodra@gmail.com>
1037 * Makefile.am: Remove h8500 support.
1038 * configure.ac: Likewise.
1039 * disassemble.c: Likewise.
1040 * disassemble.h: Likewise.
1041 * h8500-dis.c: Delete.
1042 * h8500-opc.h: Delete.
1043 * Makefile.in: Regenerate.
1044 * configure: Regenerate.
1045 * po/POTFILES.in: Regenerate.
1047 2018-04-16 Alan Modra <amodra@gmail.com>
1049 * configure.ac: Remove tahoe support.
1050 * configure: Regenerate.
1052 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1054 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1056 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1058 * i386-tbl.h: Regenerated.
1060 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1062 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1063 PREFIX_MOD_1_0FAE_REG_6.
1065 (OP_E_register): Use va_mode.
1066 * i386-dis-evex.h (prefix_table):
1067 New instructions (see prefixes above).
1068 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1069 (cpu_flags): Likewise.
1070 * i386-opc.h (enum): Likewise.
1071 (i386_cpu_flags): Likewise.
1072 * i386-opc.tbl: Add umonitor, umwait, tpause.
1073 * i386-init.h: Regenerate.
1074 * i386-tbl.h: Likewise.
1076 2018-04-11 Alan Modra <amodra@gmail.com>
1078 * opcodes/i860-dis.c: Delete.
1079 * opcodes/i960-dis.c: Delete.
1080 * Makefile.am: Remove i860 and i960 support.
1081 * configure.ac: Likewise.
1082 * disassemble.c: Likewise.
1083 * disassemble.h: Likewise.
1084 * Makefile.in: Regenerate.
1085 * configure: Regenerate.
1086 * po/POTFILES.in: Regenerate.
1088 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1091 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1093 (print_insn): Clear vex instead of vex.evex.
1095 2018-04-04 Nick Clifton <nickc@redhat.com>
1097 * po/es.po: Updated Spanish translation.
1099 2018-03-28 Jan Beulich <jbeulich@suse.com>
1101 * i386-gen.c (opcode_modifiers): Delete VecESize.
1102 * i386-opc.h (VecESize): Delete.
1103 (struct i386_opcode_modifier): Delete vecesize.
1104 * i386-opc.tbl: Drop VecESize.
1105 * i386-tlb.h: Re-generate.
1107 2018-03-28 Jan Beulich <jbeulich@suse.com>
1109 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1110 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1111 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1112 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1113 * i386-tlb.h: Re-generate.
1115 2018-03-28 Jan Beulich <jbeulich@suse.com>
1117 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1119 * i386-tlb.h: Re-generate.
1121 2018-03-28 Jan Beulich <jbeulich@suse.com>
1123 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1124 (vex_len_table): Drop Y for vcvt*2si.
1125 (putop): Replace plain 'Y' handling by abort().
1127 2018-03-28 Nick Clifton <nickc@redhat.com>
1130 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1131 instructions with only a base address register.
1132 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1133 handle AARHC64_OPND_SVE_ADDR_R.
1134 (aarch64_print_operand): Likewise.
1135 * aarch64-asm-2.c: Regenerate.
1136 * aarch64_dis-2.c: Regenerate.
1137 * aarch64-opc-2.c: Regenerate.
1139 2018-03-22 Jan Beulich <jbeulich@suse.com>
1141 * i386-opc.tbl: Drop VecESize from register only insn forms and
1142 memory forms not allowing broadcast.
1143 * i386-tlb.h: Re-generate.
1145 2018-03-22 Jan Beulich <jbeulich@suse.com>
1147 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1148 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1149 sha256*): Drop Disp<N>.
1151 2018-03-22 Jan Beulich <jbeulich@suse.com>
1153 * i386-dis.c (EbndS, bnd_swap_mode): New.
1154 (prefix_table): Use EbndS.
1155 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1156 * i386-opc.tbl (bndmov): Move misplaced Load.
1157 * i386-tlb.h: Re-generate.
1159 2018-03-22 Jan Beulich <jbeulich@suse.com>
1161 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1162 templates allowing memory operands and folded ones for register
1164 * i386-tlb.h: Re-generate.
1166 2018-03-22 Jan Beulich <jbeulich@suse.com>
1168 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1169 256-bit templates. Drop redundant leftover Disp<N>.
1170 * i386-tlb.h: Re-generate.
1172 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1174 * riscv-opc.c (riscv_insn_types): New.
1176 2018-03-13 Nick Clifton <nickc@redhat.com>
1178 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1180 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1182 * i386-opc.tbl: Add Optimize to clr.
1183 * i386-tbl.h: Regenerated.
1185 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1187 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1188 * i386-opc.h (OldGcc): Removed.
1189 (i386_opcode_modifier): Remove oldgcc.
1190 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1191 instructions for old (<= 2.8.1) versions of gcc.
1192 * i386-tbl.h: Regenerated.
1194 2018-03-08 Jan Beulich <jbeulich@suse.com>
1196 * i386-opc.h (EVEXDYN): New.
1197 * i386-opc.tbl: Fold various AVX512VL templates.
1198 * i386-tlb.h: Re-generate.
1200 2018-03-08 Jan Beulich <jbeulich@suse.com>
1202 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1203 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1204 vpexpandd, vpexpandq): Fold AFX512VF templates.
1205 * i386-tlb.h: Re-generate.
1207 2018-03-08 Jan Beulich <jbeulich@suse.com>
1209 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1210 Fold 128- and 256-bit VEX-encoded templates.
1211 * i386-tlb.h: Re-generate.
1213 2018-03-08 Jan Beulich <jbeulich@suse.com>
1215 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1216 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1217 vpexpandd, vpexpandq): Fold AVX512F templates.
1218 * i386-tlb.h: Re-generate.
1220 2018-03-08 Jan Beulich <jbeulich@suse.com>
1222 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1223 64-bit templates. Drop Disp<N>.
1224 * i386-tlb.h: Re-generate.
1226 2018-03-08 Jan Beulich <jbeulich@suse.com>
1228 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1229 and 256-bit templates.
1230 * i386-tlb.h: Re-generate.
1232 2018-03-08 Jan Beulich <jbeulich@suse.com>
1234 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1235 * i386-tlb.h: Re-generate.
1237 2018-03-08 Jan Beulich <jbeulich@suse.com>
1239 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1241 * i386-tlb.h: Re-generate.
1243 2018-03-08 Jan Beulich <jbeulich@suse.com>
1245 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1246 * i386-tlb.h: Re-generate.
1248 2018-03-08 Jan Beulich <jbeulich@suse.com>
1250 * i386-gen.c (opcode_modifiers): Delete FloatD.
1251 * i386-opc.h (FloatD): Delete.
1252 (struct i386_opcode_modifier): Delete floatd.
1253 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1255 * i386-tlb.h: Re-generate.
1257 2018-03-08 Jan Beulich <jbeulich@suse.com>
1259 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1261 2018-03-08 Jan Beulich <jbeulich@suse.com>
1263 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1264 * i386-tlb.h: Re-generate.
1266 2018-03-08 Jan Beulich <jbeulich@suse.com>
1268 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1270 * i386-tlb.h: Re-generate.
1272 2018-03-07 Alan Modra <amodra@gmail.com>
1274 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1276 * disassemble.h (print_insn_rs6000): Delete.
1277 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1278 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1279 (print_insn_rs6000): Delete.
1281 2018-03-03 Alan Modra <amodra@gmail.com>
1283 * sysdep.h (opcodes_error_handler): Define.
1284 (_bfd_error_handler): Declare.
1285 * Makefile.am: Remove stray #.
1286 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1288 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1289 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1290 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1291 opcodes_error_handler to print errors. Standardize error messages.
1292 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1293 and include opintl.h.
1294 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1295 * i386-gen.c: Standardize error messages.
1296 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1297 * Makefile.in: Regenerate.
1298 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1299 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1300 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1301 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1302 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1303 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1304 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1305 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1306 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1307 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1308 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1309 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1310 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1312 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1314 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1315 vpsub[bwdq] instructions.
1316 * i386-tbl.h: Regenerated.
1318 2018-03-01 Alan Modra <amodra@gmail.com>
1320 * configure.ac (ALL_LINGUAS): Sort.
1321 * configure: Regenerate.
1323 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1325 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1326 macro by assignements.
1328 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1331 * i386-gen.c (opcode_modifiers): Add Optimize.
1332 * i386-opc.h (Optimize): New enum.
1333 (i386_opcode_modifier): Add optimize.
1334 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1335 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1336 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1337 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1338 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1340 * i386-tbl.h: Regenerated.
1342 2018-02-26 Alan Modra <amodra@gmail.com>
1344 * crx-dis.c (getregliststring): Allocate a large enough buffer
1345 to silence false positive gcc8 warning.
1347 2018-02-22 Shea Levy <shea@shealevy.com>
1349 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1351 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1353 * i386-opc.tbl: Add {rex},
1354 * i386-tbl.h: Regenerated.
1356 2018-02-20 Maciej W. Rozycki <macro@mips.com>
1358 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1359 (mips16_opcodes): Replace `M' with `m' for "restore".
1361 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1363 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1365 2018-02-13 Maciej W. Rozycki <macro@mips.com>
1367 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1368 variable to `function_index'.
1370 2018-02-13 Nick Clifton <nickc@redhat.com>
1373 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1374 about truncation of printing.
1376 2018-02-12 Henry Wong <henry@stuffedcow.net>
1378 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1380 2018-02-05 Nick Clifton <nickc@redhat.com>
1382 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1384 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1386 * i386-dis.c (enum): Add pconfig.
1387 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1388 (cpu_flags): Add CpuPCONFIG.
1389 * i386-opc.h (enum): Add CpuPCONFIG.
1390 (i386_cpu_flags): Add cpupconfig.
1391 * i386-opc.tbl: Add PCONFIG instruction.
1392 * i386-init.h: Regenerate.
1393 * i386-tbl.h: Likewise.
1395 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1397 * i386-dis.c (enum): Add PREFIX_0F09.
1398 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1399 (cpu_flags): Add CpuWBNOINVD.
1400 * i386-opc.h (enum): Add CpuWBNOINVD.
1401 (i386_cpu_flags): Add cpuwbnoinvd.
1402 * i386-opc.tbl: Add WBNOINVD instruction.
1403 * i386-init.h: Regenerate.
1404 * i386-tbl.h: Likewise.
1406 2018-01-17 Jim Wilson <jimw@sifive.com>
1408 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1410 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1412 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1413 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1414 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1415 (cpu_flags): Add CpuIBT, CpuSHSTK.
1416 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1417 (i386_cpu_flags): Add cpuibt, cpushstk.
1418 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1419 * i386-init.h: Regenerate.
1420 * i386-tbl.h: Likewise.
1422 2018-01-16 Nick Clifton <nickc@redhat.com>
1424 * po/pt_BR.po: Updated Brazilian Portugese translation.
1425 * po/de.po: Updated German translation.
1427 2018-01-15 Jim Wilson <jimw@sifive.com>
1429 * riscv-opc.c (match_c_nop): New.
1430 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1432 2018-01-15 Nick Clifton <nickc@redhat.com>
1434 * po/uk.po: Updated Ukranian translation.
1436 2018-01-13 Nick Clifton <nickc@redhat.com>
1438 * po/opcodes.pot: Regenerated.
1440 2018-01-13 Nick Clifton <nickc@redhat.com>
1442 * configure: Regenerate.
1444 2018-01-13 Nick Clifton <nickc@redhat.com>
1446 2.30 branch created.
1448 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1450 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1451 * i386-tbl.h: Regenerate.
1453 2018-01-10 Jan Beulich <jbeulich@suse.com>
1455 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1456 * i386-tbl.h: Re-generate.
1458 2018-01-10 Jan Beulich <jbeulich@suse.com>
1460 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1461 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1462 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1463 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1464 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1465 Disp8MemShift of AVX512VL forms.
1466 * i386-tbl.h: Re-generate.
1468 2018-01-09 Jim Wilson <jimw@sifive.com>
1470 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1471 then the hi_addr value is zero.
1473 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1475 * arm-dis.c (arm_opcodes): Add csdb.
1476 (thumb32_opcodes): Add csdb.
1478 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1480 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1481 * aarch64-asm-2.c: Regenerate.
1482 * aarch64-dis-2.c: Regenerate.
1483 * aarch64-opc-2.c: Regenerate.
1485 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1488 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1489 Remove AVX512 vmovd with 64-bit operands.
1490 * i386-tbl.h: Regenerated.
1492 2018-01-05 Jim Wilson <jimw@sifive.com>
1494 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1497 2018-01-03 Alan Modra <amodra@gmail.com>
1499 Update year range in copyright notice of all files.
1501 2018-01-02 Jan Beulich <jbeulich@suse.com>
1503 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1504 and OPERAND_TYPE_REGZMM entries.
1506 For older changes see ChangeLog-2017
1508 Copyright (C) 2018 Free Software Foundation, Inc.
1510 Copying and distribution of this file, with or without modification,
1511 are permitted in any medium without royalty provided the copyright
1512 notice and this notice are preserved.
1518 version-control: never