1 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
7 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
8 fmulx to the vector indexed element group.
10 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
17 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
18 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
19 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
20 fcvtzu and frsqrte to the scalar two register misc. group.
22 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
24 * aarch64-asm-2.c: Regenerate.
25 * aarch64-dis-2.c: Regenerate.
26 * aarch64-opc-2.c: Regenerate.
27 * aarch64-tbl.h (QL_V2SAMEH): New.
28 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
29 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
30 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
31 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
32 and fsqrt to the vector register misc. group.
34 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Regenerate.
38 * aarch64-opc-2.c: Regenerate.
39 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
40 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
41 to the scalar three same group.
43 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Regenerate.
47 * aarch64-opc-2.c: Regenerate.
48 * aarch64-tbl.h (QL_V3SAMEH): New.
49 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
50 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
51 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
52 fcmgt, facgt and fminp to the vector three same group.
54 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
56 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
59 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
61 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
63 (aarch64_pstatefield_supported_p): Move feature checks for AT
65 (aarch64_sys_ins_reg_supported_p): .. to here.
67 2015-12-12 Alan Modra <amodra@gmail.com>
70 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
71 (powerpc_opcodes): Remove single-operand mfcr.
73 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
75 * aarch64-asm.c (aarch64_ins_hint): New.
76 * aarch64-asm.h (aarch64_ins_hint): Declare.
77 * aarch64-dis.c (aarch64_ext_hint): New.
78 * aarch64-dis.h (aarch64_ext_hint): Declare.
79 * aarch64-opc-2.c: Regenerate.
80 * aarch64-opc.c (aarch64_hint_options): New.
81 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
83 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
85 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
87 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
89 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
90 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
91 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
93 (aarch64_sys_reg_supported_p): Add architecture feature tests for
96 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
98 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
99 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
100 feature test for "s1e1rp" and "s1e1wp".
102 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
104 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
105 (aarch64_sys_ins_reg_supported_p): New.
107 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
109 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
110 with aarch64_sys_ins_reg_has_xt.
111 (aarch64_ext_sysins_op): Likewise.
112 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
114 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
115 (aarch64_sys_regs_dc): Likewise.
116 (aarch64_sys_regs_at): Likewise.
117 (aarch64_sys_regs_tlbi): Likewise.
118 (aarch64_sys_ins_reg_has_xt): New.
120 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
122 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
123 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
124 (aarch64_pstatefields): Add "uao".
125 (aarch64_pstatefield_supported_p): Add checks for "uao".
127 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
129 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
130 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
131 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
132 (aarch64_sys_reg_supported_p): Add architecture feature tests for
135 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
137 * aarch64-asm-2.c: Regenerate.
138 * aarch64-dis-2.c: Regenerate.
139 * aarch64-tbl.h (aarch64_feature_ras): New.
141 (aarch64_opcode_table): Add "esb".
143 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
145 * i386-dis.c (MOD_0F01_REG_5): New.
146 (RM_0F01_REG_5): Likewise.
147 (reg_table): Use MOD_0F01_REG_5.
148 (mod_table): Add MOD_0F01_REG_5.
149 (rm_table): Add RM_0F01_REG_5.
150 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
151 (cpu_flags): Add CpuOSPKE.
152 * i386-opc.h (CpuOSPKE): New.
153 (i386_cpu_flags): Add cpuospke.
154 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
155 * i386-init.h: Regenerated.
156 * i386-tbl.h: Likewise.
158 2015-12-07 DJ Delorie <dj@redhat.com>
160 * rl78-decode.opc: Enable MULU for all ISAs.
161 * rl78-decode.c: Regenerate.
163 2015-12-07 Alan Modra <amodra@gmail.com>
165 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
168 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
170 * arc-dis.c (special_flag_p): Match full mnemonic.
171 * arc-opc.c (print_insn_arc): Check section size to read
172 appropriate number of bytes. Fix printing.
173 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
176 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
178 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
181 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
183 * aarch64-asm-2.c: Regenerate.
184 * aarch64-dis-2.c: Regenerate.
185 * aarch64-opc-2.c: Regenerate.
186 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
187 (QL_INT2FP_H, QL_FP2INT_H): New.
188 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
191 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
192 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
193 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
194 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
195 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
196 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
199 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
201 * aarch64-opc.c (half_conv_t): New.
202 (expand_fp_imm): Replace is_dp flag with the parameter size to
203 specify the number of bytes for the required expansion. Treat
204 a 16-bit expansion like a 32-bit expansion. Add check for an
205 unsupported size request. Update comment.
206 (aarch64_print_operand): Update to support 16-bit floating point
207 values. Update for changes to expand_fp_imm.
209 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
211 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
214 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
216 * aarch64-asm-2.c: Regenerate.
217 * aarch64-dis-2.c: Regenerate.
218 * aarch64-opc-2.c: Regenerate.
219 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
222 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-asm.c (convert_bfc_to_bfm): New.
226 (convert_to_real): Add case for OP_BFC.
227 * aarch64-dis-2.c: Regenerate.
228 * aarch64-dis.c: (convert_bfm_to_bfc): New.
229 (convert_to_alias): Add case for OP_BFC.
230 * aarch64-opc-2.c: Regenerate.
231 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
232 to allow width operand in three-operand instructions.
233 * aarch64-tbl.h (QL_BF1): New.
234 (aarch64_feature_v8_2): New.
236 (aarch64_opcode_table): Add "bfc".
238 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
240 * aarch64-asm-2.c: Regenerate.
241 * aarch64-dis-2.c: Regenerate.
242 * aarch64-dis.c: Weaken assert.
243 * aarch64-gen.c: Include the instruction in the list of its
246 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
248 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
249 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
252 2015-11-23 Tristan Gingold <gingold@adacore.com>
254 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
256 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
258 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
259 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
260 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
261 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
262 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
263 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
264 cnthv_ctl_el2, cnthv_cval_el2.
265 (aarch64_sys_reg_supported_p): Update for the new system
268 2015-11-20 Nick Clifton <nickc@redhat.com>
271 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
273 2015-11-20 Nick Clifton <nickc@redhat.com>
275 * po/zh_CN.po: Updated simplified Chinese translation.
277 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
279 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
280 of MSR PAN immediate operand.
282 2015-11-16 Nick Clifton <nickc@redhat.com>
284 * rx-dis.c (condition_names): Replace always and never with
285 invalid, since the always/never conditions can never be legal.
287 2015-11-13 Tristan Gingold <gingold@adacore.com>
289 * configure: Regenerate.
291 2015-11-11 Alan Modra <amodra@gmail.com>
292 Peter Bergner <bergner@vnet.ibm.com>
294 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
295 Add PPC_OPCODE_VSX3 to the vsx entry.
296 (powerpc_init_dialect): Set default dialect to power9.
297 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
298 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
299 extract_l1 insert_xtq6, extract_xtq6): New static functions.
300 (insert_esync): Test for illegal L operand value.
301 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
302 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
303 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
304 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
305 PPCVSX3): New defines.
306 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
307 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
308 <mcrxr>: Use XBFRARB_MASK.
309 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
310 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
311 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
312 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
313 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
314 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
315 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
316 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
317 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
318 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
319 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
320 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
321 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
322 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
323 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
324 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
325 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
326 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
327 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
328 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
329 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
330 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
331 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
332 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
333 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
334 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
335 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
336 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
337 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
338 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
339 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
340 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
342 2015-11-02 Nick Clifton <nickc@redhat.com>
344 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
346 * rx-decode.c: Regenerate.
348 2015-11-02 Nick Clifton <nickc@redhat.com>
350 * rx-decode.opc (rx_disp): If the displacement is zero, set the
351 type to RX_Operand_Zero_Indirect.
352 * rx-decode.c: Regenerate.
353 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
355 2015-10-28 Yao Qi <yao.qi@linaro.org>
357 * aarch64-dis.c (aarch64_decode_insn): Add one argument
358 noaliases_p. Update comments. Pass noaliases_p rather than
359 no_aliases to aarch64_opcode_decode.
360 (print_insn_aarch64_word): Pass no_aliases to
363 2015-10-27 Vinay <Vinay.G@kpit.com>
366 * rl78-decode.opc (MOV): Added offset to DE register in index
368 * rl78-decode.c: Regenerate.
370 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
373 * rl78-decode.opc: Add 's' print operator to instructions that
374 access system registers.
375 * rl78-decode.c: Regenerate.
376 * rl78-dis.c (print_insn_rl78_common): Decode all system
379 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
382 * rl78-decode.opc: Add 'a' print operator to mov instructions
383 using stack pointer plus index addressing.
384 * rl78-decode.c: Regenerate.
386 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
388 * s390-opc.c: Fix comment.
389 * s390-opc.txt: Change instruction type for troo, trot, trto, and
390 trtt to RRF_U0RER since the second parameter does not need to be a
393 2015-10-08 Nick Clifton <nickc@redhat.com>
395 * arc-dis.c (print_insn_arc): Initiallise insn array.
397 2015-10-07 Yao Qi <yao.qi@linaro.org>
399 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
400 'name' rather than 'template'.
401 * aarch64-opc.c (aarch64_print_operand): Likewise.
403 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
405 * arc-dis.c: Revamped file for ARC support
406 * arc-dis.h: Likewise.
407 * arc-ext.c: Likewise.
408 * arc-ext.h: Likewise.
409 * arc-opc.c: Likewise.
410 * arc-fxi.h: New file.
411 * arc-regs.h: Likewise.
412 * arc-tbl.h: Likewise.
414 2015-10-02 Yao Qi <yao.qi@linaro.org>
416 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
417 argument insn type to aarch64_insn. Rename to ...
418 (aarch64_decode_insn): ... it.
419 (print_insn_aarch64_word): Caller updated.
421 2015-10-02 Yao Qi <yao.qi@linaro.org>
423 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
424 (print_insn_aarch64_word): Caller updated.
426 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
428 * s390-mkopc.c (main): Parse htm and vx flag.
429 * s390-opc.txt: Mark instructions from the hardware transactional
430 memory and vector facilities with the "htm"/"vx" flag.
432 2015-09-28 Nick Clifton <nickc@redhat.com>
434 * po/de.po: Updated German translation.
436 2015-09-28 Tom Rix <tom@bumblecow.com>
438 * ppc-opc.c (PPC500): Mark some opcodes as invalid
440 2015-09-23 Nick Clifton <nickc@redhat.com>
442 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
444 * tic30-dis.c (print_branch): Likewise.
445 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
446 value before left shifting.
447 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
448 * hppa-dis.c (print_insn_hppa): Likewise.
449 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
451 * msp430-dis.c (msp430_singleoperand): Likewise.
452 (msp430_doubleoperand): Likewise.
453 (print_insn_msp430): Likewise.
454 * nds32-asm.c (parse_operand): Likewise.
455 * sh-opc.h (MASK): Likewise.
456 * v850-dis.c (get_operand_value): Likewise.
458 2015-09-22 Nick Clifton <nickc@redhat.com>
460 * rx-decode.opc (bwl): Use RX_Bad_Size.
462 (ubwl): Likewise. Rename to ubw.
463 (uBWL): Rename to uBW.
464 Replace all references to uBWL with uBW.
465 * rx-decode.c: Regenerate.
466 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
467 (opsize_names): Likewise.
468 (print_insn_rx): Detect and report RX_Bad_Size.
470 2015-09-22 Anton Blanchard <anton@samba.org>
472 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
474 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
476 * sparc-dis.c (print_insn_sparc): Handle the privileged register
479 2015-08-24 Jan Stancek <jstancek@redhat.com>
481 * i386-dis.c (print_insn): Fix decoding of three byte operands.
483 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
486 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
487 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
488 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
489 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
490 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
491 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
492 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
493 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
494 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
495 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
496 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
497 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
498 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
499 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
500 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
501 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
502 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
503 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
504 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
505 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
506 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
507 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
508 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
509 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
510 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
511 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
512 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
513 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
514 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
515 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
516 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
517 (vex_w_table): Replace terminals with MOD_TABLE entries for
518 most of mask instructions.
520 2015-08-17 Alan Modra <amodra@gmail.com>
522 * cgen.sh: Trim trailing space from cgen output.
523 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
524 (print_dis_table): Likewise.
525 * opc2c.c (dump_lines): Likewise.
526 (orig_filename): Warning fix.
527 * ia64-asmtab.c: Regenerate.
529 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
531 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
532 and higher with ARM instruction set will now mark the 26-bit
533 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
534 (arm_opcodes): Fix for unpredictable nop being recognized as a
537 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
539 * micromips-opc.c (micromips_opcodes): Re-order table so that move
540 based on 'or' is first.
541 * mips-opc.c (mips_builtin_opcodes): Ditto.
543 2015-08-11 Nick Clifton <nickc@redhat.com>
546 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
549 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
551 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
553 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
555 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
556 * i386-init.h: Regenerated.
558 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
561 * i386-dis.c (MOD_0FC3): New.
562 (PREFIX_0FC3): Renamed to ...
563 (PREFIX_MOD_0_0FC3): This.
564 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
565 (prefix_table): Replace Ma with Ev on movntiS.
566 (mod_table): Add MOD_0FC3.
568 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
570 * configure: Regenerated.
572 2015-07-23 Alan Modra <amodra@gmail.com>
575 * i386-dis.c (get64): Avoid signed integer overflow.
577 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
580 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
581 "EXEvexHalfBcstXmmq" for the second operand.
582 (EVEX_W_0F79_P_2): Likewise.
583 (EVEX_W_0F7A_P_2): Likewise.
584 (EVEX_W_0F7B_P_2): Likewise.
586 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
588 * arm-dis.c (print_insn_coprocessor): Added support for quarter
589 float bitfield format.
590 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
591 quarter float bitfield format.
593 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
595 * configure: Regenerated.
597 2015-07-03 Alan Modra <amodra@gmail.com>
599 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
600 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
601 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
603 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
604 Cesar Philippidis <cesar@codesourcery.com>
606 * nios2-dis.c (nios2_extract_opcode): New.
607 (nios2_disassembler_state): New.
608 (nios2_find_opcode_hash): Use mach parameter to select correct
610 (nios2_print_insn_arg): Extend to support new R2 argument letters
612 (print_insn_nios2): Check for 16-bit instruction at end of memory.
613 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
614 (NIOS2_NUM_OPCODES): Rename to...
615 (NIOS2_NUM_R1_OPCODES): This.
616 (nios2_r2_opcodes): New.
617 (NIOS2_NUM_R2_OPCODES): New.
618 (nios2_num_r2_opcodes): New.
619 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
620 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
621 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
622 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
623 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
625 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
627 * i386-dis.c (OP_Mwaitx): New.
628 (rm_table): Add monitorx/mwaitx.
629 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
630 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
631 (operand_type_init): Add CpuMWAITX.
632 * i386-opc.h (CpuMWAITX): New.
633 (i386_cpu_flags): Add cpumwaitx.
634 * i386-opc.tbl: Add monitorx and mwaitx.
635 * i386-init.h: Regenerated.
636 * i386-tbl.h: Likewise.
638 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
640 * ppc-opc.c (insert_ls): Test for invalid LS operands.
641 (insert_esync): New function.
642 (LS, WC): Use insert_ls.
643 (ESYNC): Use insert_esync.
645 2015-06-22 Nick Clifton <nickc@redhat.com>
647 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
648 requested region lies beyond it.
649 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
650 looking for 32-bit insns.
651 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
653 * sh-dis.c (print_insn_sh): Likewise.
654 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
655 blocks of instructions.
656 * vax-dis.c (print_insn_vax): Check that the requested address
657 does not clash with the stop_vma.
659 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
661 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
662 * ppc-opc.c (FXM4): Add non-zero optional value.
665 (insert_fxm): Handle new default operand value.
666 (extract_fxm): Likewise.
667 (insert_tbr): Likewise.
668 (extract_tbr): Likewise.
670 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
672 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
674 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
676 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
678 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
680 * ppc-opc.c: Add comment accidentally removed by old commit.
683 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
685 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
687 2015-06-04 Nick Clifton <nickc@redhat.com>
690 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
692 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
694 * arm-dis.c (arm_opcodes): Add "setpan".
695 (thumb_opcodes): Add "setpan".
697 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
699 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
702 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
704 * aarch64-tbl.h (aarch64_feature_rdma): New.
706 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
707 * aarch64-asm-2.c: Regenerate.
708 * aarch64-dis-2.c: Regenerate.
709 * aarch64-opc-2.c: Regenerate.
711 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
713 * aarch64-tbl.h (aarch64_feature_lor): New.
715 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
717 * aarch64-asm-2.c: Regenerate.
718 * aarch64-dis-2.c: Regenerate.
719 * aarch64-opc-2.c: Regenerate.
721 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
723 * aarch64-opc.c (F_ARCHEXT): New.
724 (aarch64_sys_regs): Add "pan".
725 (aarch64_sys_reg_supported_p): New.
726 (aarch64_pstatefields): Add "pan".
727 (aarch64_pstatefield_supported_p): New.
729 2015-06-01 Jan Beulich <jbeulich@suse.com>
731 * i386-tbl.h: Regenerate.
733 2015-06-01 Jan Beulich <jbeulich@suse.com>
735 * i386-dis.c (print_insn): Swap rounding mode specifier and
736 general purpose register in Intel mode.
738 2015-06-01 Jan Beulich <jbeulich@suse.com>
740 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
741 * i386-tbl.h: Regenerate.
743 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
745 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
746 * i386-init.h: Regenerated.
748 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
751 * i386-dis.c: Add comments for '@'.
752 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
753 (enum x86_64_isa): New.
755 (print_i386_disassembler_options): Add amd64 and intel64.
756 (print_insn): Handle amd64 and intel64.
758 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
759 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
760 * i386-opc.h (AMD64): New.
761 (CpuIntel64): Likewise.
762 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
763 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
764 Mark direct call/jmp without Disp16|Disp32 as Intel64.
765 * i386-init.h: Regenerated.
766 * i386-tbl.h: Likewise.
768 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
770 * ppc-opc.c (IH) New define.
771 (powerpc_opcodes) <wait>: Do not enable for POWER7.
772 <tlbie>: Add RS operand for POWER7.
773 <slbia>: Add IH operand for POWER6.
775 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
777 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
780 * i386-tbl.h: Regenerated.
782 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
784 * configure.ac: Support bfd_iamcu_arch.
785 * disassemble.c (disassembler): Support bfd_iamcu_arch.
786 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
787 CPU_IAMCU_COMPAT_FLAGS.
788 (cpu_flags): Add CpuIAMCU.
789 * i386-opc.h (CpuIAMCU): New.
790 (i386_cpu_flags): Add cpuiamcu.
791 * configure: Regenerated.
792 * i386-init.h: Likewise.
793 * i386-tbl.h: Likewise.
795 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
798 * i386-dis.c (X86_64_E8): New.
799 (X86_64_E9): Likewise.
800 Update comments on 'T', 'U', 'V'. Add comments for '^'.
801 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
802 (x86_64_table): Add X86_64_E8 and X86_64_E9.
803 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
805 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
808 2015-04-30 DJ Delorie <dj@redhat.com>
810 * disassemble.c (disassembler): Choose suitable disassembler based
812 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
813 it to decode mul/div insns.
814 * rl78-decode.c: Regenerate.
815 * rl78-dis.c (print_insn_rl78): Rename to...
816 (print_insn_rl78_common): ...this, take ISA parameter.
817 (print_insn_rl78): New.
818 (print_insn_rl78_g10): New.
819 (print_insn_rl78_g13): New.
820 (print_insn_rl78_g14): New.
821 (rl78_get_disassembler): New.
823 2015-04-29 Nick Clifton <nickc@redhat.com>
825 * po/fr.po: Updated French translation.
827 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
829 * ppc-opc.c (DCBT_EO): New define.
830 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
834 <waitrsv>: Do not enable for POWER7 and later.
835 <waitimpl>: Likewise.
836 <dcbt>: Default to the two operand form of the instruction for all
837 "old" cpus. For "new" cpus, use the operand ordering that matches
838 whether the cpu is server or embedded.
841 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
843 * s390-opc.c: New instruction type VV0UU2.
844 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
847 2015-04-23 Jan Beulich <jbeulich@suse.com>
849 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
850 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
851 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
852 (vfpclasspd, vfpclassps): Add %XZ.
854 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
856 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
857 (PREFIX_UD_REPZ): Likewise.
858 (PREFIX_UD_REPNZ): Likewise.
859 (PREFIX_UD_DATA): Likewise.
860 (PREFIX_UD_ADDR): Likewise.
861 (PREFIX_UD_LOCK): Likewise.
863 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
865 * i386-dis.c (prefix_requirement): Removed.
866 (print_insn): Don't set prefix_requirement. Check
867 dp->prefix_requirement instead of prefix_requirement.
869 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
872 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
873 (PREFIX_MOD_0_0FC7_REG_6): This.
874 (PREFIX_MOD_3_0FC7_REG_6): New.
875 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
876 (prefix_table): Replace PREFIX_0FC7_REG_6 with
877 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
878 PREFIX_MOD_3_0FC7_REG_7.
879 (mod_table): Replace PREFIX_0FC7_REG_6 with
880 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
881 PREFIX_MOD_3_0FC7_REG_7.
883 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
885 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
886 (PREFIX_MANDATORY_REPNZ): Likewise.
887 (PREFIX_MANDATORY_DATA): Likewise.
888 (PREFIX_MANDATORY_ADDR): Likewise.
889 (PREFIX_MANDATORY_LOCK): Likewise.
890 (PREFIX_MANDATORY): Likewise.
891 (PREFIX_UD_SHIFT): Set to 8
892 (PREFIX_UD_REPZ): Updated.
893 (PREFIX_UD_REPNZ): Likewise.
894 (PREFIX_UD_DATA): Likewise.
895 (PREFIX_UD_ADDR): Likewise.
896 (PREFIX_UD_LOCK): Likewise.
897 (PREFIX_IGNORED_SHIFT): New.
898 (PREFIX_IGNORED_REPZ): Likewise.
899 (PREFIX_IGNORED_REPNZ): Likewise.
900 (PREFIX_IGNORED_DATA): Likewise.
901 (PREFIX_IGNORED_ADDR): Likewise.
902 (PREFIX_IGNORED_LOCK): Likewise.
903 (PREFIX_OPCODE): Likewise.
904 (PREFIX_IGNORED): Likewise.
905 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
906 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
907 (three_byte_table): Likewise.
908 (mod_table): Likewise.
909 (mandatory_prefix): Renamed to ...
910 (prefix_requirement): This.
911 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
912 Update PREFIX_90 entry.
913 (get_valid_dis386): Check prefix_requirement to see if a prefix
915 (print_insn): Replace mandatory_prefix with prefix_requirement.
917 2015-04-15 Renlin Li <renlin.li@arm.com>
919 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
920 use it for ssat and ssat16.
921 (print_insn_thumb32): Add handle case for 'D' control code.
923 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
924 H.J. Lu <hongjiu.lu@intel.com>
926 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
927 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
928 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
929 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
930 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
931 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
932 Fill prefix_requirement field.
933 (struct dis386): Add prefix_requirement field.
934 (dis386): Fill prefix_requirement field.
935 (dis386_twobyte): Ditto.
936 (twobyte_has_mandatory_prefix_: Remove.
937 (reg_table): Fill prefix_requirement field.
938 (prefix_table): Ditto.
939 (x86_64_table): Ditto.
940 (three_byte_table): Ditto.
943 (vex_len_table): Ditto.
944 (vex_w_table): Ditto.
947 (print_insn): Use prefix_requirement.
948 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
949 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
952 2015-03-30 Mike Frysinger <vapier@gentoo.org>
954 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
956 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
958 * Makefile.in: Regenerated.
960 2015-03-25 Anton Blanchard <anton@samba.org>
962 * ppc-dis.c (disassemble_init_powerpc): Only initialise
963 powerpc_opcd_indices and vle_opcd_indices once.
965 2015-03-25 Anton Blanchard <anton@samba.org>
967 * ppc-opc.c (powerpc_opcodes): Add slbfee.
969 2015-03-24 Terry Guo <terry.guo@arm.com>
971 * arm-dis.c (opcode32): Updated to use new arm feature struct.
972 (opcode16): Likewise.
973 (coprocessor_opcodes): Replace bit with feature struct.
974 (neon_opcodes): Likewise.
975 (arm_opcodes): Likewise.
976 (thumb_opcodes): Likewise.
977 (thumb32_opcodes): Likewise.
978 (print_insn_coprocessor): Likewise.
979 (print_insn_arm): Likewise.
980 (select_arm_features): Follow new feature struct.
982 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
984 * i386-dis.c (rm_table): Add clzero.
985 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
986 Add CPU_CLZERO_FLAGS.
987 (cpu_flags): Add CpuCLZERO.
988 * i386-opc.h: Add CpuCLZERO.
989 * i386-opc.tbl: Add clzero.
990 * i386-init.h: Re-generated.
991 * i386-tbl.h: Re-generated.
993 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
995 * mips-opc.c (decode_mips_operand): Fix constraint issues
996 with u and y operands.
998 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1000 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1002 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1004 * s390-opc.c: Add new IBM z13 instructions.
1005 * s390-opc.txt: Likewise.
1007 2015-03-10 Renlin Li <renlin.li@arm.com>
1009 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1010 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1012 * aarch64-asm-2.c: Regenerate.
1013 * aarch64-dis-2.c: Likewise.
1014 * aarch64-opc-2.c: Likewise.
1016 2015-03-03 Jiong Wang <jiong.wang@arm.com>
1018 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1020 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1022 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1024 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1025 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1027 2015-02-23 Vinay <Vinay.G@kpit.com>
1029 * rl78-decode.opc (MOV): Added space between two operands for
1030 'mov' instruction in index addressing mode.
1031 * rl78-decode.c: Regenerate.
1033 2015-02-19 Pedro Alves <palves@redhat.com>
1035 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1037 2015-02-10 Pedro Alves <palves@redhat.com>
1038 Tom Tromey <tromey@redhat.com>
1040 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1041 microblaze_and, microblaze_xor.
1042 * microblaze-opc.h (opcodes): Adjust.
1044 2015-01-28 James Bowman <james.bowman@ftdichip.com>
1046 * Makefile.am: Add FT32 files.
1047 * configure.ac: Handle FT32.
1048 * disassemble.c (disassembler): Call print_insn_ft32.
1049 * ft32-dis.c: New file.
1050 * ft32-opc.c: New file.
1051 * Makefile.in: Regenerate.
1052 * configure: Regenerate.
1053 * po/POTFILES.in: Regenerate.
1055 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1057 * nds32-asm.c (keyword_sr): Add new system registers.
1059 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1061 * s390-dis.c (s390_extract_operand): Support vector register
1063 (s390_print_insn_with_opcode): Support new operands types and add
1064 new handling of optional operands.
1065 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1066 and include opcode/s390.h instead.
1067 (struct op_struct): New field `flags'.
1068 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1069 (dumpTable): Dump flags.
1070 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1072 * s390-opc.c: Add new operands types, instruction formats, and
1074 (s390_opformats): Add new formats for .insn.
1075 * s390-opc.txt: Add new instructions.
1077 2015-01-01 Alan Modra <amodra@gmail.com>
1079 Update year range in copyright notice of all files.
1081 For older changes see ChangeLog-2014
1083 Copyright (C) 2015 Free Software Foundation, Inc.
1085 Copying and distribution of this file, with or without modification,
1086 are permitted in any medium without royalty provided the copyright
1087 notice and this notice are preserved.
1093 version-control: never