1 2019-06-25 Jan Beulich <jbeulich@suse.com>
3 * i386-opc.tbl (and): Mark Imm8S form for optimization.
4 * i386-tbl.h: Re-generate.
6 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
8 * i386-dis-evex.h: Break into ...
9 * i386-dis-evex-len.h: New file.
10 * i386-dis-evex-mod.h: Likewise.
11 * i386-dis-evex-prefix.h: Likewise.
12 * i386-dis-evex-reg.h: Likewise.
13 * i386-dis-evex-w.h: Likewise.
14 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
15 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
18 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
21 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
22 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
24 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
25 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
26 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
27 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
28 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
29 EVEX_LEN_0F385B_P_2_W_1.
30 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
31 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
32 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
33 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
34 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
35 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
36 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
37 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
38 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
39 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
41 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
44 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
45 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
46 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
47 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
48 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
49 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
50 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
51 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
52 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
53 EVEX_LEN_0F3A43_P_2_W_1.
54 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
55 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
56 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
57 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
58 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
59 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
60 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
61 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
62 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
63 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
64 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
65 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
67 2019-06-14 Nick Clifton <nickc@redhat.com>
69 * po/fr.po; Updated French translation.
71 2019-06-13 Stafford Horne <shorne@gmail.com>
73 * or1k-asm.c: Regenerated.
74 * or1k-desc.c: Regenerated.
75 * or1k-desc.h: Regenerated.
76 * or1k-dis.c: Regenerated.
77 * or1k-ibld.c: Regenerated.
78 * or1k-opc.c: Regenerated.
79 * or1k-opc.h: Regenerated.
80 * or1k-opinst.c: Regenerated.
82 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
84 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
86 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
89 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
90 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
91 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
92 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
93 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
94 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
95 EVEX_LEN_0F3A1B_P_2_W_1.
96 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
97 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
98 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
99 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
100 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
101 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
102 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
103 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
105 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
108 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
109 EVEX.vvvv when disassembling VEX and EVEX instructions.
110 (OP_VEX): Set vex.register_specifier to 0 after readding
111 vex.register_specifier.
112 (OP_Vex_2src_1): Likewise.
113 (OP_Vex_2src_2): Likewise.
114 (OP_LWP_E): Likewise.
115 (OP_EX_Vex): Don't check vex.register_specifier.
116 (OP_XMM_Vex): Likewise.
118 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
119 Lili Cui <lili.cui@intel.com>
121 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
122 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
124 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
125 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
126 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
127 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
128 (i386_cpu_flags): Add cpuavx512_vp2intersect.
129 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
130 * i386-init.h: Regenerated.
131 * i386-tbl.h: Likewise.
133 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
134 Lili Cui <lili.cui@intel.com>
136 * doc/c-i386.texi: Document enqcmd.
137 * testsuite/gas/i386/enqcmd-intel.d: New file.
138 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
139 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
140 * testsuite/gas/i386/enqcmd.d: Likewise.
141 * testsuite/gas/i386/enqcmd.s: Likewise.
142 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
143 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
144 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
145 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
146 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
147 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
148 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
151 2019-06-04 Alan Hayward <alan.hayward@arm.com>
153 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
155 2019-06-03 Alan Modra <amodra@gmail.com>
157 * ppc-dis.c (prefix_opcd_indices): Correct size.
159 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
162 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
164 * i386-tbl.h: Regenerated.
166 2019-05-24 Alan Modra <amodra@gmail.com>
168 * po/POTFILES.in: Regenerate.
170 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
171 Alan Modra <amodra@gmail.com>
173 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
174 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
175 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
176 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
177 XTOP>): Define and add entries.
178 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
179 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
180 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
181 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
183 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
184 Alan Modra <amodra@gmail.com>
186 * ppc-dis.c (ppc_opts): Add "future" entry.
187 (PREFIX_OPCD_SEGS): Define.
188 (prefix_opcd_indices): New array.
189 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
190 (lookup_prefix): New function.
191 (print_insn_powerpc): Handle 64-bit prefix instructions.
192 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
193 (PMRR, POWERXX): Define.
194 (prefix_opcodes): New instruction table.
195 (prefix_num_opcodes): New constant.
197 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
199 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
200 * configure: Regenerated.
201 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
203 (HFILES): Add bpf-desc.h and bpf-opc.h.
204 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
205 bpf-ibld.c and bpf-opc.c.
207 * Makefile.in: Regenerated.
208 * disassemble.c (ARCH_bpf): Define.
209 (disassembler): Add case for bfd_arch_bpf.
210 (disassemble_init_for_target): Likewise.
211 (enum epbf_isa_attr): Define.
212 * disassemble.h: extern print_insn_bpf.
213 * bpf-asm.c: Generated.
214 * bpf-opc.h: Likewise.
215 * bpf-opc.c: Likewise.
216 * bpf-ibld.c: Likewise.
217 * bpf-dis.c: Likewise.
218 * bpf-desc.h: Likewise.
219 * bpf-desc.c: Likewise.
221 2019-05-21 Sudakshina Das <sudi.das@arm.com>
223 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
224 and VMSR with the new operands.
226 2019-05-21 Sudakshina Das <sudi.das@arm.com>
228 * arm-dis.c (enum mve_instructions): New enum
229 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
231 (mve_opcodes): New instructions as above.
232 (is_mve_encoding_conflict): Add cases for csinc, csinv,
234 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
236 2019-05-21 Sudakshina Das <sudi.das@arm.com>
238 * arm-dis.c (emun mve_instructions): Updated for new instructions.
239 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
240 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
241 uqshl, urshrl and urshr.
242 (is_mve_okay_in_it): Add new instructions to TRUE list.
243 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
244 (print_insn_mve): Updated to accept new %j,
245 %<bitfield>m and %<bitfield>n patterns.
247 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
249 * mips-opc.c (mips_builtin_opcodes): Change source register
252 2019-05-20 Nick Clifton <nickc@redhat.com>
254 * po/fr.po: Updated French translation.
256 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
257 Michael Collison <michael.collison@arm.com>
259 * arm-dis.c (thumb32_opcodes): Add new instructions.
260 (enum mve_instructions): Likewise.
261 (enum mve_undefined): Add new reasons.
262 (is_mve_encoding_conflict): Handle new instructions.
263 (is_mve_undefined): Likewise.
264 (is_mve_unpredictable): Likewise.
265 (print_mve_undefined): Likewise.
266 (print_mve_size): Likewise.
268 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
269 Michael Collison <michael.collison@arm.com>
271 * arm-dis.c (thumb32_opcodes): Add new instructions.
272 (enum mve_instructions): Likewise.
273 (is_mve_encoding_conflict): Handle new instructions.
274 (is_mve_undefined): Likewise.
275 (is_mve_unpredictable): Likewise.
276 (print_mve_size): Likewise.
278 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
279 Michael Collison <michael.collison@arm.com>
281 * arm-dis.c (thumb32_opcodes): Add new instructions.
282 (enum mve_instructions): Likewise.
283 (is_mve_encoding_conflict): Likewise.
284 (is_mve_unpredictable): Likewise.
285 (print_mve_size): Likewise.
287 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
288 Michael Collison <michael.collison@arm.com>
290 * arm-dis.c (thumb32_opcodes): Add new instructions.
291 (enum mve_instructions): Likewise.
292 (is_mve_encoding_conflict): Handle new instructions.
293 (is_mve_undefined): Likewise.
294 (is_mve_unpredictable): Likewise.
295 (print_mve_size): Likewise.
297 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
298 Michael Collison <michael.collison@arm.com>
300 * arm-dis.c (thumb32_opcodes): Add new instructions.
301 (enum mve_instructions): Likewise.
302 (is_mve_encoding_conflict): Handle new instructions.
303 (is_mve_undefined): Likewise.
304 (is_mve_unpredictable): Likewise.
305 (print_mve_size): Likewise.
306 (print_insn_mve): Likewise.
308 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
309 Michael Collison <michael.collison@arm.com>
311 * arm-dis.c (thumb32_opcodes): Add new instructions.
312 (print_insn_thumb32): Handle new instructions.
314 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
315 Michael Collison <michael.collison@arm.com>
317 * arm-dis.c (enum mve_instructions): Add new instructions.
318 (enum mve_undefined): Add new reasons.
319 (is_mve_encoding_conflict): Handle new instructions.
320 (is_mve_undefined): Likewise.
321 (is_mve_unpredictable): Likewise.
322 (print_mve_undefined): Likewise.
323 (print_mve_size): Likewise.
324 (print_mve_shift_n): Likewise.
325 (print_insn_mve): Likewise.
327 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
328 Michael Collison <michael.collison@arm.com>
330 * arm-dis.c (enum mve_instructions): Add new instructions.
331 (is_mve_encoding_conflict): Handle new instructions.
332 (is_mve_unpredictable): Likewise.
333 (print_mve_rotate): Likewise.
334 (print_mve_size): Likewise.
335 (print_insn_mve): Likewise.
337 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
338 Michael Collison <michael.collison@arm.com>
340 * arm-dis.c (enum mve_instructions): Add new instructions.
341 (is_mve_encoding_conflict): Handle new instructions.
342 (is_mve_unpredictable): Likewise.
343 (print_mve_size): Likewise.
344 (print_insn_mve): Likewise.
346 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
347 Michael Collison <michael.collison@arm.com>
349 * arm-dis.c (enum mve_instructions): Add new instructions.
350 (enum mve_undefined): Add new reasons.
351 (is_mve_encoding_conflict): Handle new instructions.
352 (is_mve_undefined): Likewise.
353 (is_mve_unpredictable): Likewise.
354 (print_mve_undefined): Likewise.
355 (print_mve_size): Likewise.
356 (print_insn_mve): Likewise.
358 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
359 Michael Collison <michael.collison@arm.com>
361 * arm-dis.c (enum mve_instructions): Add new instructions.
362 (is_mve_encoding_conflict): Handle new instructions.
363 (is_mve_undefined): Likewise.
364 (is_mve_unpredictable): Likewise.
365 (print_mve_size): Likewise.
366 (print_insn_mve): Likewise.
368 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
369 Michael Collison <michael.collison@arm.com>
371 * arm-dis.c (enum mve_instructions): Add new instructions.
372 (enum mve_unpredictable): Add new reasons.
373 (enum mve_undefined): Likewise.
374 (is_mve_okay_in_it): Handle new isntructions.
375 (is_mve_encoding_conflict): Likewise.
376 (is_mve_undefined): Likewise.
377 (is_mve_unpredictable): Likewise.
378 (print_mve_vmov_index): Likewise.
379 (print_simd_imm8): Likewise.
380 (print_mve_undefined): Likewise.
381 (print_mve_unpredictable): Likewise.
382 (print_mve_size): Likewise.
383 (print_insn_mve): Likewise.
385 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
386 Michael Collison <michael.collison@arm.com>
388 * arm-dis.c (enum mve_instructions): Add new instructions.
389 (enum mve_unpredictable): Add new reasons.
390 (enum mve_undefined): Likewise.
391 (is_mve_encoding_conflict): Handle new instructions.
392 (is_mve_undefined): Likewise.
393 (is_mve_unpredictable): Likewise.
394 (print_mve_undefined): Likewise.
395 (print_mve_unpredictable): Likewise.
396 (print_mve_rounding_mode): Likewise.
397 (print_mve_vcvt_size): Likewise.
398 (print_mve_size): Likewise.
399 (print_insn_mve): Likewise.
401 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
402 Michael Collison <michael.collison@arm.com>
404 * arm-dis.c (enum mve_instructions): Add new instructions.
405 (enum mve_unpredictable): Add new reasons.
406 (enum mve_undefined): Likewise.
407 (is_mve_undefined): Handle new instructions.
408 (is_mve_unpredictable): Likewise.
409 (print_mve_undefined): Likewise.
410 (print_mve_unpredictable): Likewise.
411 (print_mve_size): Likewise.
412 (print_insn_mve): Likewise.
414 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
415 Michael Collison <michael.collison@arm.com>
417 * arm-dis.c (enum mve_instructions): Add new instructions.
418 (enum mve_undefined): Add new reasons.
419 (insns): Add new instructions.
420 (is_mve_encoding_conflict):
421 (print_mve_vld_str_addr): New print function.
422 (is_mve_undefined): Handle new instructions.
423 (is_mve_unpredictable): Likewise.
424 (print_mve_undefined): Likewise.
425 (print_mve_size): Likewise.
426 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
427 (print_insn_mve): Handle new operands.
429 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
430 Michael Collison <michael.collison@arm.com>
432 * arm-dis.c (enum mve_instructions): Add new instructions.
433 (enum mve_unpredictable): Add new reasons.
434 (is_mve_encoding_conflict): Handle new instructions.
435 (is_mve_unpredictable): Likewise.
436 (mve_opcodes): Add new instructions.
437 (print_mve_unpredictable): Handle new reasons.
438 (print_mve_register_blocks): New print function.
439 (print_mve_size): Handle new instructions.
440 (print_insn_mve): Likewise.
442 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
443 Michael Collison <michael.collison@arm.com>
445 * arm-dis.c (enum mve_instructions): Add new instructions.
446 (enum mve_unpredictable): Add new reasons.
447 (enum mve_undefined): Likewise.
448 (is_mve_encoding_conflict): Handle new instructions.
449 (is_mve_undefined): Likewise.
450 (is_mve_unpredictable): Likewise.
451 (coprocessor_opcodes): Move NEON VDUP from here...
452 (neon_opcodes): ... to here.
453 (mve_opcodes): Add new instructions.
454 (print_mve_undefined): Handle new reasons.
455 (print_mve_unpredictable): Likewise.
456 (print_mve_size): Handle new instructions.
457 (print_insn_neon): Handle vdup.
458 (print_insn_mve): Handle new operands.
460 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
461 Michael Collison <michael.collison@arm.com>
463 * arm-dis.c (enum mve_instructions): Add new instructions.
464 (enum mve_unpredictable): Add new values.
465 (mve_opcodes): Add new instructions.
466 (vec_condnames): New array with vector conditions.
467 (mve_predicatenames): New array with predicate suffixes.
468 (mve_vec_sizename): New array with vector sizes.
469 (enum vpt_pred_state): New enum with vector predication states.
470 (struct vpt_block): New struct type for vpt blocks.
471 (vpt_block_state): Global struct to keep track of state.
472 (mve_extract_pred_mask): New helper function.
473 (num_instructions_vpt_block): Likewise.
474 (mark_outside_vpt_block): Likewise.
475 (mark_inside_vpt_block): Likewise.
476 (invert_next_predicate_state): Likewise.
477 (update_next_predicate_state): Likewise.
478 (update_vpt_block_state): Likewise.
479 (is_vpt_instruction): Likewise.
480 (is_mve_encoding_conflict): Add entries for new instructions.
481 (is_mve_unpredictable): Likewise.
482 (print_mve_unpredictable): Handle new cases.
483 (print_instruction_predicate): Likewise.
484 (print_mve_size): New function.
485 (print_vec_condition): New function.
486 (print_insn_mve): Handle vpt blocks and new print operands.
488 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
490 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
491 8, 14 and 15 for Armv8.1-M Mainline.
493 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
494 Michael Collison <michael.collison@arm.com>
496 * arm-dis.c (enum mve_instructions): New enum.
497 (enum mve_unpredictable): Likewise.
498 (enum mve_undefined): Likewise.
499 (struct mopcode32): New struct.
500 (is_mve_okay_in_it): New function.
501 (is_mve_architecture): Likewise.
502 (arm_decode_field): Likewise.
503 (arm_decode_field_multiple): Likewise.
504 (is_mve_encoding_conflict): Likewise.
505 (is_mve_undefined): Likewise.
506 (is_mve_unpredictable): Likewise.
507 (print_mve_undefined): Likewise.
508 (print_mve_unpredictable): Likewise.
509 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
510 (print_insn_mve): New function.
511 (print_insn_thumb32): Handle MVE architecture.
512 (select_arm_features): Force thumb for Armv8.1-m Mainline.
514 2019-05-10 Nick Clifton <nickc@redhat.com>
517 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
518 end of the table prematurely.
520 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
522 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
525 2019-05-11 Alan Modra <amodra@gmail.com>
527 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
528 when -Mraw is in effect.
530 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
532 * aarch64-dis-2.c: Regenerate.
533 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
534 (OP_SVE_BBB): New variant set.
535 (OP_SVE_DDDD): New variant set.
536 (OP_SVE_HHH): New variant set.
537 (OP_SVE_HHHU): New variant set.
538 (OP_SVE_SSS): New variant set.
539 (OP_SVE_SSSU): New variant set.
540 (OP_SVE_SHH): New variant set.
541 (OP_SVE_SBBU): New variant set.
542 (OP_SVE_DSS): New variant set.
543 (OP_SVE_DHHU): New variant set.
544 (OP_SVE_VMV_HSD_BHS): New variant set.
545 (OP_SVE_VVU_HSD_BHS): New variant set.
546 (OP_SVE_VVVU_SD_BH): New variant set.
547 (OP_SVE_VVVU_BHSD): New variant set.
548 (OP_SVE_VVV_QHD_DBS): New variant set.
549 (OP_SVE_VVV_HSD_BHS): New variant set.
550 (OP_SVE_VVV_HSD_BHS2): New variant set.
551 (OP_SVE_VVV_BHS_HSD): New variant set.
552 (OP_SVE_VV_BHS_HSD): New variant set.
553 (OP_SVE_VVV_SD): New variant set.
554 (OP_SVE_VVU_BHS_HSD): New variant set.
555 (OP_SVE_VZVV_SD): New variant set.
556 (OP_SVE_VZVV_BH): New variant set.
557 (OP_SVE_VZV_SD): New variant set.
558 (aarch64_opcode_table): Add sve2 instructions.
560 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
562 * aarch64-asm-2.c: Regenerated.
563 * aarch64-dis-2.c: Regenerated.
564 * aarch64-opc-2.c: Regenerated.
565 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
566 for SVE_SHLIMM_UNPRED_22.
567 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
568 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
571 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
573 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
574 sve_size_tsz_bhs iclass encode.
575 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
576 sve_size_tsz_bhs iclass decode.
578 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
580 * aarch64-asm-2.c: Regenerated.
581 * aarch64-dis-2.c: Regenerated.
582 * aarch64-opc-2.c: Regenerated.
583 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
584 for SVE_Zm4_11_INDEX.
585 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
586 (fields): Handle SVE_i2h field.
587 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
588 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
590 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
592 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
593 sve_shift_tsz_bhsd iclass encode.
594 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
595 sve_shift_tsz_bhsd iclass decode.
597 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
599 * aarch64-asm-2.c: Regenerated.
600 * aarch64-dis-2.c: Regenerated.
601 * aarch64-opc-2.c: Regenerated.
602 * aarch64-asm.c (aarch64_ins_sve_shrimm):
603 (aarch64_encode_variant_using_iclass): Handle
604 sve_shift_tsz_hsd iclass encode.
605 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
606 sve_shift_tsz_hsd iclass decode.
607 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
608 for SVE_SHRIMM_UNPRED_22.
609 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
610 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
613 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
615 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
616 sve_size_013 iclass encode.
617 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
618 sve_size_013 iclass decode.
620 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
622 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
623 sve_size_bh iclass encode.
624 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
625 sve_size_bh iclass decode.
627 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
629 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
630 sve_size_sd2 iclass encode.
631 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
632 sve_size_sd2 iclass decode.
633 * aarch64-opc.c (fields): Handle SVE_sz2 field.
634 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
636 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
638 * aarch64-asm-2.c: Regenerated.
639 * aarch64-dis-2.c: Regenerated.
640 * aarch64-opc-2.c: Regenerated.
641 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
643 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
644 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
646 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
648 * aarch64-asm-2.c: Regenerated.
649 * aarch64-dis-2.c: Regenerated.
650 * aarch64-opc-2.c: Regenerated.
651 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
652 for SVE_Zm3_11_INDEX.
653 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
654 (fields): Handle SVE_i3l and SVE_i3h2 fields.
655 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
657 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
659 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
661 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
662 sve_size_hsd2 iclass encode.
663 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
664 sve_size_hsd2 iclass decode.
665 * aarch64-opc.c (fields): Handle SVE_size field.
666 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
668 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
670 * aarch64-asm-2.c: Regenerated.
671 * aarch64-dis-2.c: Regenerated.
672 * aarch64-opc-2.c: Regenerated.
673 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
675 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
676 (fields): Handle SVE_rot3 field.
677 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
678 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
680 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
682 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
685 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
688 (aarch64_feature_sve2, aarch64_feature_sve2aes,
689 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
690 aarch64_feature_sve2bitperm): New feature sets.
691 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
692 for feature set addresses.
693 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
694 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
696 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
697 Faraz Shahbazker <fshahbazker@wavecomp.com>
699 * mips-dis.c (mips_calculate_combination_ases): Add ISA
700 argument and set ASE_EVA_R6 appropriately.
701 (set_default_mips_dis_options): Pass ISA to above.
702 (parse_mips_dis_option): Likewise.
703 * mips-opc.c (EVAR6): New macro.
704 (mips_builtin_opcodes): Add llwpe, scwpe.
706 2019-05-01 Sudakshina Das <sudi.das@arm.com>
708 * aarch64-asm-2.c: Regenerated.
709 * aarch64-dis-2.c: Regenerated.
710 * aarch64-opc-2.c: Regenerated.
711 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
712 AARCH64_OPND_TME_UIMM16.
713 (aarch64_print_operand): Likewise.
714 * aarch64-tbl.h (QL_IMM_NIL): New.
717 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
719 2019-04-29 John Darrington <john@darrington.wattle.id.au>
721 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
723 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
724 Faraz Shahbazker <fshahbazker@wavecomp.com>
726 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
728 2019-04-24 John Darrington <john@darrington.wattle.id.au>
730 * s12z-opc.h: Add extern "C" bracketing to help
731 users who wish to use this interface in c++ code.
733 2019-04-24 John Darrington <john@darrington.wattle.id.au>
735 * s12z-opc.c (bm_decode): Handle bit map operations with the
738 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
740 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
741 specifier. Add entries for VLDR and VSTR of system registers.
742 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
743 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
744 of %J and %K format specifier.
746 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
748 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
749 Add new entries for VSCCLRM instruction.
750 (print_insn_coprocessor): Handle new %C format control code.
752 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
754 * arm-dis.c (enum isa): New enum.
755 (struct sopcode32): New structure.
756 (coprocessor_opcodes): change type of entries to struct sopcode32 and
757 set isa field of all current entries to ANY.
758 (print_insn_coprocessor): Change type of insn to struct sopcode32.
759 Only match an entry if its isa field allows the current mode.
761 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
763 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
765 (print_insn_thumb32): Add logic to print %n CLRM register list.
767 2019-04-15 Sudakshina Das <sudi.das@arm.com>
769 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
772 2019-04-15 Sudakshina Das <sudi.das@arm.com>
774 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
775 (print_insn_thumb32): Edit the switch case for %Z.
777 2019-04-15 Sudakshina Das <sudi.das@arm.com>
779 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
781 2019-04-15 Sudakshina Das <sudi.das@arm.com>
783 * arm-dis.c (thumb32_opcodes): New instruction bfl.
785 2019-04-15 Sudakshina Das <sudi.das@arm.com>
787 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
789 2019-04-15 Sudakshina Das <sudi.das@arm.com>
791 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
792 Arm register with r13 and r15 unpredictable.
793 (thumb32_opcodes): New instructions for bfx and bflx.
795 2019-04-15 Sudakshina Das <sudi.das@arm.com>
797 * arm-dis.c (thumb32_opcodes): New instructions for bf.
799 2019-04-15 Sudakshina Das <sudi.das@arm.com>
801 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
803 2019-04-15 Sudakshina Das <sudi.das@arm.com>
805 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
807 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
809 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
811 2019-04-12 John Darrington <john@darrington.wattle.id.au>
813 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
814 "optr". ("operator" is a reserved word in c++).
816 2019-04-11 Sudakshina Das <sudi.das@arm.com>
818 * aarch64-opc.c (aarch64_print_operand): Add case for
820 (verify_constraints): Likewise.
821 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
822 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
823 to accept Rt|SP as first operand.
824 (AARCH64_OPERANDS): Add new Rt_SP.
825 * aarch64-asm-2.c: Regenerated.
826 * aarch64-dis-2.c: Regenerated.
827 * aarch64-opc-2.c: Regenerated.
829 2019-04-11 Sudakshina Das <sudi.das@arm.com>
831 * aarch64-asm-2.c: Regenerated.
832 * aarch64-dis-2.c: Likewise.
833 * aarch64-opc-2.c: Likewise.
834 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
836 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
838 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
840 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
842 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
843 * i386-init.h: Regenerated.
845 2019-04-07 Alan Modra <amodra@gmail.com>
847 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
848 op_separator to control printing of spaces, comma and parens
849 rather than need_comma, need_paren and spaces vars.
851 2019-04-07 Alan Modra <amodra@gmail.com>
854 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
855 (print_insn_neon, print_insn_arm): Likewise.
857 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
859 * i386-dis-evex.h (evex_table): Updated to support BF16
861 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
862 and EVEX_W_0F3872_P_3.
863 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
864 (cpu_flags): Add bitfield for CpuAVX512_BF16.
865 * i386-opc.h (enum): Add CpuAVX512_BF16.
866 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
867 * i386-opc.tbl: Add AVX512 BF16 instructions.
868 * i386-init.h: Regenerated.
869 * i386-tbl.h: Likewise.
871 2019-04-05 Alan Modra <amodra@gmail.com>
873 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
874 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
875 to favour printing of "-" branch hint when using the "y" bit.
876 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
878 2019-04-05 Alan Modra <amodra@gmail.com>
880 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
881 opcode until first operand is output.
883 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
886 * ppc-opc.c (valid_bo_pre_v2): Add comments.
887 (valid_bo_post_v2): Add support for 'at' branch hints.
888 (insert_bo): Only error on branch on ctr.
889 (get_bo_hint_mask): New function.
890 (insert_boe): Add new 'branch_taken' formal argument. Add support
891 for inserting 'at' branch hints.
892 (extract_boe): Add new 'branch_taken' formal argument. Add support
893 for extracting 'at' branch hints.
894 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
895 (BOE): Delete operand.
896 (BOM, BOP): New operands.
898 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
899 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
900 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
901 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
902 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
903 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
904 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
905 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
906 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
907 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
908 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
909 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
910 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
911 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
912 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
913 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
914 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
915 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
916 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
917 bttarl+>: New extended mnemonics.
919 2019-03-28 Alan Modra <amodra@gmail.com>
922 * ppc-opc.c (BTF): Define.
923 (powerpc_opcodes): Use for mtfsb*.
924 * ppc-dis.c (print_insn_powerpc): Print fields with both
925 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
927 2019-03-25 Tamar Christina <tamar.christina@arm.com>
929 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
930 (mapping_symbol_for_insn): Implement new algorithm.
931 (print_insn): Remove duplicate code.
933 2019-03-25 Tamar Christina <tamar.christina@arm.com>
935 * aarch64-dis.c (print_insn_aarch64):
938 2019-03-25 Tamar Christina <tamar.christina@arm.com>
940 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
943 2019-03-25 Tamar Christina <tamar.christina@arm.com>
945 * aarch64-dis.c (last_stop_offset): New.
946 (print_insn_aarch64): Use stop_offset.
948 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
951 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
953 * i386-init.h: Regenerated.
955 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
958 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
959 vmovdqu16, vmovdqu32 and vmovdqu64.
960 * i386-tbl.h: Regenerated.
962 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
964 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
965 from vstrszb, vstrszh, and vstrszf.
967 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
969 * s390-opc.txt: Add instruction descriptions.
971 2019-02-08 Jim Wilson <jimw@sifive.com>
973 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
976 2019-02-07 Tamar Christina <tamar.christina@arm.com>
978 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
980 2019-02-07 Tamar Christina <tamar.christina@arm.com>
983 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
984 * aarch64-opc.c (verify_elem_sd): New.
985 (fields): Add FLD_sz entr.
986 * aarch64-tbl.h (_SIMD_INSN): New.
987 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
988 fmulx scalar and vector by element isns.
990 2019-02-07 Nick Clifton <nickc@redhat.com>
992 * po/sv.po: Updated Swedish translation.
994 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
996 * s390-mkopc.c (main): Accept arch13 as cpu string.
997 * s390-opc.c: Add new instruction formats and instruction opcode
999 * s390-opc.txt: Add new arch13 instructions.
1001 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1003 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1004 (aarch64_opcode): Change encoding for stg, stzg
1006 * aarch64-asm-2.c: Regenerated.
1007 * aarch64-dis-2.c: Regenerated.
1008 * aarch64-opc-2.c: Regenerated.
1010 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1012 * aarch64-asm-2.c: Regenerated.
1013 * aarch64-dis-2.c: Likewise.
1014 * aarch64-opc-2.c: Likewise.
1015 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1017 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1018 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1020 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1021 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1022 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1023 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1024 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1025 case for ldstgv_indexed.
1026 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1027 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1028 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1029 * aarch64-asm-2.c: Regenerated.
1030 * aarch64-dis-2.c: Regenerated.
1031 * aarch64-opc-2.c: Regenerated.
1033 2019-01-23 Nick Clifton <nickc@redhat.com>
1035 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1037 2019-01-21 Nick Clifton <nickc@redhat.com>
1039 * po/de.po: Updated German translation.
1040 * po/uk.po: Updated Ukranian translation.
1042 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1043 * mips-dis.c (mips_arch_choices): Fix typo in
1044 gs464, gs464e and gs264e descriptors.
1046 2019-01-19 Nick Clifton <nickc@redhat.com>
1048 * configure: Regenerate.
1049 * po/opcodes.pot: Regenerate.
1051 2018-06-24 Nick Clifton <nickc@redhat.com>
1053 2.32 branch created.
1055 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1057 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1059 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1062 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1064 * configure: Regenerate.
1066 2019-01-07 Alan Modra <amodra@gmail.com>
1068 * configure: Regenerate.
1069 * po/POTFILES.in: Regenerate.
1071 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1073 * s12z-opc.c: New file.
1074 * s12z-opc.h: New file.
1075 * s12z-dis.c: Removed all code not directly related to display
1076 of instructions. Used the interface provided by the new files
1078 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1079 * Makefile.in: Regenerate.
1080 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1081 * configure: Regenerate.
1083 2019-01-01 Alan Modra <amodra@gmail.com>
1085 Update year range in copyright notice of all files.
1087 For older changes see ChangeLog-2018
1089 Copyright (C) 2019 Free Software Foundation, Inc.
1091 Copying and distribution of this file, with or without modification,
1092 are permitted in any medium without royalty provided the copyright
1093 notice and this notice are preserved.
1099 version-control: never