1 2018-10-09 Sudakshina Das <sudi.das@arm.com>
3 * aarch64-opc.c (operand_general_constraint_met_p): Add
4 SSBS in the check for one-bit immediate.
5 (aarch64_sys_regs): New entry for SSBS.
6 (aarch64_sys_reg_supported_p): New check for above.
7 (aarch64_pstatefields): New entry for SSBS.
8 (aarch64_pstatefield_supported_p): New check for above.
10 2018-10-09 Sudakshina Das <sudi.das@arm.com>
12 * aarch64-opc.c (aarch64_sys_regs): New entries for
13 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
14 (aarch64_sys_reg_supported_p): New checks for above.
16 2018-10-09 Sudakshina Das <sudi.das@arm.com>
18 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
19 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
20 with the hint immediate.
21 * aarch64-opc.c (aarch64_hint_options): New entries for
22 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
23 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
24 while checking for HINT_OPD_F_NOPRINT flag.
25 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
27 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
28 (aarch64_opcode_table): Add entry for BTI.
29 (AARCH64_OPERANDS): Add new description for BTI targets.
30 * aarch64-asm-2.c: Regenerate.
31 * aarch64-dis-2.c: Regenerate.
32 * aarch64-opc-2.c: Regenerate.
34 2018-10-09 Sudakshina Das <sudi.das@arm.com>
36 * aarch64-opc.c (aarch64_sys_regs): New entries for
38 (aarch64_sys_reg_supported_p): New check for above.
40 2018-10-09 Sudakshina Das <sudi.das@arm.com>
42 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
43 (aarch64_sys_ins_reg_supported_p): New check for above.
45 2018-10-09 Sudakshina Das <sudi.das@arm.com>
47 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
48 AARCH64_OPND_SYSREG_SR.
49 * aarch64-opc.c (aarch64_print_operand): Likewise.
50 (aarch64_sys_regs_sr): Define table.
51 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
52 AARCH64_FEATURE_PREDRES.
53 * aarch64-tbl.h (aarch64_feature_predres): New.
54 (PREDRES, PREDRES_INSN): New.
55 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
56 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
57 * aarch64-asm-2.c: Regenerate.
58 * aarch64-dis-2.c: Regenerate.
59 * aarch64-opc-2.c: Regenerate.
61 2018-10-09 Sudakshina Das <sudi.das@arm.com>
63 * aarch64-tbl.h (aarch64_feature_sb): New.
65 (aarch64_opcode_table): Add entry for sb.
66 * aarch64-asm-2.c: Regenerate.
67 * aarch64-dis-2.c: Regenerate.
68 * aarch64-opc-2.c: Regenerate.
70 2018-10-09 Sudakshina Das <sudi.das@arm.com>
72 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
73 (aarch64_feature_frintts): New.
74 (FLAGMANIP, FRINTTS): New.
75 (aarch64_opcode_table): Add entries for xaflag, axflag
76 and frint[32,64][x,z] instructions.
77 * aarch64-asm-2.c: Regenerate.
78 * aarch64-dis-2.c: Regenerate.
79 * aarch64-opc-2.c: Regenerate.
81 2018-10-09 Sudakshina Das <sudi.das@arm.com>
83 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
84 (ARMV8_5, V8_5_INSN): New.
86 2018-10-08 Tamar Christina <tamar.christina@arm.com>
88 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
90 2018-10-05 H.J. Lu <hongjiu.lu@intel.com>
92 * i386-dis.c (rm_table): Add enclv.
93 * i386-opc.tbl: Add enclv.
94 * i386-tbl.h: Regenerated.
96 2018-10-05 Sudakshina Das <sudi.das@arm.com>
98 * arm-dis.c (arm_opcodes): Add sb.
99 (thumb32_opcodes): Likewise.
101 2018-10-05 Richard Henderson <rth@twiddle.net>
102 Stafford Horne <shorne@gmail.com>
104 * or1k-desc.c: Regenerate.
105 * or1k-desc.h: Regenerate.
106 * or1k-opc.c: Regenerate.
107 * or1k-opc.h: Regenerate.
108 * or1k-opinst.c: Regenerate.
110 2018-10-05 Richard Henderson <rth@twiddle.net>
112 * or1k-asm.c: Regenerated.
113 * or1k-desc.c: Regenerated.
114 * or1k-desc.h: Regenerated.
115 * or1k-dis.c: Regenerated.
116 * or1k-ibld.c: Regenerated.
117 * or1k-opc.c: Regenerated.
118 * or1k-opc.h: Regenerated.
119 * or1k-opinst.c: Regenerated.
121 2018-10-05 Richard Henderson <rth@twiddle.net>
123 * or1k-asm.c: Regenerate.
125 2018-10-03 Tamar Christina <tamar.christina@arm.com>
127 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
128 * aarch64-dis.c (print_operands): Refactor to take notes.
129 (print_verifier_notes): New.
130 (print_aarch64_insn): Apply constraint verifier.
131 (print_insn_aarch64_word): Update call to print_aarch64_insn.
132 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
134 2018-10-03 Tamar Christina <tamar.christina@arm.com>
136 * aarch64-opc.c (init_insn_block): New.
137 (verify_constraints, aarch64_is_destructive_by_operands): New.
138 * aarch64-opc.h (verify_constraints): New.
140 2018-10-03 Tamar Christina <tamar.christina@arm.com>
142 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
143 * aarch64-opc.c (verify_ldpsw): Update arguments.
145 2018-10-03 Tamar Christina <tamar.christina@arm.com>
147 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
148 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
150 2018-10-03 Tamar Christina <tamar.christina@arm.com>
152 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
153 * aarch64-dis.c (insn_sequence): New.
155 2018-10-03 Tamar Christina <tamar.christina@arm.com>
157 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
158 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
159 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
160 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
163 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
165 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
167 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
168 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
169 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
170 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
171 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
172 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
173 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
175 2018-10-02 Palmer Dabbelt <palmer@sifive.com>
177 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
179 2018-09-23 Sandra Loosemore <sandra@codesourcery.com>
181 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
182 are used when extracting signed fields and converting them to
183 potentially 64-bit types.
185 2018-09-21 Simon Marchi <simon.marchi@ericsson.com>
187 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
188 * Makefile.in: Re-generate.
189 * aclocal.m4: Re-generate.
190 * configure: Re-generate.
191 * configure.ac: Remove check for -Wno-missing-field-initializers.
192 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
193 (csky_v2_opcodes): Likewise.
195 2018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
197 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
199 2018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
201 * nds32-asm.c (operand_fields): Remove the unused fields.
202 (nds32_opcodes): Remove the unused instructions.
203 * nds32-dis.c (nds32_ex9_info): Removed.
204 (nds32_parse_opcode): Updated.
205 (print_insn_nds32): Likewise.
206 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
207 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
208 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
209 build_opcode_hash_table): New functions.
210 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
211 nds32_opcode_table): New.
212 (hw_ktabs): Declare it to a pointer rather than an array.
213 (build_hash_table): Removed.
214 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
215 SYN_ROPT and upadte HW_GPR and HW_INT.
216 * nds32-dis.c (keywords): Remove const.
217 (match_field): New function.
218 (nds32_parse_opcode): Updated.
219 * disassemble.c (disassemble_init_for_target):
220 Add disassemble_init_nds32.
221 * nds32-dis.c (eum map_type): New.
222 (nds32_private_data): Likewise.
223 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
224 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
225 (print_insn_nds32): Updated.
226 * nds32-asm.c (parse_aext_reg): Add new parameter.
227 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
230 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
231 (operand_fields): Add new fields.
232 (nds32_opcodes): Add new instructions.
233 (keyword_aridxi_mx): New keyword.
234 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
236 (ALU2_1, ALU2_2, ALU2_3): New macros.
237 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
239 2018-09-17 Kito Cheng <kito@andestech.com>
241 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
243 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
246 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
247 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
248 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
249 (EVEX_LEN_0F7E_P_1): Likewise.
250 (EVEX_LEN_0F7E_P_2): Likewise.
251 (EVEX_LEN_0FD6_P_2): Likewise.
252 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
253 (EVEX_LEN_TABLE): Likewise.
254 (EVEX_LEN_0F6E_P_2): New enum.
255 (EVEX_LEN_0F7E_P_1): Likewise.
256 (EVEX_LEN_0F7E_P_2): Likewise.
257 (EVEX_LEN_0FD6_P_2): Likewise.
258 (evex_len_table): New.
259 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
260 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
261 * i386-tbl.h: Regenerated.
263 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
266 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
267 VEX_LEN_0F7E_P_2 entries.
268 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
269 * i386-tbl.h: Regenerated.
271 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
273 * i386-dis.c (VZERO_Fixup): Removed.
275 (VEX_LEN_0F10_P_1): Likewise.
276 (VEX_LEN_0F10_P_3): Likewise.
277 (VEX_LEN_0F11_P_1): Likewise.
278 (VEX_LEN_0F11_P_3): Likewise.
279 (VEX_LEN_0F2E_P_0): Likewise.
280 (VEX_LEN_0F2E_P_2): Likewise.
281 (VEX_LEN_0F2F_P_0): Likewise.
282 (VEX_LEN_0F2F_P_2): Likewise.
283 (VEX_LEN_0F51_P_1): Likewise.
284 (VEX_LEN_0F51_P_3): Likewise.
285 (VEX_LEN_0F52_P_1): Likewise.
286 (VEX_LEN_0F53_P_1): Likewise.
287 (VEX_LEN_0F58_P_1): Likewise.
288 (VEX_LEN_0F58_P_3): Likewise.
289 (VEX_LEN_0F59_P_1): Likewise.
290 (VEX_LEN_0F59_P_3): Likewise.
291 (VEX_LEN_0F5A_P_1): Likewise.
292 (VEX_LEN_0F5A_P_3): Likewise.
293 (VEX_LEN_0F5C_P_1): Likewise.
294 (VEX_LEN_0F5C_P_3): Likewise.
295 (VEX_LEN_0F5D_P_1): Likewise.
296 (VEX_LEN_0F5D_P_3): Likewise.
297 (VEX_LEN_0F5E_P_1): Likewise.
298 (VEX_LEN_0F5E_P_3): Likewise.
299 (VEX_LEN_0F5F_P_1): Likewise.
300 (VEX_LEN_0F5F_P_3): Likewise.
301 (VEX_LEN_0FC2_P_1): Likewise.
302 (VEX_LEN_0FC2_P_3): Likewise.
303 (VEX_LEN_0F3A0A_P_2): Likewise.
304 (VEX_LEN_0F3A0B_P_2): Likewise.
305 (VEX_W_0F10_P_0): Likewise.
306 (VEX_W_0F10_P_1): Likewise.
307 (VEX_W_0F10_P_2): Likewise.
308 (VEX_W_0F10_P_3): Likewise.
309 (VEX_W_0F11_P_0): Likewise.
310 (VEX_W_0F11_P_1): Likewise.
311 (VEX_W_0F11_P_2): Likewise.
312 (VEX_W_0F11_P_3): Likewise.
313 (VEX_W_0F12_P_0_M_0): Likewise.
314 (VEX_W_0F12_P_0_M_1): Likewise.
315 (VEX_W_0F12_P_1): Likewise.
316 (VEX_W_0F12_P_2): Likewise.
317 (VEX_W_0F12_P_3): Likewise.
318 (VEX_W_0F13_M_0): Likewise.
319 (VEX_W_0F14): Likewise.
320 (VEX_W_0F15): Likewise.
321 (VEX_W_0F16_P_0_M_0): Likewise.
322 (VEX_W_0F16_P_0_M_1): Likewise.
323 (VEX_W_0F16_P_1): Likewise.
324 (VEX_W_0F16_P_2): Likewise.
325 (VEX_W_0F17_M_0): Likewise.
326 (VEX_W_0F28): Likewise.
327 (VEX_W_0F29): Likewise.
328 (VEX_W_0F2B_M_0): Likewise.
329 (VEX_W_0F2E_P_0): Likewise.
330 (VEX_W_0F2E_P_2): Likewise.
331 (VEX_W_0F2F_P_0): Likewise.
332 (VEX_W_0F2F_P_2): Likewise.
333 (VEX_W_0F50_M_0): Likewise.
334 (VEX_W_0F51_P_0): Likewise.
335 (VEX_W_0F51_P_1): Likewise.
336 (VEX_W_0F51_P_2): Likewise.
337 (VEX_W_0F51_P_3): Likewise.
338 (VEX_W_0F52_P_0): Likewise.
339 (VEX_W_0F52_P_1): Likewise.
340 (VEX_W_0F53_P_0): Likewise.
341 (VEX_W_0F53_P_1): Likewise.
342 (VEX_W_0F58_P_0): Likewise.
343 (VEX_W_0F58_P_1): Likewise.
344 (VEX_W_0F58_P_2): Likewise.
345 (VEX_W_0F58_P_3): Likewise.
346 (VEX_W_0F59_P_0): Likewise.
347 (VEX_W_0F59_P_1): Likewise.
348 (VEX_W_0F59_P_2): Likewise.
349 (VEX_W_0F59_P_3): Likewise.
350 (VEX_W_0F5A_P_0): Likewise.
351 (VEX_W_0F5A_P_1): Likewise.
352 (VEX_W_0F5A_P_3): Likewise.
353 (VEX_W_0F5B_P_0): Likewise.
354 (VEX_W_0F5B_P_1): Likewise.
355 (VEX_W_0F5B_P_2): Likewise.
356 (VEX_W_0F5C_P_0): Likewise.
357 (VEX_W_0F5C_P_1): Likewise.
358 (VEX_W_0F5C_P_2): Likewise.
359 (VEX_W_0F5C_P_3): Likewise.
360 (VEX_W_0F5D_P_0): Likewise.
361 (VEX_W_0F5D_P_1): Likewise.
362 (VEX_W_0F5D_P_2): Likewise.
363 (VEX_W_0F5D_P_3): Likewise.
364 (VEX_W_0F5E_P_0): Likewise.
365 (VEX_W_0F5E_P_1): Likewise.
366 (VEX_W_0F5E_P_2): Likewise.
367 (VEX_W_0F5E_P_3): Likewise.
368 (VEX_W_0F5F_P_0): Likewise.
369 (VEX_W_0F5F_P_1): Likewise.
370 (VEX_W_0F5F_P_2): Likewise.
371 (VEX_W_0F5F_P_3): Likewise.
372 (VEX_W_0F60_P_2): Likewise.
373 (VEX_W_0F61_P_2): Likewise.
374 (VEX_W_0F62_P_2): Likewise.
375 (VEX_W_0F63_P_2): Likewise.
376 (VEX_W_0F64_P_2): Likewise.
377 (VEX_W_0F65_P_2): Likewise.
378 (VEX_W_0F66_P_2): Likewise.
379 (VEX_W_0F67_P_2): Likewise.
380 (VEX_W_0F68_P_2): Likewise.
381 (VEX_W_0F69_P_2): Likewise.
382 (VEX_W_0F6A_P_2): Likewise.
383 (VEX_W_0F6B_P_2): Likewise.
384 (VEX_W_0F6C_P_2): Likewise.
385 (VEX_W_0F6D_P_2): Likewise.
386 (VEX_W_0F6F_P_1): Likewise.
387 (VEX_W_0F6F_P_2): Likewise.
388 (VEX_W_0F70_P_1): Likewise.
389 (VEX_W_0F70_P_2): Likewise.
390 (VEX_W_0F70_P_3): Likewise.
391 (VEX_W_0F71_R_2_P_2): Likewise.
392 (VEX_W_0F71_R_4_P_2): Likewise.
393 (VEX_W_0F71_R_6_P_2): Likewise.
394 (VEX_W_0F72_R_2_P_2): Likewise.
395 (VEX_W_0F72_R_4_P_2): Likewise.
396 (VEX_W_0F72_R_6_P_2): Likewise.
397 (VEX_W_0F73_R_2_P_2): Likewise.
398 (VEX_W_0F73_R_3_P_2): Likewise.
399 (VEX_W_0F73_R_6_P_2): Likewise.
400 (VEX_W_0F73_R_7_P_2): Likewise.
401 (VEX_W_0F74_P_2): Likewise.
402 (VEX_W_0F75_P_2): Likewise.
403 (VEX_W_0F76_P_2): Likewise.
404 (VEX_W_0F77_P_0): Likewise.
405 (VEX_W_0F7C_P_2): Likewise.
406 (VEX_W_0F7C_P_3): Likewise.
407 (VEX_W_0F7D_P_2): Likewise.
408 (VEX_W_0F7D_P_3): Likewise.
409 (VEX_W_0F7E_P_1): Likewise.
410 (VEX_W_0F7F_P_1): Likewise.
411 (VEX_W_0F7F_P_2): Likewise.
412 (VEX_W_0FAE_R_2_M_0): Likewise.
413 (VEX_W_0FAE_R_3_M_0): Likewise.
414 (VEX_W_0FC2_P_0): Likewise.
415 (VEX_W_0FC2_P_1): Likewise.
416 (VEX_W_0FC2_P_2): Likewise.
417 (VEX_W_0FC2_P_3): Likewise.
418 (VEX_W_0FD0_P_2): Likewise.
419 (VEX_W_0FD0_P_3): Likewise.
420 (VEX_W_0FD1_P_2): Likewise.
421 (VEX_W_0FD2_P_2): Likewise.
422 (VEX_W_0FD3_P_2): Likewise.
423 (VEX_W_0FD4_P_2): Likewise.
424 (VEX_W_0FD5_P_2): Likewise.
425 (VEX_W_0FD6_P_2): Likewise.
426 (VEX_W_0FD7_P_2_M_1): Likewise.
427 (VEX_W_0FD8_P_2): Likewise.
428 (VEX_W_0FD9_P_2): Likewise.
429 (VEX_W_0FDA_P_2): Likewise.
430 (VEX_W_0FDB_P_2): Likewise.
431 (VEX_W_0FDC_P_2): Likewise.
432 (VEX_W_0FDD_P_2): Likewise.
433 (VEX_W_0FDE_P_2): Likewise.
434 (VEX_W_0FDF_P_2): Likewise.
435 (VEX_W_0FE0_P_2): Likewise.
436 (VEX_W_0FE1_P_2): Likewise.
437 (VEX_W_0FE2_P_2): Likewise.
438 (VEX_W_0FE3_P_2): Likewise.
439 (VEX_W_0FE4_P_2): Likewise.
440 (VEX_W_0FE5_P_2): Likewise.
441 (VEX_W_0FE6_P_1): Likewise.
442 (VEX_W_0FE6_P_2): Likewise.
443 (VEX_W_0FE6_P_3): Likewise.
444 (VEX_W_0FE7_P_2_M_0): Likewise.
445 (VEX_W_0FE8_P_2): Likewise.
446 (VEX_W_0FE9_P_2): Likewise.
447 (VEX_W_0FEA_P_2): Likewise.
448 (VEX_W_0FEB_P_2): Likewise.
449 (VEX_W_0FEC_P_2): Likewise.
450 (VEX_W_0FED_P_2): Likewise.
451 (VEX_W_0FEE_P_2): Likewise.
452 (VEX_W_0FEF_P_2): Likewise.
453 (VEX_W_0FF0_P_3_M_0): Likewise.
454 (VEX_W_0FF1_P_2): Likewise.
455 (VEX_W_0FF2_P_2): Likewise.
456 (VEX_W_0FF3_P_2): Likewise.
457 (VEX_W_0FF4_P_2): Likewise.
458 (VEX_W_0FF5_P_2): Likewise.
459 (VEX_W_0FF6_P_2): Likewise.
460 (VEX_W_0FF7_P_2): Likewise.
461 (VEX_W_0FF8_P_2): Likewise.
462 (VEX_W_0FF9_P_2): Likewise.
463 (VEX_W_0FFA_P_2): Likewise.
464 (VEX_W_0FFB_P_2): Likewise.
465 (VEX_W_0FFC_P_2): Likewise.
466 (VEX_W_0FFD_P_2): Likewise.
467 (VEX_W_0FFE_P_2): Likewise.
468 (VEX_W_0F3800_P_2): Likewise.
469 (VEX_W_0F3801_P_2): Likewise.
470 (VEX_W_0F3802_P_2): Likewise.
471 (VEX_W_0F3803_P_2): Likewise.
472 (VEX_W_0F3804_P_2): Likewise.
473 (VEX_W_0F3805_P_2): Likewise.
474 (VEX_W_0F3806_P_2): Likewise.
475 (VEX_W_0F3807_P_2): Likewise.
476 (VEX_W_0F3808_P_2): Likewise.
477 (VEX_W_0F3809_P_2): Likewise.
478 (VEX_W_0F380A_P_2): Likewise.
479 (VEX_W_0F380B_P_2): Likewise.
480 (VEX_W_0F3817_P_2): Likewise.
481 (VEX_W_0F381C_P_2): Likewise.
482 (VEX_W_0F381D_P_2): Likewise.
483 (VEX_W_0F381E_P_2): Likewise.
484 (VEX_W_0F3820_P_2): Likewise.
485 (VEX_W_0F3821_P_2): Likewise.
486 (VEX_W_0F3822_P_2): Likewise.
487 (VEX_W_0F3823_P_2): Likewise.
488 (VEX_W_0F3824_P_2): Likewise.
489 (VEX_W_0F3825_P_2): Likewise.
490 (VEX_W_0F3828_P_2): Likewise.
491 (VEX_W_0F3829_P_2): Likewise.
492 (VEX_W_0F382A_P_2_M_0): Likewise.
493 (VEX_W_0F382B_P_2): Likewise.
494 (VEX_W_0F3830_P_2): Likewise.
495 (VEX_W_0F3831_P_2): Likewise.
496 (VEX_W_0F3832_P_2): Likewise.
497 (VEX_W_0F3833_P_2): Likewise.
498 (VEX_W_0F3834_P_2): Likewise.
499 (VEX_W_0F3835_P_2): Likewise.
500 (VEX_W_0F3837_P_2): Likewise.
501 (VEX_W_0F3838_P_2): Likewise.
502 (VEX_W_0F3839_P_2): Likewise.
503 (VEX_W_0F383A_P_2): Likewise.
504 (VEX_W_0F383B_P_2): Likewise.
505 (VEX_W_0F383C_P_2): Likewise.
506 (VEX_W_0F383D_P_2): Likewise.
507 (VEX_W_0F383E_P_2): Likewise.
508 (VEX_W_0F383F_P_2): Likewise.
509 (VEX_W_0F3840_P_2): Likewise.
510 (VEX_W_0F3841_P_2): Likewise.
511 (VEX_W_0F38DB_P_2): Likewise.
512 (VEX_W_0F3A08_P_2): Likewise.
513 (VEX_W_0F3A09_P_2): Likewise.
514 (VEX_W_0F3A0A_P_2): Likewise.
515 (VEX_W_0F3A0B_P_2): Likewise.
516 (VEX_W_0F3A0C_P_2): Likewise.
517 (VEX_W_0F3A0D_P_2): Likewise.
518 (VEX_W_0F3A0E_P_2): Likewise.
519 (VEX_W_0F3A0F_P_2): Likewise.
520 (VEX_W_0F3A21_P_2): Likewise.
521 (VEX_W_0F3A40_P_2): Likewise.
522 (VEX_W_0F3A41_P_2): Likewise.
523 (VEX_W_0F3A42_P_2): Likewise.
524 (VEX_W_0F3A62_P_2): Likewise.
525 (VEX_W_0F3A63_P_2): Likewise.
526 (VEX_W_0F3ADF_P_2): Likewise.
527 (VEX_LEN_0F77_P_0): New.
528 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
529 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
530 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
531 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
532 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
533 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
534 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
535 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
536 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
537 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
538 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
539 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
540 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
541 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
542 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
543 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
544 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
545 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
546 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
547 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
548 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
549 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
550 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
551 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
552 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
553 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
554 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
555 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
556 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
557 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
558 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
559 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
560 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
561 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
562 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
563 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
564 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
565 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
566 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
567 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
568 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
569 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
570 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
571 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
572 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
573 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
574 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
575 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
576 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
577 (vex_table): Update VEX 0F28 and 0F29 entries.
578 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
579 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
580 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
581 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
582 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
583 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
584 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
585 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
586 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
587 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
588 VEX_LEN_0F3A0B_P_2 entries.
589 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
590 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
591 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
592 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
593 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
594 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
595 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
596 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
597 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
598 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
599 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
600 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
601 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
602 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
603 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
604 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
605 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
606 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
607 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
608 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
609 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
610 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
611 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
612 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
613 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
614 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
615 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
616 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
617 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
618 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
619 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
620 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
621 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
622 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
623 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
624 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
625 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
626 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
627 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
628 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
629 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
630 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
631 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
632 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
633 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
634 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
635 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
636 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
637 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
638 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
639 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
640 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
641 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
642 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
643 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
644 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
645 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
646 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
647 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
648 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
649 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
650 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
651 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
652 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
653 VEX_W_0F3ADF_P_2 entries.
654 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
655 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
656 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
658 2018-09-17 H.J. Lu <hongjiu.lu@intel.com>
660 * i386-opc.tbl (VexWIG): New.
661 Replace VexW=3 with VexWIG.
663 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
665 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
666 * i386-tbl.h: Regenerated.
668 2018-09-15 H.J. Lu <hongjiu.lu@intel.com>
671 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
672 VEX_LEN_0FD6_P_2 entries.
673 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
674 * i386-tbl.h: Regenerated.
676 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
679 * i386-opc.h (VEXWIG): New.
680 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
681 * i386-tbl.h: Regenerated.
683 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
686 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
687 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
688 * i386-dis.c (EXxEVexR64): New.
689 (evex_rounding_64_mode): Likewise.
690 (OP_Rounding): Handle evex_rounding_64_mode.
692 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
695 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
696 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
697 * i386-dis.c (Edqa): New.
698 (dqa_mode): Likewise.
699 (intel_operand_size): Handle dqa_mode as m_mode.
700 (OP_E_register): Handle dqa_mode as dq_mode.
701 (OP_E_memory): Set shift for dqa_mode based on address_mode.
703 2018-09-14 H.J. Lu <hongjiu.lu@intel.com>
705 * i386-dis.c (OP_E_memory): Reformat.
707 2018-09-14 Jan Beulich <jbeulich@suse.com>
709 * i386-opc.tbl (crc32): Fold byte and word forms.
710 * i386-tbl.h: Re-generate.
712 2018-09-13 H.J. Lu <hongjiu.lu@intel.com>
714 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
715 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
716 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
717 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
718 * i386-tbl.h: Regenerated.
720 2018-09-13 Jan Beulich <jbeulich@suse.com>
722 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
724 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
725 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
726 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
727 * i386-tbl.h: Re-generate.
729 2018-09-13 Jan Beulich <jbeulich@suse.com>
731 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
733 * i386-tbl.h: Re-generate.
735 2018-09-13 Jan Beulich <jbeulich@suse.com>
737 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
739 * i386-tbl.h: Re-generate.
741 2018-09-13 Jan Beulich <jbeulich@suse.com>
743 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
745 * i386-tbl.h: Re-generate.
747 2018-09-13 Jan Beulich <jbeulich@suse.com>
749 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
751 * i386-tbl.h: Re-generate.
753 2018-09-13 Jan Beulich <jbeulich@suse.com>
755 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
757 * i386-tbl.h: Re-generate.
759 2018-09-13 Jan Beulich <jbeulich@suse.com>
761 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
763 * i386-tbl.h: Re-generate.
765 2018-09-13 Jan Beulich <jbeulich@suse.com>
767 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
768 * i386-tbl.h: Re-generate.
770 2018-09-13 Jan Beulich <jbeulich@suse.com>
772 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
773 * i386-tbl.h: Re-generate.
775 2018-09-13 Jan Beulich <jbeulich@suse.com>
777 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
779 * i386-tbl.h: Re-generate.
781 2018-09-13 Jan Beulich <jbeulich@suse.com>
783 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
785 * i386-tbl.h: Re-generate.
787 2018-09-13 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
790 * i386-tbl.h: Re-generate.
792 2018-09-13 Jan Beulich <jbeulich@suse.com>
794 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
795 * i386-tbl.h: Re-generate.
797 2018-09-13 Jan Beulich <jbeulich@suse.com>
799 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
800 * i386-tbl.h: Re-generate.
802 2018-09-13 Jan Beulich <jbeulich@suse.com>
804 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
806 * i386-tbl.h: Re-generate.
808 2018-09-13 Jan Beulich <jbeulich@suse.com>
810 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
812 * i386-tbl.h: Re-generate.
814 2018-09-13 Jan Beulich <jbeulich@suse.com>
816 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
818 * i386-tbl.h: Re-generate.
820 2018-09-13 Jan Beulich <jbeulich@suse.com>
822 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
823 * i386-tbl.h: Re-generate.
825 2018-09-13 Jan Beulich <jbeulich@suse.com>
827 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
828 * i386-tbl.h: Re-generate.
830 2018-09-13 Jan Beulich <jbeulich@suse.com>
832 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
833 * i386-tbl.h: Re-generate.
835 2018-09-13 Jan Beulich <jbeulich@suse.com>
837 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
838 (vpbroadcastw, rdpid): Drop NoRex64.
839 * i386-tbl.h: Re-generate.
841 2018-09-13 Jan Beulich <jbeulich@suse.com>
843 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
844 store templates, adding D.
845 * i386-tbl.h: Re-generate.
847 2018-09-13 Jan Beulich <jbeulich@suse.com>
849 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
850 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
851 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
852 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
853 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
854 Fold load and store templates where possible, adding D. Drop
855 IgnoreSize where it was pointlessly present. Drop redundant
857 * i386-tbl.h: Re-generate.
859 2018-09-13 Jan Beulich <jbeulich@suse.com>
861 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
862 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
863 (intel_operand_size): Handle v_bndmk_mode.
864 (OP_E_memory): Likewise. Produce (bad) when also riprel.
866 2018-09-08 John Darrington <john@darrington.wattle.id.au>
868 * disassemble.c (ARCH_s12z): Define if ARCH_all.
870 2018-08-31 Kito Cheng <kito@andestech.com>
872 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
873 compressed floating point instructions.
875 2018-08-30 Kito Cheng <kito@andestech.com>
877 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
878 riscv_opcode.xlen_requirement.
879 * riscv-opc.c (riscv_opcodes): Update for struct change.
881 2018-08-29 Martin Aberg <maberg@gaisler.com>
883 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
884 psr (PWRPSR) instruction.
886 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
888 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
890 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
892 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
894 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
896 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
897 loongson3a as an alias of gs464 for compatibility.
898 * mips-opc.c (mips_opcodes): Change Comments.
900 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
902 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
904 (print_mips_disassembler_options): Document -M loongson-ext.
905 * mips-opc.c (LEXT2): New macro.
906 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
908 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
910 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
912 (parse_mips_ase_option): Handle -M loongson-ext option.
913 (print_mips_disassembler_options): Document -M loongson-ext.
914 * mips-opc.c (IL3A): Delete.
915 * mips-opc.c (LEXT): New macro.
916 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
919 2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
921 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
923 (parse_mips_ase_option): Handle -M loongson-cam option.
924 (print_mips_disassembler_options): Document -M loongson-cam.
925 * mips-opc.c (LCAM): New macro.
926 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
929 2018-08-21 Alan Modra <amodra@gmail.com>
931 * ppc-dis.c (operand_value_powerpc): Init "invalid".
932 (skip_optional_operands): Count optional operands, and update
933 ppc_optional_operand_value call.
934 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
935 (extract_vlensi): Likewise.
936 (extract_fxm): Return default value for missing optional operand.
937 (extract_ls, extract_raq, extract_tbr): Likewise.
938 (insert_sxl, extract_sxl): New functions.
939 (insert_esync, extract_esync): Remove Power9 handling and simplify.
940 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
941 flag and extra entry.
942 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
945 2018-08-20 Alan Modra <amodra@gmail.com>
947 * sh-opc.h (MASK): Simplify.
949 2018-08-18 John Darrington <john@darrington.wattle.id.au>
951 * s12z-dis.c (bm_decode): Deal with cases where the mode is
952 BM_RESERVED0 or BM_RESERVED1
953 (bm_rel_decode, bm_n_bytes): Ditto.
955 2018-08-18 John Darrington <john@darrington.wattle.id.au>
959 2018-08-14 H.J. Lu <hongjiu.lu@intel.com>
961 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
962 address with the addr32 prefix and without base nor index
965 2018-08-11 H.J. Lu <hongjiu.lu@intel.com>
967 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
968 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
969 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
970 (cpu_flags): Add CpuCMOV and CpuFXSR.
971 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
972 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
973 * i386-init.h: Regenerated.
974 * i386-tbl.h: Likewise.
976 2018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
978 * arc-regs.h: Update auxiliary registers.
980 2018-08-06 Jan Beulich <jbeulich@suse.com>
982 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
983 (RegIP, RegIZ): Define.
984 * i386-reg.tbl: Adjust comments.
985 (rip): Use Qword instead of BaseIndex. Use RegIP.
986 (eip): Use Dword instead of BaseIndex. Use RegIP.
987 (riz): Add Qword. Use RegIZ.
988 (eiz): Add Dword. Use RegIZ.
989 * i386-tbl.h: Re-generate.
991 2018-08-03 Jan Beulich <jbeulich@suse.com>
993 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
994 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
995 vpmovzxdq, vpmovzxwd): Remove NoRex64.
996 * i386-tbl.h: Re-generate.
998 2018-08-03 Jan Beulich <jbeulich@suse.com>
1000 * i386-gen.c (operand_types): Remove Mem field.
1001 * i386-opc.h (union i386_operand_type): Remove mem field.
1002 * i386-init.h, i386-tbl.h: Re-generate.
1004 2018-08-01 Alan Modra <amodra@gmail.com>
1006 * po/POTFILES.in: Regenerate.
1008 2018-07-31 Nick Clifton <nickc@redhat.com>
1010 * po/sv.po: Updated Swedish translation.
1012 2018-07-31 Jan Beulich <jbeulich@suse.com>
1014 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1015 * i386-init.h, i386-tbl.h: Re-generate.
1017 2018-07-31 Jan Beulich <jbeulich@suse.com>
1019 * i386-opc.h (ZEROING_MASKING) Rename to ...
1020 (DYNAMIC_MASKING): ... this. Adjust comment.
1021 * i386-opc.tbl (MaskingMorZ): Define.
1022 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1023 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1024 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1025 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1026 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1027 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1028 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1029 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1030 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1032 2018-07-31 Jan Beulich <jbeulich@suse.com>
1034 * i386-opc.tbl: Use element rather than vector size for AVX512*
1035 scatter/gather insns.
1036 * i386-tbl.h: Re-generate.
1038 2018-07-31 Jan Beulich <jbeulich@suse.com>
1040 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1041 (cpu_flags): Drop CpuVREX.
1042 * i386-opc.h (CpuVREX): Delete.
1043 (union i386_cpu_flags): Remove cpuvrex.
1044 * i386-init.h, i386-tbl.h: Re-generate.
1046 2018-07-30 Jim Wilson <jimw@sifive.com>
1048 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1050 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1052 2018-07-30 Andrew Jenner <andrew@codesourcery.com>
1054 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1055 * Makefile.in: Regenerated.
1056 * configure.ac: Add C-SKY.
1057 * configure: Regenerated.
1058 * csky-dis.c: New file.
1059 * csky-opc.h: New file.
1060 * disassemble.c (ARCH_csky): Define.
1061 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1062 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1064 2018-07-27 Alan Modra <amodra@gmail.com>
1066 * ppc-opc.c (insert_sprbat): Correct function parameter and
1068 (extract_sprbat): Likewise, variable too.
1070 2018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1071 Alan Modra <amodra@gmail.com>
1073 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1074 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1075 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1076 support disjointed BAT.
1077 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1078 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1079 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1081 2018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1082 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1084 * i386-gen.c (adjust_broadcast_modifier): New function.
1085 (process_i386_opcode_modifier): Add an argument for operands.
1086 Adjust the Broadcast value based on operands.
1087 (output_i386_opcode): Pass operand_types to
1088 process_i386_opcode_modifier.
1089 (process_i386_opcodes): Pass NULL as operands to
1090 process_i386_opcode_modifier.
1091 * i386-opc.h (BYTE_BROADCAST): New.
1092 (WORD_BROADCAST): Likewise.
1093 (DWORD_BROADCAST): Likewise.
1094 (QWORD_BROADCAST): Likewise.
1095 (i386_opcode_modifier): Expand broadcast to 3 bits.
1096 * i386-tbl.h: Regenerated.
1098 2018-07-24 Alan Modra <amodra@gmail.com>
1101 * or1k-desc.h: Regenerate.
1103 2018-07-24 Jan Beulich <jbeulich@suse.com>
1105 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1106 vcvtusi2ss, and vcvtusi2sd.
1107 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1108 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1109 * i386-tbl.h: Re-generate.
1111 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1113 * arc-opc.c (extract_w6): Fix extending the sign.
1115 2018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1117 * arc-tbl.h (vewt): Allow it for ARC EM family.
1119 2018-07-23 Alan Modra <amodra@gmail.com>
1122 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1123 opcode variants for mtspr/mfspr encodings.
1125 2018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1126 Maciej W. Rozycki <macro@mips.com>
1128 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1129 loongson3a descriptors.
1130 (parse_mips_ase_option): Handle -M loongson-mmi option.
1131 (print_mips_disassembler_options): Document -M loongson-mmi.
1132 * mips-opc.c (LMMI): New macro.
1133 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1136 2018-07-19 Jan Beulich <jbeulich@suse.com>
1138 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1139 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1140 IgnoreSize and [XYZ]MMword where applicable.
1141 * i386-tbl.h: Re-generate.
1143 2018-07-19 Jan Beulich <jbeulich@suse.com>
1145 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1146 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1147 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1148 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1149 * i386-tbl.h: Re-generate.
1151 2018-07-19 Jan Beulich <jbeulich@suse.com>
1153 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1154 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1155 VPCLMULQDQ templates into their respective AVX512VL counterparts
1156 where possible, using Disp8ShiftVL and CheckRegSize instead of
1157 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1158 * i386-tbl.h: Re-generate.
1160 2018-07-19 Jan Beulich <jbeulich@suse.com>
1162 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1163 AVX512VL counterparts where possible, using Disp8ShiftVL and
1164 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1165 IgnoreSize) as appropriate.
1166 * i386-tbl.h: Re-generate.
1168 2018-07-19 Jan Beulich <jbeulich@suse.com>
1170 * i386-opc.tbl: Fold AVX512BW templates into their respective
1171 AVX512VL counterparts where possible, using Disp8ShiftVL and
1172 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1173 IgnoreSize) as appropriate.
1174 * i386-tbl.h: Re-generate.
1176 2018-07-19 Jan Beulich <jbeulich@suse.com>
1178 * i386-opc.tbl: Fold AVX512CD templates into their respective
1179 AVX512VL counterparts where possible, using Disp8ShiftVL and
1180 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1181 IgnoreSize) as appropriate.
1182 * i386-tbl.h: Re-generate.
1184 2018-07-19 Jan Beulich <jbeulich@suse.com>
1186 * i386-opc.h (DISP8_SHIFT_VL): New.
1187 * i386-opc.tbl (Disp8ShiftVL): Define.
1188 (various): Fold AVX512VL templates into their respective
1189 AVX512F counterparts where possible, using Disp8ShiftVL and
1190 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1191 IgnoreSize) as appropriate.
1192 * i386-tbl.h: Re-generate.
1194 2018-07-19 Jan Beulich <jbeulich@suse.com>
1196 * Makefile.am: Change dependencies and rule for
1197 $(srcdir)/i386-init.h.
1198 * Makefile.in: Re-generate.
1199 * i386-gen.c (process_i386_opcodes): New local variable
1200 "marker". Drop opening of input file. Recognize marker and line
1202 * i386-opc.tbl (OPCODE_I386_H): Define.
1203 (i386-opc.h): Include it.
1206 2018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1209 * i386-opc.h (Byte): Update comments.
1215 (Xmmword): Likewise.
1216 (Ymmword): Likewise.
1217 (Zmmword): Likewise.
1218 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1220 * i386-tbl.h: Regenerated.
1222 2018-07-12 Sudakshina Das <sudi.das@arm.com>
1224 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1225 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1226 * aarch64-asm-2.c: Regenerate.
1227 * aarch64-dis-2.c: Regenerate.
1228 * aarch64-opc-2.c: Regenerate.
1230 2018-07-12 Tamar Christina <tamar.christina@arm.com>
1233 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1234 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1235 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1236 sqdmulh, sqrdmulh): Use Em16.
1238 2018-07-11 Sudakshina Das <sudi.das@arm.com>
1240 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1241 csdb together with them.
1242 (thumb32_opcodes): Likewise.
1244 2018-07-11 Jan Beulich <jbeulich@suse.com>
1246 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1247 requiring 32-bit registers as operands 2 and 3. Improve
1249 (mwait, mwaitx): Fold templates. Improve comments.
1250 OPERAND_TYPE_INOUTPORTREG.
1251 * i386-tbl.h: Re-generate.
1253 2018-07-11 Jan Beulich <jbeulich@suse.com>
1255 * i386-gen.c (operand_type_init): Remove
1256 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1257 OPERAND_TYPE_INOUTPORTREG.
1258 * i386-init.h: Re-generate.
1260 2018-07-11 Jan Beulich <jbeulich@suse.com>
1262 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1263 (wrssq, wrussq): Add Qword.
1264 * i386-tbl.h: Re-generate.
1266 2018-07-11 Jan Beulich <jbeulich@suse.com>
1268 * i386-opc.h: Rename OTMax to OTNum.
1269 (OTNumOfUints): Adjust calculation.
1270 (OTUnused): Directly alias to OTNum.
1272 2018-07-09 Maciej W. Rozycki <macro@mips.com>
1274 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1276 (lea_reg_xys): Likewise.
1277 (print_insn_loop_primitive): Rename `reg' local variable to
1280 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1283 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1285 2018-07-06 Tamar Christina <tamar.christina@arm.com>
1288 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1289 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1291 2018-07-02 Maciej W. Rozycki <macro@mips.com>
1294 * mips-dis.c (mips_option_arg_t): New enumeration.
1295 (mips_options): New variable.
1296 (disassembler_options_mips): New function.
1297 (print_mips_disassembler_options): Reimplement in terms of
1298 `disassembler_options_mips'.
1299 * arm-dis.c (disassembler_options_arm): Adapt to using the
1300 `disasm_options_and_args_t' structure.
1301 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1302 * s390-dis.c (disassembler_options_s390): Likewise.
1304 2018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1306 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1308 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1309 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1310 * testsuite/ld-arm/tls-longplt.d: Likewise.
1312 2018-06-29 Tamar Christina <tamar.christina@arm.com>
1315 * aarch64-asm-2.c: Regenerate.
1316 * aarch64-dis-2.c: Likewise.
1317 * aarch64-opc-2.c: Likewise.
1318 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1319 * aarch64-opc.c (operand_general_constraint_met_p,
1320 aarch64_print_operand): Likewise.
1321 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1322 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1324 (AARCH64_OPERANDS): Add Em2.
1326 2018-06-26 Nick Clifton <nickc@redhat.com>
1328 * po/uk.po: Updated Ukranian translation.
1329 * po/de.po: Updated German translation.
1330 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1332 2018-06-26 Nick Clifton <nickc@redhat.com>
1334 * nfp-dis.c: Fix spelling mistake.
1336 2018-06-24 Nick Clifton <nickc@redhat.com>
1338 * configure: Regenerate.
1339 * po/opcodes.pot: Regenerate.
1341 2018-06-24 Nick Clifton <nickc@redhat.com>
1343 2.31 branch created.
1345 2018-06-19 Tamar Christina <tamar.christina@arm.com>
1347 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1348 * aarch64-asm-2.c: Regenerate.
1349 * aarch64-dis-2.c: Likewise.
1351 2018-06-21 Maciej W. Rozycki <macro@mips.com>
1353 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1354 `-M ginv' option description.
1356 2018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1359 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1362 2018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1364 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1365 * configure.ac: Remove AC_PREREQ.
1366 * Makefile.in: Re-generate.
1367 * aclocal.m4: Re-generate.
1368 * configure: Re-generate.
1370 2018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1372 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1373 mips64r6 descriptors.
1374 (parse_mips_ase_option): Handle -Mginv option.
1375 (print_mips_disassembler_options): Document -Mginv.
1376 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1378 (mips_opcodes): Define ginvi and ginvt.
1380 2018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1381 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1383 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1384 * mips-opc.c (CRC, CRC64): New macros.
1385 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1386 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1389 2018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1392 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1393 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1395 2018-06-06 Alan Modra <amodra@gmail.com>
1397 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1398 setjmp. Move init for some other vars later too.
1400 2018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1402 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1403 (dis_private): Add new fields for property section tracking.
1404 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1405 (xtensa_instruction_fits): New functions.
1406 (fetch_data): Bump minimal fetch size to 4.
1407 (print_insn_xtensa): Make struct dis_private static.
1408 Load and prepare property table on section change.
1409 Don't disassemble literals. Don't disassemble instructions that
1410 cross property table boundaries.
1412 2018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1414 * configure: Regenerated.
1416 2018-06-01 Jan Beulich <jbeulich@suse.com>
1418 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1419 * i386-tbl.h: Re-generate.
1421 2018-06-01 Jan Beulich <jbeulich@suse.com>
1423 * i386-opc.tbl (sldt, str): Add NoRex64.
1424 * i386-tbl.h: Re-generate.
1426 2018-06-01 Jan Beulich <jbeulich@suse.com>
1428 * i386-opc.tbl (invpcid): Add Oword.
1429 * i386-tbl.h: Re-generate.
1431 2018-06-01 Alan Modra <amodra@gmail.com>
1433 * sysdep.h (_bfd_error_handler): Don't declare.
1434 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1435 * rl78-decode.opc: Likewise.
1436 * msp430-decode.c: Regenerate.
1437 * rl78-decode.c: Regenerate.
1439 2018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1441 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1442 * i386-init.h : Regenerated.
1444 2018-05-25 Alan Modra <amodra@gmail.com>
1446 * Makefile.in: Regenerate.
1447 * po/POTFILES.in: Regenerate.
1449 2018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1451 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1452 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1453 (insert_bab, extract_bab, insert_btab, extract_btab,
1454 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1455 (BAT, BBA VBA RBS XB6S): Delete macros.
1456 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1457 (BB, BD, RBX, XC6): Update for new macros.
1458 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1459 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1460 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1461 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1463 2018-05-18 John Darrington <john@darrington.wattle.id.au>
1465 * Makefile.am: Add support for s12z architecture.
1466 * configure.ac: Likewise.
1467 * disassemble.c: Likewise.
1468 * disassemble.h: Likewise.
1469 * Makefile.in: Regenerate.
1470 * configure: Regenerate.
1471 * s12z-dis.c: New file.
1474 2018-05-18 Alan Modra <amodra@gmail.com>
1476 * nfp-dis.c: Don't #include libbfd.h.
1477 (init_nfp3200_priv): Use bfd_get_section_contents.
1478 (nit_nfp6000_mecsr_sec): Likewise.
1480 2018-05-17 Nick Clifton <nickc@redhat.com>
1482 * po/zh_CN.po: Updated simplified Chinese translation.
1484 2018-05-16 Tamar Christina <tamar.christina@arm.com>
1487 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1488 * aarch64-dis-2.c: Regenerate.
1490 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1493 * aarch64-asm.c (opintl.h): Include.
1494 (aarch64_ins_sysreg): Enforce read/write constraints.
1495 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1496 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1497 (F_REG_READ, F_REG_WRITE): New.
1498 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1499 AARCH64_OPND_SYSREG.
1500 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1501 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1502 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1503 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1504 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1505 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1506 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1507 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1508 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1509 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1510 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1511 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1512 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1513 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1514 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1515 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1516 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1518 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1521 * aarch64-dis.c (no_notes: New.
1522 (parse_aarch64_dis_option): Support notes.
1523 (aarch64_decode_insn, print_operands): Likewise.
1524 (print_aarch64_disassembler_options): Document notes.
1525 * aarch64-opc.c (aarch64_print_operand): Support notes.
1527 2018-05-15 Tamar Christina <tamar.christina@arm.com>
1530 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1531 and take error struct.
1532 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1533 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1534 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1535 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1536 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1537 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1538 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1539 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1540 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1541 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1542 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1543 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1544 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1545 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1546 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1547 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1548 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1549 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1550 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1551 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1552 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1553 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1554 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1555 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1556 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1557 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1558 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1559 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1560 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1561 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1562 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1563 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1564 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1565 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1566 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1567 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1568 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1569 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1570 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1571 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1572 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1573 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1574 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1575 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1576 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1577 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1578 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1579 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1580 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1581 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1582 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1583 (determine_disassembling_preference, aarch64_decode_insn,
1584 print_insn_aarch64_word, print_insn_data): Take errors struct.
1585 (print_insn_aarch64): Use errors.
1586 * aarch64-asm-2.c: Regenerate.
1587 * aarch64-dis-2.c: Regenerate.
1588 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1589 boolean in aarch64_insert_operan.
1590 (print_operand_extractor): Likewise.
1591 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1593 2018-05-15 Francois H. Theron <francois.theron@netronome.com>
1595 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1597 2018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1599 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1601 2018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1603 * cr16-opc.c (cr16_instruction): Comment typo fix.
1604 * hppa-dis.c (print_insn_hppa): Likewise.
1606 2018-05-08 Jim Wilson <jimw@sifive.com>
1608 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1609 (match_c_slli64, match_srxi_as_c_srxi): New.
1610 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1611 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1612 <c.slli, c.srli, c.srai>: Use match_s_slli.
1613 <c.slli64, c.srli64, c.srai64>: New.
1615 2018-05-08 Alan Modra <amodra@gmail.com>
1617 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1618 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1619 partition opcode space for index lookup.
1621 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1623 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1624 <insn_length>: ...with this. Update usage.
1625 Remove duplicate call to *info->memory_error_func.
1627 2018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1628 H.J. Lu <hongjiu.lu@intel.com>
1630 * i386-dis.c (Gva): New.
1631 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1632 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1633 (prefix_table): New instructions (see prefix above).
1634 (mod_table): New instructions (see prefix above).
1635 (OP_G): Handle va_mode.
1636 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1637 CPU_MOVDIR64B_FLAGS.
1638 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1639 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1640 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1641 * i386-opc.tbl: Add movidir{i,64b}.
1642 * i386-init.h: Regenerated.
1643 * i386-tbl.h: Likewise.
1645 2018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1647 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1649 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1650 (AddrPrefixOpReg): This.
1651 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1652 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1654 2018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1656 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1657 (vle_num_opcodes): Likewise.
1658 (spe2_num_opcodes): Likewise.
1659 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1660 initialization loop.
1661 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1662 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1665 2018-05-01 Tamar Christina <tamar.christina@arm.com>
1667 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1669 2018-04-30 Francois H. Theron <francois.theron@netronome.com>
1671 Makefile.am: Added nfp-dis.c.
1672 configure.ac: Added bfd_nfp_arch.
1673 disassemble.h: Added print_insn_nfp prototype.
1674 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1675 nfp-dis.c: New, for NFP support.
1676 po/POTFILES.in: Added nfp-dis.c to the list.
1677 Makefile.in: Regenerate.
1678 configure: Regenerate.
1680 2018-04-26 Jan Beulich <jbeulich@suse.com>
1682 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1683 templates into their base ones.
1684 * i386-tlb.h: Re-generate.
1686 2018-04-26 Jan Beulich <jbeulich@suse.com>
1688 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1689 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1690 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1691 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1692 * i386-init.h: Re-generate.
1694 2018-04-26 Jan Beulich <jbeulich@suse.com>
1696 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1697 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1698 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1699 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1701 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1703 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1705 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1706 cpuregzmm, and cpuregmask.
1707 * i386-init.h: Re-generate.
1708 * i386-tbl.h: Re-generate.
1710 2018-04-26 Jan Beulich <jbeulich@suse.com>
1712 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1713 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1714 * i386-init.h: Re-generate.
1716 2018-04-26 Jan Beulich <jbeulich@suse.com>
1718 * i386-gen.c (VexImmExt): Delete.
1719 * i386-opc.h (VexImmExt, veximmext): Delete.
1720 * i386-opc.tbl: Drop all VexImmExt uses.
1721 * i386-tlb.h: Re-generate.
1723 2018-04-25 Jan Beulich <jbeulich@suse.com>
1725 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1726 register-only forms.
1727 * i386-tlb.h: Re-generate.
1729 2018-04-25 Tamar Christina <tamar.christina@arm.com>
1731 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1733 2018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1735 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1737 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1738 (cpu_flags): Add CpuCLDEMOTE.
1739 * i386-init.h: Regenerate.
1740 * i386-opc.h (enum): Add CpuCLDEMOTE,
1741 (i386_cpu_flags): Add cpucldemote.
1742 * i386-opc.tbl: Add cldemote.
1743 * i386-tbl.h: Regenerate.
1745 2018-04-16 Alan Modra <amodra@gmail.com>
1747 * Makefile.am: Remove sh5 and sh64 support.
1748 * configure.ac: Likewise.
1749 * disassemble.c: Likewise.
1750 * disassemble.h: Likewise.
1751 * sh-dis.c: Likewise.
1752 * sh64-dis.c: Delete.
1753 * sh64-opc.c: Delete.
1754 * sh64-opc.h: Delete.
1755 * Makefile.in: Regenerate.
1756 * configure: Regenerate.
1757 * po/POTFILES.in: Regenerate.
1759 2018-04-16 Alan Modra <amodra@gmail.com>
1761 * Makefile.am: Remove w65 support.
1762 * configure.ac: Likewise.
1763 * disassemble.c: Likewise.
1764 * disassemble.h: Likewise.
1765 * w65-dis.c: Delete.
1766 * w65-opc.h: Delete.
1767 * Makefile.in: Regenerate.
1768 * configure: Regenerate.
1769 * po/POTFILES.in: Regenerate.
1771 2018-04-16 Alan Modra <amodra@gmail.com>
1773 * configure.ac: Remove we32k support.
1774 * configure: Regenerate.
1776 2018-04-16 Alan Modra <amodra@gmail.com>
1778 * Makefile.am: Remove m88k support.
1779 * configure.ac: Likewise.
1780 * disassemble.c: Likewise.
1781 * disassemble.h: Likewise.
1782 * m88k-dis.c: Delete.
1783 * Makefile.in: Regenerate.
1784 * configure: Regenerate.
1785 * po/POTFILES.in: Regenerate.
1787 2018-04-16 Alan Modra <amodra@gmail.com>
1789 * Makefile.am: Remove i370 support.
1790 * configure.ac: Likewise.
1791 * disassemble.c: Likewise.
1792 * disassemble.h: Likewise.
1793 * i370-dis.c: Delete.
1794 * i370-opc.c: Delete.
1795 * Makefile.in: Regenerate.
1796 * configure: Regenerate.
1797 * po/POTFILES.in: Regenerate.
1799 2018-04-16 Alan Modra <amodra@gmail.com>
1801 * Makefile.am: Remove h8500 support.
1802 * configure.ac: Likewise.
1803 * disassemble.c: Likewise.
1804 * disassemble.h: Likewise.
1805 * h8500-dis.c: Delete.
1806 * h8500-opc.h: Delete.
1807 * Makefile.in: Regenerate.
1808 * configure: Regenerate.
1809 * po/POTFILES.in: Regenerate.
1811 2018-04-16 Alan Modra <amodra@gmail.com>
1813 * configure.ac: Remove tahoe support.
1814 * configure: Regenerate.
1816 2018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1818 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1820 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1822 * i386-tbl.h: Regenerated.
1824 2018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1826 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1827 PREFIX_MOD_1_0FAE_REG_6.
1829 (OP_E_register): Use va_mode.
1830 * i386-dis-evex.h (prefix_table):
1831 New instructions (see prefixes above).
1832 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1833 (cpu_flags): Likewise.
1834 * i386-opc.h (enum): Likewise.
1835 (i386_cpu_flags): Likewise.
1836 * i386-opc.tbl: Add umonitor, umwait, tpause.
1837 * i386-init.h: Regenerate.
1838 * i386-tbl.h: Likewise.
1840 2018-04-11 Alan Modra <amodra@gmail.com>
1842 * opcodes/i860-dis.c: Delete.
1843 * opcodes/i960-dis.c: Delete.
1844 * Makefile.am: Remove i860 and i960 support.
1845 * configure.ac: Likewise.
1846 * disassemble.c: Likewise.
1847 * disassemble.h: Likewise.
1848 * Makefile.in: Regenerate.
1849 * configure: Regenerate.
1850 * po/POTFILES.in: Regenerate.
1852 2018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1855 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1857 (print_insn): Clear vex instead of vex.evex.
1859 2018-04-04 Nick Clifton <nickc@redhat.com>
1861 * po/es.po: Updated Spanish translation.
1863 2018-03-28 Jan Beulich <jbeulich@suse.com>
1865 * i386-gen.c (opcode_modifiers): Delete VecESize.
1866 * i386-opc.h (VecESize): Delete.
1867 (struct i386_opcode_modifier): Delete vecesize.
1868 * i386-opc.tbl: Drop VecESize.
1869 * i386-tlb.h: Re-generate.
1871 2018-03-28 Jan Beulich <jbeulich@suse.com>
1873 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1874 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1875 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1876 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1877 * i386-tlb.h: Re-generate.
1879 2018-03-28 Jan Beulich <jbeulich@suse.com>
1881 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1883 * i386-tlb.h: Re-generate.
1885 2018-03-28 Jan Beulich <jbeulich@suse.com>
1887 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1888 (vex_len_table): Drop Y for vcvt*2si.
1889 (putop): Replace plain 'Y' handling by abort().
1891 2018-03-28 Nick Clifton <nickc@redhat.com>
1894 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1895 instructions with only a base address register.
1896 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1897 handle AARHC64_OPND_SVE_ADDR_R.
1898 (aarch64_print_operand): Likewise.
1899 * aarch64-asm-2.c: Regenerate.
1900 * aarch64_dis-2.c: Regenerate.
1901 * aarch64-opc-2.c: Regenerate.
1903 2018-03-22 Jan Beulich <jbeulich@suse.com>
1905 * i386-opc.tbl: Drop VecESize from register only insn forms and
1906 memory forms not allowing broadcast.
1907 * i386-tlb.h: Re-generate.
1909 2018-03-22 Jan Beulich <jbeulich@suse.com>
1911 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1912 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1913 sha256*): Drop Disp<N>.
1915 2018-03-22 Jan Beulich <jbeulich@suse.com>
1917 * i386-dis.c (EbndS, bnd_swap_mode): New.
1918 (prefix_table): Use EbndS.
1919 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1920 * i386-opc.tbl (bndmov): Move misplaced Load.
1921 * i386-tlb.h: Re-generate.
1923 2018-03-22 Jan Beulich <jbeulich@suse.com>
1925 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1926 templates allowing memory operands and folded ones for register
1928 * i386-tlb.h: Re-generate.
1930 2018-03-22 Jan Beulich <jbeulich@suse.com>
1932 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1933 256-bit templates. Drop redundant leftover Disp<N>.
1934 * i386-tlb.h: Re-generate.
1936 2018-03-14 Kito Cheng <kito.cheng@gmail.com>
1938 * riscv-opc.c (riscv_insn_types): New.
1940 2018-03-13 Nick Clifton <nickc@redhat.com>
1942 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1944 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1946 * i386-opc.tbl: Add Optimize to clr.
1947 * i386-tbl.h: Regenerated.
1949 2018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1951 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1952 * i386-opc.h (OldGcc): Removed.
1953 (i386_opcode_modifier): Remove oldgcc.
1954 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1955 instructions for old (<= 2.8.1) versions of gcc.
1956 * i386-tbl.h: Regenerated.
1958 2018-03-08 Jan Beulich <jbeulich@suse.com>
1960 * i386-opc.h (EVEXDYN): New.
1961 * i386-opc.tbl: Fold various AVX512VL templates.
1962 * i386-tlb.h: Re-generate.
1964 2018-03-08 Jan Beulich <jbeulich@suse.com>
1966 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1967 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1968 vpexpandd, vpexpandq): Fold AFX512VF templates.
1969 * i386-tlb.h: Re-generate.
1971 2018-03-08 Jan Beulich <jbeulich@suse.com>
1973 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1974 Fold 128- and 256-bit VEX-encoded templates.
1975 * i386-tlb.h: Re-generate.
1977 2018-03-08 Jan Beulich <jbeulich@suse.com>
1979 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1980 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1981 vpexpandd, vpexpandq): Fold AVX512F templates.
1982 * i386-tlb.h: Re-generate.
1984 2018-03-08 Jan Beulich <jbeulich@suse.com>
1986 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1987 64-bit templates. Drop Disp<N>.
1988 * i386-tlb.h: Re-generate.
1990 2018-03-08 Jan Beulich <jbeulich@suse.com>
1992 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1993 and 256-bit templates.
1994 * i386-tlb.h: Re-generate.
1996 2018-03-08 Jan Beulich <jbeulich@suse.com>
1998 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1999 * i386-tlb.h: Re-generate.
2001 2018-03-08 Jan Beulich <jbeulich@suse.com>
2003 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2005 * i386-tlb.h: Re-generate.
2007 2018-03-08 Jan Beulich <jbeulich@suse.com>
2009 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2010 * i386-tlb.h: Re-generate.
2012 2018-03-08 Jan Beulich <jbeulich@suse.com>
2014 * i386-gen.c (opcode_modifiers): Delete FloatD.
2015 * i386-opc.h (FloatD): Delete.
2016 (struct i386_opcode_modifier): Delete floatd.
2017 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2019 * i386-tlb.h: Re-generate.
2021 2018-03-08 Jan Beulich <jbeulich@suse.com>
2023 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2025 2018-03-08 Jan Beulich <jbeulich@suse.com>
2027 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2028 * i386-tlb.h: Re-generate.
2030 2018-03-08 Jan Beulich <jbeulich@suse.com>
2032 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2034 * i386-tlb.h: Re-generate.
2036 2018-03-07 Alan Modra <amodra@gmail.com>
2038 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2040 * disassemble.h (print_insn_rs6000): Delete.
2041 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2042 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2043 (print_insn_rs6000): Delete.
2045 2018-03-03 Alan Modra <amodra@gmail.com>
2047 * sysdep.h (opcodes_error_handler): Define.
2048 (_bfd_error_handler): Declare.
2049 * Makefile.am: Remove stray #.
2050 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2052 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2053 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2054 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2055 opcodes_error_handler to print errors. Standardize error messages.
2056 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2057 and include opintl.h.
2058 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2059 * i386-gen.c: Standardize error messages.
2060 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2061 * Makefile.in: Regenerate.
2062 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2063 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2064 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2065 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2066 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2067 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2068 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2069 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2070 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2071 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2072 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2073 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2074 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2076 2018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2078 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2079 vpsub[bwdq] instructions.
2080 * i386-tbl.h: Regenerated.
2082 2018-03-01 Alan Modra <amodra@gmail.com>
2084 * configure.ac (ALL_LINGUAS): Sort.
2085 * configure: Regenerate.
2087 2018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2089 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2090 macro by assignements.
2092 2018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2095 * i386-gen.c (opcode_modifiers): Add Optimize.
2096 * i386-opc.h (Optimize): New enum.
2097 (i386_opcode_modifier): Add optimize.
2098 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2099 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2100 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2101 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2102 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2104 * i386-tbl.h: Regenerated.
2106 2018-02-26 Alan Modra <amodra@gmail.com>
2108 * crx-dis.c (getregliststring): Allocate a large enough buffer
2109 to silence false positive gcc8 warning.
2111 2018-02-22 Shea Levy <shea@shealevy.com>
2113 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2115 2018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2117 * i386-opc.tbl: Add {rex},
2118 * i386-tbl.h: Regenerated.
2120 2018-02-20 Maciej W. Rozycki <macro@mips.com>
2122 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2123 (mips16_opcodes): Replace `M' with `m' for "restore".
2125 2018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2127 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2129 2018-02-13 Maciej W. Rozycki <macro@mips.com>
2131 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2132 variable to `function_index'.
2134 2018-02-13 Nick Clifton <nickc@redhat.com>
2137 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2138 about truncation of printing.
2140 2018-02-12 Henry Wong <henry@stuffedcow.net>
2142 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2144 2018-02-05 Nick Clifton <nickc@redhat.com>
2146 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2148 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2150 * i386-dis.c (enum): Add pconfig.
2151 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2152 (cpu_flags): Add CpuPCONFIG.
2153 * i386-opc.h (enum): Add CpuPCONFIG.
2154 (i386_cpu_flags): Add cpupconfig.
2155 * i386-opc.tbl: Add PCONFIG instruction.
2156 * i386-init.h: Regenerate.
2157 * i386-tbl.h: Likewise.
2159 2018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2161 * i386-dis.c (enum): Add PREFIX_0F09.
2162 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2163 (cpu_flags): Add CpuWBNOINVD.
2164 * i386-opc.h (enum): Add CpuWBNOINVD.
2165 (i386_cpu_flags): Add cpuwbnoinvd.
2166 * i386-opc.tbl: Add WBNOINVD instruction.
2167 * i386-init.h: Regenerate.
2168 * i386-tbl.h: Likewise.
2170 2018-01-17 Jim Wilson <jimw@sifive.com>
2172 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2174 2018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2176 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2177 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2178 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2179 (cpu_flags): Add CpuIBT, CpuSHSTK.
2180 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2181 (i386_cpu_flags): Add cpuibt, cpushstk.
2182 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2183 * i386-init.h: Regenerate.
2184 * i386-tbl.h: Likewise.
2186 2018-01-16 Nick Clifton <nickc@redhat.com>
2188 * po/pt_BR.po: Updated Brazilian Portugese translation.
2189 * po/de.po: Updated German translation.
2191 2018-01-15 Jim Wilson <jimw@sifive.com>
2193 * riscv-opc.c (match_c_nop): New.
2194 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2196 2018-01-15 Nick Clifton <nickc@redhat.com>
2198 * po/uk.po: Updated Ukranian translation.
2200 2018-01-13 Nick Clifton <nickc@redhat.com>
2202 * po/opcodes.pot: Regenerated.
2204 2018-01-13 Nick Clifton <nickc@redhat.com>
2206 * configure: Regenerate.
2208 2018-01-13 Nick Clifton <nickc@redhat.com>
2210 2.30 branch created.
2212 2018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2214 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2215 * i386-tbl.h: Regenerate.
2217 2018-01-10 Jan Beulich <jbeulich@suse.com>
2219 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2220 * i386-tbl.h: Re-generate.
2222 2018-01-10 Jan Beulich <jbeulich@suse.com>
2224 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2225 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2226 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2227 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2228 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2229 Disp8MemShift of AVX512VL forms.
2230 * i386-tbl.h: Re-generate.
2232 2018-01-09 Jim Wilson <jimw@sifive.com>
2234 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2235 then the hi_addr value is zero.
2237 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2239 * arm-dis.c (arm_opcodes): Add csdb.
2240 (thumb32_opcodes): Add csdb.
2242 2018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2244 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2245 * aarch64-asm-2.c: Regenerate.
2246 * aarch64-dis-2.c: Regenerate.
2247 * aarch64-opc-2.c: Regenerate.
2249 2018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2252 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2253 Remove AVX512 vmovd with 64-bit operands.
2254 * i386-tbl.h: Regenerated.
2256 2018-01-05 Jim Wilson <jimw@sifive.com>
2258 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2261 2018-01-03 Alan Modra <amodra@gmail.com>
2263 Update year range in copyright notice of all files.
2265 2018-01-02 Jan Beulich <jbeulich@suse.com>
2267 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2268 and OPERAND_TYPE_REGZMM entries.
2270 For older changes see ChangeLog-2017
2272 Copyright (C) 2018 Free Software Foundation, Inc.
2274 Copying and distribution of this file, with or without modification,
2275 are permitted in any medium without royalty provided the copyright
2276 notice and this notice are preserved.
2282 version-control: never