1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
4 sve_size_tsz_bhs iclass encode.
5 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
6 sve_size_tsz_bhs iclass decode.
8 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
10 * aarch64-asm-2.c: Regenerated.
11 * aarch64-dis-2.c: Regenerated.
12 * aarch64-opc-2.c: Regenerated.
13 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
15 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
16 (fields): Handle SVE_i2h field.
17 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
18 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
20 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
22 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
23 sve_shift_tsz_bhsd iclass encode.
24 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
25 sve_shift_tsz_bhsd iclass decode.
27 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
29 * aarch64-asm-2.c: Regenerated.
30 * aarch64-dis-2.c: Regenerated.
31 * aarch64-opc-2.c: Regenerated.
32 * aarch64-asm.c (aarch64_ins_sve_shrimm):
33 (aarch64_encode_variant_using_iclass): Handle
34 sve_shift_tsz_hsd iclass encode.
35 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
36 sve_shift_tsz_hsd iclass decode.
37 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
38 for SVE_SHRIMM_UNPRED_22.
39 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
40 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
43 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
45 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
46 sve_size_013 iclass encode.
47 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
48 sve_size_013 iclass decode.
50 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
52 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
53 sve_size_bh iclass encode.
54 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
55 sve_size_bh iclass decode.
57 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
59 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
60 sve_size_sd2 iclass encode.
61 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
62 sve_size_sd2 iclass decode.
63 * aarch64-opc.c (fields): Handle SVE_sz2 field.
64 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
66 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
68 * aarch64-asm-2.c: Regenerated.
69 * aarch64-dis-2.c: Regenerated.
70 * aarch64-opc-2.c: Regenerated.
71 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
73 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
74 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
76 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
78 * aarch64-asm-2.c: Regenerated.
79 * aarch64-dis-2.c: Regenerated.
80 * aarch64-opc-2.c: Regenerated.
81 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
83 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
84 (fields): Handle SVE_i3l and SVE_i3h2 fields.
85 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
87 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
89 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
91 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
92 sve_size_hsd2 iclass encode.
93 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
94 sve_size_hsd2 iclass decode.
95 * aarch64-opc.c (fields): Handle SVE_size field.
96 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
98 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
100 * aarch64-asm-2.c: Regenerated.
101 * aarch64-dis-2.c: Regenerated.
102 * aarch64-opc-2.c: Regenerated.
103 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
105 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
106 (fields): Handle SVE_rot3 field.
107 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
108 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
110 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
112 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
115 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
118 (aarch64_feature_sve2, aarch64_feature_sve2aes,
119 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
120 aarch64_feature_sve2bitperm): New feature sets.
121 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
122 for feature set addresses.
123 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
124 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
126 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
127 Faraz Shahbazker <fshahbazker@wavecomp.com>
129 * mips-dis.c (mips_calculate_combination_ases): Add ISA
130 argument and set ASE_EVA_R6 appropriately.
131 (set_default_mips_dis_options): Pass ISA to above.
132 (parse_mips_dis_option): Likewise.
133 * mips-opc.c (EVAR6): New macro.
134 (mips_builtin_opcodes): Add llwpe, scwpe.
136 2019-05-01 Sudakshina Das <sudi.das@arm.com>
138 * aarch64-asm-2.c: Regenerated.
139 * aarch64-dis-2.c: Regenerated.
140 * aarch64-opc-2.c: Regenerated.
141 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
142 AARCH64_OPND_TME_UIMM16.
143 (aarch64_print_operand): Likewise.
144 * aarch64-tbl.h (QL_IMM_NIL): New.
147 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
149 2019-04-29 John Darrington <john@darrington.wattle.id.au>
151 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
153 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
154 Faraz Shahbazker <fshahbazker@wavecomp.com>
156 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
158 2019-04-24 John Darrington <john@darrington.wattle.id.au>
160 * s12z-opc.h: Add extern "C" bracketing to help
161 users who wish to use this interface in c++ code.
163 2019-04-24 John Darrington <john@darrington.wattle.id.au>
165 * s12z-opc.c (bm_decode): Handle bit map operations with the
168 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
170 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
171 specifier. Add entries for VLDR and VSTR of system registers.
172 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
173 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
174 of %J and %K format specifier.
176 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
178 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
179 Add new entries for VSCCLRM instruction.
180 (print_insn_coprocessor): Handle new %C format control code.
182 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
184 * arm-dis.c (enum isa): New enum.
185 (struct sopcode32): New structure.
186 (coprocessor_opcodes): change type of entries to struct sopcode32 and
187 set isa field of all current entries to ANY.
188 (print_insn_coprocessor): Change type of insn to struct sopcode32.
189 Only match an entry if its isa field allows the current mode.
191 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
193 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
195 (print_insn_thumb32): Add logic to print %n CLRM register list.
197 2019-04-15 Sudakshina Das <sudi.das@arm.com>
199 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
202 2019-04-15 Sudakshina Das <sudi.das@arm.com>
204 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
205 (print_insn_thumb32): Edit the switch case for %Z.
207 2019-04-15 Sudakshina Das <sudi.das@arm.com>
209 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
211 2019-04-15 Sudakshina Das <sudi.das@arm.com>
213 * arm-dis.c (thumb32_opcodes): New instruction bfl.
215 2019-04-15 Sudakshina Das <sudi.das@arm.com>
217 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
219 2019-04-15 Sudakshina Das <sudi.das@arm.com>
221 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
222 Arm register with r13 and r15 unpredictable.
223 (thumb32_opcodes): New instructions for bfx and bflx.
225 2019-04-15 Sudakshina Das <sudi.das@arm.com>
227 * arm-dis.c (thumb32_opcodes): New instructions for bf.
229 2019-04-15 Sudakshina Das <sudi.das@arm.com>
231 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
233 2019-04-15 Sudakshina Das <sudi.das@arm.com>
235 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
237 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
239 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
241 2019-04-12 John Darrington <john@darrington.wattle.id.au>
243 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
244 "optr". ("operator" is a reserved word in c++).
246 2019-04-11 Sudakshina Das <sudi.das@arm.com>
248 * aarch64-opc.c (aarch64_print_operand): Add case for
250 (verify_constraints): Likewise.
251 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
252 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
253 to accept Rt|SP as first operand.
254 (AARCH64_OPERANDS): Add new Rt_SP.
255 * aarch64-asm-2.c: Regenerated.
256 * aarch64-dis-2.c: Regenerated.
257 * aarch64-opc-2.c: Regenerated.
259 2019-04-11 Sudakshina Das <sudi.das@arm.com>
261 * aarch64-asm-2.c: Regenerated.
262 * aarch64-dis-2.c: Likewise.
263 * aarch64-opc-2.c: Likewise.
264 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
266 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
268 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
270 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
272 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
273 * i386-init.h: Regenerated.
275 2019-04-07 Alan Modra <amodra@gmail.com>
277 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
278 op_separator to control printing of spaces, comma and parens
279 rather than need_comma, need_paren and spaces vars.
281 2019-04-07 Alan Modra <amodra@gmail.com>
284 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
285 (print_insn_neon, print_insn_arm): Likewise.
287 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
289 * i386-dis-evex.h (evex_table): Updated to support BF16
291 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
292 and EVEX_W_0F3872_P_3.
293 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
294 (cpu_flags): Add bitfield for CpuAVX512_BF16.
295 * i386-opc.h (enum): Add CpuAVX512_BF16.
296 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
297 * i386-opc.tbl: Add AVX512 BF16 instructions.
298 * i386-init.h: Regenerated.
299 * i386-tbl.h: Likewise.
301 2019-04-05 Alan Modra <amodra@gmail.com>
303 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
304 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
305 to favour printing of "-" branch hint when using the "y" bit.
306 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
308 2019-04-05 Alan Modra <amodra@gmail.com>
310 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
311 opcode until first operand is output.
313 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
316 * ppc-opc.c (valid_bo_pre_v2): Add comments.
317 (valid_bo_post_v2): Add support for 'at' branch hints.
318 (insert_bo): Only error on branch on ctr.
319 (get_bo_hint_mask): New function.
320 (insert_boe): Add new 'branch_taken' formal argument. Add support
321 for inserting 'at' branch hints.
322 (extract_boe): Add new 'branch_taken' formal argument. Add support
323 for extracting 'at' branch hints.
324 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
325 (BOE): Delete operand.
326 (BOM, BOP): New operands.
328 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
329 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
330 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
331 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
332 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
333 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
334 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
335 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
336 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
337 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
338 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
339 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
340 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
341 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
342 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
343 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
344 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
345 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
346 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
347 bttarl+>: New extended mnemonics.
349 2019-03-28 Alan Modra <amodra@gmail.com>
352 * ppc-opc.c (BTF): Define.
353 (powerpc_opcodes): Use for mtfsb*.
354 * ppc-dis.c (print_insn_powerpc): Print fields with both
355 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
357 2019-03-25 Tamar Christina <tamar.christina@arm.com>
359 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
360 (mapping_symbol_for_insn): Implement new algorithm.
361 (print_insn): Remove duplicate code.
363 2019-03-25 Tamar Christina <tamar.christina@arm.com>
365 * aarch64-dis.c (print_insn_aarch64):
368 2019-03-25 Tamar Christina <tamar.christina@arm.com>
370 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
373 2019-03-25 Tamar Christina <tamar.christina@arm.com>
375 * aarch64-dis.c (last_stop_offset): New.
376 (print_insn_aarch64): Use stop_offset.
378 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
381 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
383 * i386-init.h: Regenerated.
385 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
388 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
389 vmovdqu16, vmovdqu32 and vmovdqu64.
390 * i386-tbl.h: Regenerated.
392 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
394 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
395 from vstrszb, vstrszh, and vstrszf.
397 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
399 * s390-opc.txt: Add instruction descriptions.
401 2019-02-08 Jim Wilson <jimw@sifive.com>
403 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
406 2019-02-07 Tamar Christina <tamar.christina@arm.com>
408 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
410 2019-02-07 Tamar Christina <tamar.christina@arm.com>
413 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
414 * aarch64-opc.c (verify_elem_sd): New.
415 (fields): Add FLD_sz entr.
416 * aarch64-tbl.h (_SIMD_INSN): New.
417 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
418 fmulx scalar and vector by element isns.
420 2019-02-07 Nick Clifton <nickc@redhat.com>
422 * po/sv.po: Updated Swedish translation.
424 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
426 * s390-mkopc.c (main): Accept arch13 as cpu string.
427 * s390-opc.c: Add new instruction formats and instruction opcode
429 * s390-opc.txt: Add new arch13 instructions.
431 2019-01-25 Sudakshina Das <sudi.das@arm.com>
433 * aarch64-tbl.h (QL_LDST_AT): Update macro.
434 (aarch64_opcode): Change encoding for stg, stzg
436 * aarch64-asm-2.c: Regenerated.
437 * aarch64-dis-2.c: Regenerated.
438 * aarch64-opc-2.c: Regenerated.
440 2019-01-25 Sudakshina Das <sudi.das@arm.com>
442 * aarch64-asm-2.c: Regenerated.
443 * aarch64-dis-2.c: Likewise.
444 * aarch64-opc-2.c: Likewise.
445 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
447 2019-01-25 Sudakshina Das <sudi.das@arm.com>
448 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
450 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
451 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
452 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
453 * aarch64-dis.h (ext_addr_simple_2): Likewise.
454 * aarch64-opc.c (operand_general_constraint_met_p): Remove
455 case for ldstgv_indexed.
456 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
457 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
458 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
459 * aarch64-asm-2.c: Regenerated.
460 * aarch64-dis-2.c: Regenerated.
461 * aarch64-opc-2.c: Regenerated.
463 2019-01-23 Nick Clifton <nickc@redhat.com>
465 * po/pt_BR.po: Updated Brazilian Portuguese translation.
467 2019-01-21 Nick Clifton <nickc@redhat.com>
469 * po/de.po: Updated German translation.
470 * po/uk.po: Updated Ukranian translation.
472 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
473 * mips-dis.c (mips_arch_choices): Fix typo in
474 gs464, gs464e and gs264e descriptors.
476 2019-01-19 Nick Clifton <nickc@redhat.com>
478 * configure: Regenerate.
479 * po/opcodes.pot: Regenerate.
481 2018-06-24 Nick Clifton <nickc@redhat.com>
485 2019-01-09 John Darrington <john@darrington.wattle.id.au>
487 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
489 -dis.c (opr_emit_disassembly): Do not omit an index if it is
492 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
494 * configure: Regenerate.
496 2019-01-07 Alan Modra <amodra@gmail.com>
498 * configure: Regenerate.
499 * po/POTFILES.in: Regenerate.
501 2019-01-03 John Darrington <john@darrington.wattle.id.au>
503 * s12z-opc.c: New file.
504 * s12z-opc.h: New file.
505 * s12z-dis.c: Removed all code not directly related to display
506 of instructions. Used the interface provided by the new files
508 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
509 * Makefile.in: Regenerate.
510 * configure.ac (bfd_s12z_arch): Correct the dependencies.
511 * configure: Regenerate.
513 2019-01-01 Alan Modra <amodra@gmail.com>
515 Update year range in copyright notice of all files.
517 For older changes see ChangeLog-2018
519 Copyright (C) 2019 Free Software Foundation, Inc.
521 Copying and distribution of this file, with or without modification,
522 are permitted in any medium without royalty provided the copyright
523 notice and this notice are preserved.
529 version-control: never