1 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
5 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
7 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
8 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
9 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
11 (aarch64_sys_reg_supported_p): Add architecture feature tests for
14 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
16 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
17 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
18 feature test for "s1e1rp" and "s1e1wp".
20 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
22 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
23 (aarch64_sys_ins_reg_supported_p): New.
25 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
27 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
28 with aarch64_sys_ins_reg_has_xt.
29 (aarch64_ext_sysins_op): Likewise.
30 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
32 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
33 (aarch64_sys_regs_dc): Likewise.
34 (aarch64_sys_regs_at): Likewise.
35 (aarch64_sys_regs_tlbi): Likewise.
36 (aarch64_sys_ins_reg_has_xt): New.
38 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
40 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
41 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
42 (aarch64_pstatefields): Add "uao".
43 (aarch64_pstatefield_supported_p): Add checks for "uao".
45 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
47 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
48 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
49 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
50 (aarch64_sys_reg_supported_p): Add architecture feature tests for
53 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
55 * aarch64-asm-2.c: Regenerate.
56 * aarch64-dis-2.c: Regenerate.
57 * aarch64-tbl.h (aarch64_feature_ras): New.
59 (aarch64_opcode_table): Add "esb".
61 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
63 * i386-dis.c (MOD_0F01_REG_5): New.
64 (RM_0F01_REG_5): Likewise.
65 (reg_table): Use MOD_0F01_REG_5.
66 (mod_table): Add MOD_0F01_REG_5.
67 (rm_table): Add RM_0F01_REG_5.
68 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
69 (cpu_flags): Add CpuOSPKE.
70 * i386-opc.h (CpuOSPKE): New.
71 (i386_cpu_flags): Add cpuospke.
72 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
73 * i386-init.h: Regenerated.
74 * i386-tbl.h: Likewise.
76 2015-12-07 DJ Delorie <dj@redhat.com>
78 * rl78-decode.opc: Enable MULU for all ISAs.
79 * rl78-decode.c: Regenerate.
81 2015-12-07 Alan Modra <amodra@gmail.com>
83 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
86 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
88 * arc-dis.c (special_flag_p): Match full mnemonic.
89 * arc-opc.c (print_insn_arc): Check section size to read
90 appropriate number of bytes. Fix printing.
91 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
94 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
96 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
99 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
101 * aarch64-asm-2.c: Regenerate.
102 * aarch64-dis-2.c: Regenerate.
103 * aarch64-opc-2.c: Regenerate.
104 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
105 (QL_INT2FP_H, QL_FP2INT_H): New.
106 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
109 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
110 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
111 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
112 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
113 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
114 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
117 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
119 * aarch64-opc.c (half_conv_t): New.
120 (expand_fp_imm): Replace is_dp flag with the parameter size to
121 specify the number of bytes for the required expansion. Treat
122 a 16-bit expansion like a 32-bit expansion. Add check for an
123 unsupported size request. Update comment.
124 (aarch64_print_operand): Update to support 16-bit floating point
125 values. Update for changes to expand_fp_imm.
127 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
129 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
132 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
134 * aarch64-asm-2.c: Regenerate.
135 * aarch64-dis-2.c: Regenerate.
136 * aarch64-opc-2.c: Regenerate.
137 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
140 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
142 * aarch64-asm-2.c: Regenerate.
143 * aarch64-asm.c (convert_bfc_to_bfm): New.
144 (convert_to_real): Add case for OP_BFC.
145 * aarch64-dis-2.c: Regenerate.
146 * aarch64-dis.c: (convert_bfm_to_bfc): New.
147 (convert_to_alias): Add case for OP_BFC.
148 * aarch64-opc-2.c: Regenerate.
149 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
150 to allow width operand in three-operand instructions.
151 * aarch64-tbl.h (QL_BF1): New.
152 (aarch64_feature_v8_2): New.
154 (aarch64_opcode_table): Add "bfc".
156 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
158 * aarch64-asm-2.c: Regenerate.
159 * aarch64-dis-2.c: Regenerate.
160 * aarch64-dis.c: Weaken assert.
161 * aarch64-gen.c: Include the instruction in the list of its
164 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
166 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
167 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
170 2015-11-23 Tristan Gingold <gingold@adacore.com>
172 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
174 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
176 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
177 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
178 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
179 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
180 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
181 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
182 cnthv_ctl_el2, cnthv_cval_el2.
183 (aarch64_sys_reg_supported_p): Update for the new system
186 2015-11-20 Nick Clifton <nickc@redhat.com>
189 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
191 2015-11-20 Nick Clifton <nickc@redhat.com>
193 * po/zh_CN.po: Updated simplified Chinese translation.
195 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
197 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
198 of MSR PAN immediate operand.
200 2015-11-16 Nick Clifton <nickc@redhat.com>
202 * rx-dis.c (condition_names): Replace always and never with
203 invalid, since the always/never conditions can never be legal.
205 2015-11-13 Tristan Gingold <gingold@adacore.com>
207 * configure: Regenerate.
209 2015-11-11 Alan Modra <amodra@gmail.com>
210 Peter Bergner <bergner@vnet.ibm.com>
212 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
213 Add PPC_OPCODE_VSX3 to the vsx entry.
214 (powerpc_init_dialect): Set default dialect to power9.
215 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
216 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
217 extract_l1 insert_xtq6, extract_xtq6): New static functions.
218 (insert_esync): Test for illegal L operand value.
219 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
220 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
221 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
222 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
223 PPCVSX3): New defines.
224 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
225 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
226 <mcrxr>: Use XBFRARB_MASK.
227 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
228 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
229 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
230 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
231 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
232 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
233 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
234 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
235 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
236 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
237 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
238 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
239 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
240 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
241 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
242 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
243 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
244 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
245 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
246 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
247 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
248 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
249 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
250 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
251 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
252 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
253 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
254 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
255 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
256 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
257 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
258 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
260 2015-11-02 Nick Clifton <nickc@redhat.com>
262 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
264 * rx-decode.c: Regenerate.
266 2015-11-02 Nick Clifton <nickc@redhat.com>
268 * rx-decode.opc (rx_disp): If the displacement is zero, set the
269 type to RX_Operand_Zero_Indirect.
270 * rx-decode.c: Regenerate.
271 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
273 2015-10-28 Yao Qi <yao.qi@linaro.org>
275 * aarch64-dis.c (aarch64_decode_insn): Add one argument
276 noaliases_p. Update comments. Pass noaliases_p rather than
277 no_aliases to aarch64_opcode_decode.
278 (print_insn_aarch64_word): Pass no_aliases to
281 2015-10-27 Vinay <Vinay.G@kpit.com>
284 * rl78-decode.opc (MOV): Added offset to DE register in index
286 * rl78-decode.c: Regenerate.
288 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
291 * rl78-decode.opc: Add 's' print operator to instructions that
292 access system registers.
293 * rl78-decode.c: Regenerate.
294 * rl78-dis.c (print_insn_rl78_common): Decode all system
297 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
300 * rl78-decode.opc: Add 'a' print operator to mov instructions
301 using stack pointer plus index addressing.
302 * rl78-decode.c: Regenerate.
304 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
306 * s390-opc.c: Fix comment.
307 * s390-opc.txt: Change instruction type for troo, trot, trto, and
308 trtt to RRF_U0RER since the second parameter does not need to be a
311 2015-10-08 Nick Clifton <nickc@redhat.com>
313 * arc-dis.c (print_insn_arc): Initiallise insn array.
315 2015-10-07 Yao Qi <yao.qi@linaro.org>
317 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
318 'name' rather than 'template'.
319 * aarch64-opc.c (aarch64_print_operand): Likewise.
321 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
323 * arc-dis.c: Revamped file for ARC support
324 * arc-dis.h: Likewise.
325 * arc-ext.c: Likewise.
326 * arc-ext.h: Likewise.
327 * arc-opc.c: Likewise.
328 * arc-fxi.h: New file.
329 * arc-regs.h: Likewise.
330 * arc-tbl.h: Likewise.
332 2015-10-02 Yao Qi <yao.qi@linaro.org>
334 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
335 argument insn type to aarch64_insn. Rename to ...
336 (aarch64_decode_insn): ... it.
337 (print_insn_aarch64_word): Caller updated.
339 2015-10-02 Yao Qi <yao.qi@linaro.org>
341 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
342 (print_insn_aarch64_word): Caller updated.
344 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
346 * s390-mkopc.c (main): Parse htm and vx flag.
347 * s390-opc.txt: Mark instructions from the hardware transactional
348 memory and vector facilities with the "htm"/"vx" flag.
350 2015-09-28 Nick Clifton <nickc@redhat.com>
352 * po/de.po: Updated German translation.
354 2015-09-28 Tom Rix <tom@bumblecow.com>
356 * ppc-opc.c (PPC500): Mark some opcodes as invalid
358 2015-09-23 Nick Clifton <nickc@redhat.com>
360 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
362 * tic30-dis.c (print_branch): Likewise.
363 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
364 value before left shifting.
365 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
366 * hppa-dis.c (print_insn_hppa): Likewise.
367 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
369 * msp430-dis.c (msp430_singleoperand): Likewise.
370 (msp430_doubleoperand): Likewise.
371 (print_insn_msp430): Likewise.
372 * nds32-asm.c (parse_operand): Likewise.
373 * sh-opc.h (MASK): Likewise.
374 * v850-dis.c (get_operand_value): Likewise.
376 2015-09-22 Nick Clifton <nickc@redhat.com>
378 * rx-decode.opc (bwl): Use RX_Bad_Size.
380 (ubwl): Likewise. Rename to ubw.
381 (uBWL): Rename to uBW.
382 Replace all references to uBWL with uBW.
383 * rx-decode.c: Regenerate.
384 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
385 (opsize_names): Likewise.
386 (print_insn_rx): Detect and report RX_Bad_Size.
388 2015-09-22 Anton Blanchard <anton@samba.org>
390 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
392 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
394 * sparc-dis.c (print_insn_sparc): Handle the privileged register
397 2015-08-24 Jan Stancek <jstancek@redhat.com>
399 * i386-dis.c (print_insn): Fix decoding of three byte operands.
401 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
404 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
405 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
406 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
407 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
408 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
409 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
410 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
411 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
412 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
413 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
414 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
415 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
416 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
417 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
418 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
419 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
420 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
421 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
422 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
423 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
424 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
425 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
426 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
427 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
428 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
429 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
430 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
431 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
432 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
433 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
434 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
435 (vex_w_table): Replace terminals with MOD_TABLE entries for
436 most of mask instructions.
438 2015-08-17 Alan Modra <amodra@gmail.com>
440 * cgen.sh: Trim trailing space from cgen output.
441 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
442 (print_dis_table): Likewise.
443 * opc2c.c (dump_lines): Likewise.
444 (orig_filename): Warning fix.
445 * ia64-asmtab.c: Regenerate.
447 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
449 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
450 and higher with ARM instruction set will now mark the 26-bit
451 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
452 (arm_opcodes): Fix for unpredictable nop being recognized as a
455 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
457 * micromips-opc.c (micromips_opcodes): Re-order table so that move
458 based on 'or' is first.
459 * mips-opc.c (mips_builtin_opcodes): Ditto.
461 2015-08-11 Nick Clifton <nickc@redhat.com>
464 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
467 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
469 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
471 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
473 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
474 * i386-init.h: Regenerated.
476 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
479 * i386-dis.c (MOD_0FC3): New.
480 (PREFIX_0FC3): Renamed to ...
481 (PREFIX_MOD_0_0FC3): This.
482 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
483 (prefix_table): Replace Ma with Ev on movntiS.
484 (mod_table): Add MOD_0FC3.
486 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
488 * configure: Regenerated.
490 2015-07-23 Alan Modra <amodra@gmail.com>
493 * i386-dis.c (get64): Avoid signed integer overflow.
495 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
498 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
499 "EXEvexHalfBcstXmmq" for the second operand.
500 (EVEX_W_0F79_P_2): Likewise.
501 (EVEX_W_0F7A_P_2): Likewise.
502 (EVEX_W_0F7B_P_2): Likewise.
504 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
506 * arm-dis.c (print_insn_coprocessor): Added support for quarter
507 float bitfield format.
508 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
509 quarter float bitfield format.
511 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
513 * configure: Regenerated.
515 2015-07-03 Alan Modra <amodra@gmail.com>
517 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
518 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
519 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
521 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
522 Cesar Philippidis <cesar@codesourcery.com>
524 * nios2-dis.c (nios2_extract_opcode): New.
525 (nios2_disassembler_state): New.
526 (nios2_find_opcode_hash): Use mach parameter to select correct
528 (nios2_print_insn_arg): Extend to support new R2 argument letters
530 (print_insn_nios2): Check for 16-bit instruction at end of memory.
531 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
532 (NIOS2_NUM_OPCODES): Rename to...
533 (NIOS2_NUM_R1_OPCODES): This.
534 (nios2_r2_opcodes): New.
535 (NIOS2_NUM_R2_OPCODES): New.
536 (nios2_num_r2_opcodes): New.
537 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
538 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
539 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
540 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
541 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
543 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
545 * i386-dis.c (OP_Mwaitx): New.
546 (rm_table): Add monitorx/mwaitx.
547 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
548 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
549 (operand_type_init): Add CpuMWAITX.
550 * i386-opc.h (CpuMWAITX): New.
551 (i386_cpu_flags): Add cpumwaitx.
552 * i386-opc.tbl: Add monitorx and mwaitx.
553 * i386-init.h: Regenerated.
554 * i386-tbl.h: Likewise.
556 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
558 * ppc-opc.c (insert_ls): Test for invalid LS operands.
559 (insert_esync): New function.
560 (LS, WC): Use insert_ls.
561 (ESYNC): Use insert_esync.
563 2015-06-22 Nick Clifton <nickc@redhat.com>
565 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
566 requested region lies beyond it.
567 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
568 looking for 32-bit insns.
569 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
571 * sh-dis.c (print_insn_sh): Likewise.
572 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
573 blocks of instructions.
574 * vax-dis.c (print_insn_vax): Check that the requested address
575 does not clash with the stop_vma.
577 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
579 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
580 * ppc-opc.c (FXM4): Add non-zero optional value.
583 (insert_fxm): Handle new default operand value.
584 (extract_fxm): Likewise.
585 (insert_tbr): Likewise.
586 (extract_tbr): Likewise.
588 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
590 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
592 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
594 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
596 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
598 * ppc-opc.c: Add comment accidentally removed by old commit.
601 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
603 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
605 2015-06-04 Nick Clifton <nickc@redhat.com>
608 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
610 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
612 * arm-dis.c (arm_opcodes): Add "setpan".
613 (thumb_opcodes): Add "setpan".
615 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
617 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
620 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
622 * aarch64-tbl.h (aarch64_feature_rdma): New.
624 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
625 * aarch64-asm-2.c: Regenerate.
626 * aarch64-dis-2.c: Regenerate.
627 * aarch64-opc-2.c: Regenerate.
629 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
631 * aarch64-tbl.h (aarch64_feature_lor): New.
633 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
635 * aarch64-asm-2.c: Regenerate.
636 * aarch64-dis-2.c: Regenerate.
637 * aarch64-opc-2.c: Regenerate.
639 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
641 * aarch64-opc.c (F_ARCHEXT): New.
642 (aarch64_sys_regs): Add "pan".
643 (aarch64_sys_reg_supported_p): New.
644 (aarch64_pstatefields): Add "pan".
645 (aarch64_pstatefield_supported_p): New.
647 2015-06-01 Jan Beulich <jbeulich@suse.com>
649 * i386-tbl.h: Regenerate.
651 2015-06-01 Jan Beulich <jbeulich@suse.com>
653 * i386-dis.c (print_insn): Swap rounding mode specifier and
654 general purpose register in Intel mode.
656 2015-06-01 Jan Beulich <jbeulich@suse.com>
658 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
659 * i386-tbl.h: Regenerate.
661 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
663 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
664 * i386-init.h: Regenerated.
666 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
669 * i386-dis.c: Add comments for '@'.
670 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
671 (enum x86_64_isa): New.
673 (print_i386_disassembler_options): Add amd64 and intel64.
674 (print_insn): Handle amd64 and intel64.
676 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
677 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
678 * i386-opc.h (AMD64): New.
679 (CpuIntel64): Likewise.
680 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
681 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
682 Mark direct call/jmp without Disp16|Disp32 as Intel64.
683 * i386-init.h: Regenerated.
684 * i386-tbl.h: Likewise.
686 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
688 * ppc-opc.c (IH) New define.
689 (powerpc_opcodes) <wait>: Do not enable for POWER7.
690 <tlbie>: Add RS operand for POWER7.
691 <slbia>: Add IH operand for POWER6.
693 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
695 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
698 * i386-tbl.h: Regenerated.
700 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
702 * configure.ac: Support bfd_iamcu_arch.
703 * disassemble.c (disassembler): Support bfd_iamcu_arch.
704 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
705 CPU_IAMCU_COMPAT_FLAGS.
706 (cpu_flags): Add CpuIAMCU.
707 * i386-opc.h (CpuIAMCU): New.
708 (i386_cpu_flags): Add cpuiamcu.
709 * configure: Regenerated.
710 * i386-init.h: Likewise.
711 * i386-tbl.h: Likewise.
713 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
716 * i386-dis.c (X86_64_E8): New.
717 (X86_64_E9): Likewise.
718 Update comments on 'T', 'U', 'V'. Add comments for '^'.
719 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
720 (x86_64_table): Add X86_64_E8 and X86_64_E9.
721 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
723 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
726 2015-04-30 DJ Delorie <dj@redhat.com>
728 * disassemble.c (disassembler): Choose suitable disassembler based
730 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
731 it to decode mul/div insns.
732 * rl78-decode.c: Regenerate.
733 * rl78-dis.c (print_insn_rl78): Rename to...
734 (print_insn_rl78_common): ...this, take ISA parameter.
735 (print_insn_rl78): New.
736 (print_insn_rl78_g10): New.
737 (print_insn_rl78_g13): New.
738 (print_insn_rl78_g14): New.
739 (rl78_get_disassembler): New.
741 2015-04-29 Nick Clifton <nickc@redhat.com>
743 * po/fr.po: Updated French translation.
745 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
747 * ppc-opc.c (DCBT_EO): New define.
748 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
752 <waitrsv>: Do not enable for POWER7 and later.
753 <waitimpl>: Likewise.
754 <dcbt>: Default to the two operand form of the instruction for all
755 "old" cpus. For "new" cpus, use the operand ordering that matches
756 whether the cpu is server or embedded.
759 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
761 * s390-opc.c: New instruction type VV0UU2.
762 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
765 2015-04-23 Jan Beulich <jbeulich@suse.com>
767 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
768 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
769 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
770 (vfpclasspd, vfpclassps): Add %XZ.
772 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
774 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
775 (PREFIX_UD_REPZ): Likewise.
776 (PREFIX_UD_REPNZ): Likewise.
777 (PREFIX_UD_DATA): Likewise.
778 (PREFIX_UD_ADDR): Likewise.
779 (PREFIX_UD_LOCK): Likewise.
781 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
783 * i386-dis.c (prefix_requirement): Removed.
784 (print_insn): Don't set prefix_requirement. Check
785 dp->prefix_requirement instead of prefix_requirement.
787 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
790 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
791 (PREFIX_MOD_0_0FC7_REG_6): This.
792 (PREFIX_MOD_3_0FC7_REG_6): New.
793 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
794 (prefix_table): Replace PREFIX_0FC7_REG_6 with
795 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
796 PREFIX_MOD_3_0FC7_REG_7.
797 (mod_table): Replace PREFIX_0FC7_REG_6 with
798 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
799 PREFIX_MOD_3_0FC7_REG_7.
801 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
803 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
804 (PREFIX_MANDATORY_REPNZ): Likewise.
805 (PREFIX_MANDATORY_DATA): Likewise.
806 (PREFIX_MANDATORY_ADDR): Likewise.
807 (PREFIX_MANDATORY_LOCK): Likewise.
808 (PREFIX_MANDATORY): Likewise.
809 (PREFIX_UD_SHIFT): Set to 8
810 (PREFIX_UD_REPZ): Updated.
811 (PREFIX_UD_REPNZ): Likewise.
812 (PREFIX_UD_DATA): Likewise.
813 (PREFIX_UD_ADDR): Likewise.
814 (PREFIX_UD_LOCK): Likewise.
815 (PREFIX_IGNORED_SHIFT): New.
816 (PREFIX_IGNORED_REPZ): Likewise.
817 (PREFIX_IGNORED_REPNZ): Likewise.
818 (PREFIX_IGNORED_DATA): Likewise.
819 (PREFIX_IGNORED_ADDR): Likewise.
820 (PREFIX_IGNORED_LOCK): Likewise.
821 (PREFIX_OPCODE): Likewise.
822 (PREFIX_IGNORED): Likewise.
823 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
824 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
825 (three_byte_table): Likewise.
826 (mod_table): Likewise.
827 (mandatory_prefix): Renamed to ...
828 (prefix_requirement): This.
829 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
830 Update PREFIX_90 entry.
831 (get_valid_dis386): Check prefix_requirement to see if a prefix
833 (print_insn): Replace mandatory_prefix with prefix_requirement.
835 2015-04-15 Renlin Li <renlin.li@arm.com>
837 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
838 use it for ssat and ssat16.
839 (print_insn_thumb32): Add handle case for 'D' control code.
841 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
842 H.J. Lu <hongjiu.lu@intel.com>
844 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
845 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
846 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
847 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
848 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
849 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
850 Fill prefix_requirement field.
851 (struct dis386): Add prefix_requirement field.
852 (dis386): Fill prefix_requirement field.
853 (dis386_twobyte): Ditto.
854 (twobyte_has_mandatory_prefix_: Remove.
855 (reg_table): Fill prefix_requirement field.
856 (prefix_table): Ditto.
857 (x86_64_table): Ditto.
858 (three_byte_table): Ditto.
861 (vex_len_table): Ditto.
862 (vex_w_table): Ditto.
865 (print_insn): Use prefix_requirement.
866 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
867 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
870 2015-03-30 Mike Frysinger <vapier@gentoo.org>
872 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
874 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
876 * Makefile.in: Regenerated.
878 2015-03-25 Anton Blanchard <anton@samba.org>
880 * ppc-dis.c (disassemble_init_powerpc): Only initialise
881 powerpc_opcd_indices and vle_opcd_indices once.
883 2015-03-25 Anton Blanchard <anton@samba.org>
885 * ppc-opc.c (powerpc_opcodes): Add slbfee.
887 2015-03-24 Terry Guo <terry.guo@arm.com>
889 * arm-dis.c (opcode32): Updated to use new arm feature struct.
890 (opcode16): Likewise.
891 (coprocessor_opcodes): Replace bit with feature struct.
892 (neon_opcodes): Likewise.
893 (arm_opcodes): Likewise.
894 (thumb_opcodes): Likewise.
895 (thumb32_opcodes): Likewise.
896 (print_insn_coprocessor): Likewise.
897 (print_insn_arm): Likewise.
898 (select_arm_features): Follow new feature struct.
900 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
902 * i386-dis.c (rm_table): Add clzero.
903 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
904 Add CPU_CLZERO_FLAGS.
905 (cpu_flags): Add CpuCLZERO.
906 * i386-opc.h: Add CpuCLZERO.
907 * i386-opc.tbl: Add clzero.
908 * i386-init.h: Re-generated.
909 * i386-tbl.h: Re-generated.
911 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
913 * mips-opc.c (decode_mips_operand): Fix constraint issues
914 with u and y operands.
916 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
918 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
920 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
922 * s390-opc.c: Add new IBM z13 instructions.
923 * s390-opc.txt: Likewise.
925 2015-03-10 Renlin Li <renlin.li@arm.com>
927 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
928 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
930 * aarch64-asm-2.c: Regenerate.
931 * aarch64-dis-2.c: Likewise.
932 * aarch64-opc-2.c: Likewise.
934 2015-03-03 Jiong Wang <jiong.wang@arm.com>
936 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
938 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
940 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
942 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
943 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
945 2015-02-23 Vinay <Vinay.G@kpit.com>
947 * rl78-decode.opc (MOV): Added space between two operands for
948 'mov' instruction in index addressing mode.
949 * rl78-decode.c: Regenerate.
951 2015-02-19 Pedro Alves <palves@redhat.com>
953 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
955 2015-02-10 Pedro Alves <palves@redhat.com>
956 Tom Tromey <tromey@redhat.com>
958 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
959 microblaze_and, microblaze_xor.
960 * microblaze-opc.h (opcodes): Adjust.
962 2015-01-28 James Bowman <james.bowman@ftdichip.com>
964 * Makefile.am: Add FT32 files.
965 * configure.ac: Handle FT32.
966 * disassemble.c (disassembler): Call print_insn_ft32.
967 * ft32-dis.c: New file.
968 * ft32-opc.c: New file.
969 * Makefile.in: Regenerate.
970 * configure: Regenerate.
971 * po/POTFILES.in: Regenerate.
973 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
975 * nds32-asm.c (keyword_sr): Add new system registers.
977 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
979 * s390-dis.c (s390_extract_operand): Support vector register
981 (s390_print_insn_with_opcode): Support new operands types and add
982 new handling of optional operands.
983 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
984 and include opcode/s390.h instead.
985 (struct op_struct): New field `flags'.
986 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
987 (dumpTable): Dump flags.
988 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
990 * s390-opc.c: Add new operands types, instruction formats, and
992 (s390_opformats): Add new formats for .insn.
993 * s390-opc.txt: Add new instructions.
995 2015-01-01 Alan Modra <amodra@gmail.com>
997 Update year range in copyright notice of all files.
999 For older changes see ChangeLog-2014
1001 Copyright (C) 2015 Free Software Foundation, Inc.
1003 Copying and distribution of this file, with or without modification,
1004 are permitted in any medium without royalty provided the copyright
1005 notice and this notice are preserved.
1011 version-control: never