1 2011-10-27 Peter Bergner <bergner@vnet.ibm.com>
3 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
4 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
5 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
8 2011-10-25 Alan Modra <amodra@gmail.com>
10 Apply mainline patches
11 2011-09-28 Jan Beulich <jbeulich@suse.com>
12 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
14 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
15 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
16 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
17 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
18 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
19 on DFP quad instructions.
21 2011-09-21 David S. Miller <davem@davemloft.net>
23 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
24 bits. Fix "fchksm16" mnemonic.
26 2011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
28 The changes below bring 'mov' and 'ticc' instructions into line
29 with the V8 SPARC Architecture Manual.
30 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
31 * sparc-opc.c (sparc_opcodes): Add alias entries for
32 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
33 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
34 * sparc-opc.c (sparc_opcodes): Move/Change entries for
35 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
37 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
40 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
41 This has been reported as being accepted by the Sun assmebler.
43 2011-09-08 David S. Miller <davem@davemloft.net>
45 * sparc-opc.c (pdistn): Destination is integer not float register.
47 2011-09-07 Andreas Schwab <schwab@linux-m68k.org>
50 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
52 2011-08-26 Nick Clifton <nickc@redhat.com>
54 * po/es.po: Updated Spanish translation.
56 2011-08-22 Nick Clifton <nickc@redhat.com>
58 * Makefile.am (CPUDIR): Redfine to point to top level cpu
60 (stamp-frv): Use CPUDIR.
61 (stamp-iq2000): Likewise.
62 (stamp-lm32): Likewise.
63 (stamp-m32c): Likewise.
65 (stamp-xc16x): Likewise.
66 * Makefile.in: Regenerate.
68 2011-08-09 Chao-ying Fu <fu@mips.com>
69 Maciej W. Rozycki <macro@codesourcery.com>
71 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
73 (print_insn_args, print_insn_micromips): Handle MCU.
74 * micromips-opc.c (MC): New macro.
75 (micromips_opcodes): Add "aclr", "aset" and "iret".
76 * mips-opc.c (MC): New macro.
77 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
79 2011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
81 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
82 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
83 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
84 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
85 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
86 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
88 (micromips_opcodes): Update register use flags of: "addiu",
89 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
90 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
91 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
92 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
93 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
94 "swm" and "xor" instructions.
96 2011-08-05 David S. Miller <davem@davemloft.net>
98 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
100 (print_insn_sparc): Handle '4', '5', and '(' format codes.
101 Accept %asr numbers below 28.
102 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
105 2011-08-02 Quentin Neill <quentin.neill@amd.com>
107 * i386-dis.c (xop_table): Remove spurious bextr insn.
109 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
112 * i386-dis.c (print_insn): Optimize info->mach check.
114 2011-08-01 H.J. Lu <hongjiu.lu@intel.com>
117 * i386-opc.tbl: Add Disp32S to 64bit call.
118 * i386-tbl.h: Regenerated.
120 2011-07-24 Chao-ying Fu <fu@mips.com>
121 Maciej W. Rozycki <macro@codesourcery.com>
123 * micromips-opc.c: New file.
124 * mips-dis.c (micromips_to_32_reg_b_map): New array.
125 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
126 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
127 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
128 (micromips_to_32_reg_q_map): Likewise.
129 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
130 (micromips_ase): New variable.
131 (is_micromips): New function.
132 (set_default_mips_dis_options): Handle microMIPS ASE.
133 (print_insn_micromips): New function.
134 (is_compressed_mode_p): Likewise.
135 (_print_insn_mips): Handle microMIPS instructions.
136 * Makefile.am (CFILES): Add micromips-opc.c.
137 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
138 * Makefile.in: Regenerate.
139 * configure: Regenerate.
141 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
142 (micromips_to_32_reg_i_map): Likewise.
143 (micromips_to_32_reg_m_map): Likewise.
144 (micromips_to_32_reg_n_map): New macro.
146 2011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
148 * mips-opc.c (NODS): New macro.
149 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
150 (DSP_VOLA): Likewise.
151 (mips_builtin_opcodes): Add NODS annotation to "deret" and
152 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
153 place of TRAP for "wait", "waiti" and "yield".
154 * mips16-opc.c (NODS): New macro.
155 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
156 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
157 "restore" and "save".
159 2011-07-22 H.J. Lu <hongjiu.lu@intel.com>
161 * configure.in: Handle bfd_k1om_arch.
162 * configure: Regenerated.
164 * disassemble.c (disassembler): Handle bfd_k1om_arch.
166 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
167 bfd_mach_k1om_intel_syntax.
169 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
170 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
171 (cpu_flags): Add CpuK1OM.
173 * i386-opc.h (CpuK1OM): New.
174 (i386_cpu_flags): Add cpuk1om.
176 * i386-init.h: Regenerated.
177 * i386-tbl.h: Likewise.
179 2011-07-12 Nick Clifton <nickc@redhat.com>
181 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
184 2011-07-01 Nick Clifton <nickc@redhat.com>
187 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
188 insns using post-increment addressing.
190 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
192 * i386-dis.c (vex_len_table): Update rorxS.
194 2011-06-30 H.J. Lu <hongjiu.lu@intel.com>
196 AVX Programming Reference (June, 2011)
197 * i386-dis.c (vex_len_table): Correct rorxS.
199 * i386-opc.tbl: Correct rorx.
200 * i386-tbl.h: Regenerated.
202 2011-06-29 H.J. Lu <hongjiu.lu@intel.com>
204 * tilegx-opc.c (find_opcode): Replace "index" with "i".
205 * tilepro-opc.c (find_opcode): Likewise.
207 2011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
209 * mips16-opc.c (jalrc, jrc): Move earlier in file.
211 2011-06-21 H.J. Lu <hongjiu.lu@intel.com>
213 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
216 2011-06-17 Andreas Schwab <schwab@redhat.com>
218 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
219 (MOSTLYCLEANFILES): ... here.
220 * Makefile.in: Regenerate.
222 2011-06-14 Alan Modra <amodra@gmail.com>
224 * Makefile.in: Regenerate.
226 2011-06-13 Walter Lee <walt@tilera.com>
228 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
229 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
230 * Makefile.in: Regenerate.
231 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
232 * configure: Regenerate.
233 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
234 * po/POTFILES.in: Regenerate.
235 * tilegx-dis.c: New file.
236 * tilegx-opc.c: New file.
237 * tilepro-dis.c: New file.
238 * tilepro-opc.c: New file.
240 2011-06-10 H.J. Lu <hongjiu.lu@intel.com>
242 AVX Programming Reference (June, 2011)
243 * i386-dis.c (XMGatherQ): New.
244 * i386-dis.c (EXxmm_mb): New.
245 (EXxmm_mb): Likewise.
246 (EXxmm_mw): Likewise.
247 (EXxmm_md): Likewise.
248 (EXxmm_mq): Likewise.
251 (VexGatherQ): Likewise.
252 (MVexVSIBDWpX): Likewise.
253 (MVexVSIBQWpX): Likewise.
254 (xmm_mb_mode): Likewise.
255 (xmm_mw_mode): Likewise.
256 (xmm_md_mode): Likewise.
257 (xmm_mq_mode): Likewise.
258 (xmmdw_mode): Likewise.
259 (xmmqd_mode): Likewise.
260 (ymmxmm_mode): Likewise.
261 (vex_vsib_d_w_dq_mode): Likewise.
262 (vex_vsib_q_w_dq_mode): Likewise.
263 (MOD_VEX_0F385A_PREFIX_2): Likewise.
264 (MOD_VEX_0F388C_PREFIX_2): Likewise.
265 (MOD_VEX_0F388E_PREFIX_2): Likewise.
266 (PREFIX_0F3882): Likewise.
267 (PREFIX_VEX_0F3816): Likewise.
268 (PREFIX_VEX_0F3836): Likewise.
269 (PREFIX_VEX_0F3845): Likewise.
270 (PREFIX_VEX_0F3846): Likewise.
271 (PREFIX_VEX_0F3847): Likewise.
272 (PREFIX_VEX_0F3858): Likewise.
273 (PREFIX_VEX_0F3859): Likewise.
274 (PREFIX_VEX_0F385A): Likewise.
275 (PREFIX_VEX_0F3878): Likewise.
276 (PREFIX_VEX_0F3879): Likewise.
277 (PREFIX_VEX_0F388C): Likewise.
278 (PREFIX_VEX_0F388E): Likewise.
279 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
280 (PREFIX_VEX_0F38F5): Likewise.
281 (PREFIX_VEX_0F38F6): Likewise.
282 (PREFIX_VEX_0F3A00): Likewise.
283 (PREFIX_VEX_0F3A01): Likewise.
284 (PREFIX_VEX_0F3A02): Likewise.
285 (PREFIX_VEX_0F3A38): Likewise.
286 (PREFIX_VEX_0F3A39): Likewise.
287 (PREFIX_VEX_0F3A46): Likewise.
288 (PREFIX_VEX_0F3AF0): Likewise.
289 (VEX_LEN_0F3816_P_2): Likewise.
290 (VEX_LEN_0F3819_P_2): Likewise.
291 (VEX_LEN_0F3836_P_2): Likewise.
292 (VEX_LEN_0F385A_P_2_M_0): Likewise.
293 (VEX_LEN_0F38F5_P_0): Likewise.
294 (VEX_LEN_0F38F5_P_1): Likewise.
295 (VEX_LEN_0F38F5_P_3): Likewise.
296 (VEX_LEN_0F38F6_P_3): Likewise.
297 (VEX_LEN_0F38F7_P_1): Likewise.
298 (VEX_LEN_0F38F7_P_2): Likewise.
299 (VEX_LEN_0F38F7_P_3): Likewise.
300 (VEX_LEN_0F3A00_P_2): Likewise.
301 (VEX_LEN_0F3A01_P_2): Likewise.
302 (VEX_LEN_0F3A38_P_2): Likewise.
303 (VEX_LEN_0F3A39_P_2): Likewise.
304 (VEX_LEN_0F3A46_P_2): Likewise.
305 (VEX_LEN_0F3AF0_P_3): Likewise.
306 (VEX_W_0F3816_P_2): Likewise.
307 (VEX_W_0F3818_P_2): Likewise.
308 (VEX_W_0F3819_P_2): Likewise.
309 (VEX_W_0F3836_P_2): Likewise.
310 (VEX_W_0F3846_P_2): Likewise.
311 (VEX_W_0F3858_P_2): Likewise.
312 (VEX_W_0F3859_P_2): Likewise.
313 (VEX_W_0F385A_P_2_M_0): Likewise.
314 (VEX_W_0F3878_P_2): Likewise.
315 (VEX_W_0F3879_P_2): Likewise.
316 (VEX_W_0F3A00_P_2): Likewise.
317 (VEX_W_0F3A01_P_2): Likewise.
318 (VEX_W_0F3A02_P_2): Likewise.
319 (VEX_W_0F3A38_P_2): Likewise.
320 (VEX_W_0F3A39_P_2): Likewise.
321 (VEX_W_0F3A46_P_2): Likewise.
322 (MOD_VEX_0F3818_PREFIX_2): Removed.
323 (MOD_VEX_0F3819_PREFIX_2): Likewise.
324 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
325 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
326 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
327 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
328 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
329 (VEX_LEN_0F3A0E_P_2): Likewise.
330 (VEX_LEN_0F3A0F_P_2): Likewise.
331 (VEX_LEN_0F3A42_P_2): Likewise.
332 (VEX_LEN_0F3A4C_P_2): Likewise.
333 (VEX_W_0F3818_P_2_M_0): Likewise.
334 (VEX_W_0F3819_P_2_M_0): Likewise.
335 (prefix_table): Updated.
336 (three_byte_table): Likewise.
337 (vex_table): Likewise.
338 (vex_len_table): Likewise.
339 (vex_w_table): Likewise.
340 (mod_table): Likewise.
341 (putop): Handle "LW".
342 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
343 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
344 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
346 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
347 vex_vsib_q_w_dq_mode.
348 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
351 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
352 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
353 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
354 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
355 (opcode_modifiers): Add VecSIB.
357 * i386-opc.h (CpuAVX2): New.
359 (CpuLZCNT): Likewise.
360 (CpuINVPCID): Likewise.
361 (VecSIB128): Likewise.
362 (VecSIB256): Likewise.
364 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
365 (i386_opcode_modifier): Add vecsib.
367 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
368 * i386-init.h: Regenerated.
369 * i386-tbl.h: Likewise.
371 2011-06-03 Quentin Neill <quentin.neill@amd.com>
373 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
374 * i386-init.h: Regenerated.
376 2011-06-03 Nick Clifton <nickc@redhat.com>
379 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
380 computing address offsets.
381 (print_arm_address): Likewise.
382 (print_insn_arm): Likewise.
383 (print_insn_thumb16): Likewise.
384 (print_insn_thumb32): Likewise.
386 2011-06-02 Jie Zhang <jie@codesourcery.com>
387 Nathan Sidwell <nathan@codesourcery.com>
388 Maciej Rozycki <macro@codesourcery.com>
390 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
392 (print_arm_address): Likewise. Elide positive #0 appropriately.
393 (print_insn_arm): Likewise.
395 2011-06-02 Nick Clifton <nickc@redhat.com>
398 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
399 passed to print_address_func.
401 2011-06-02 Nick Clifton <nickc@redhat.com>
403 * arm-dis.c: Fix spelling mistakes.
404 * op/opcodes.pot: Regenerate.
406 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
408 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
409 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
410 * s390-opc.txt: Fix cxr instruction type.
412 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
414 * s390-opc.c: Add new instruction types marking register pair
416 * s390-opc.txt: Match instructions having register pair operands
417 to the new instruction types.
419 2011-05-19 Nick Clifton <nickc@redhat.com>
421 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
424 2011-05-10 Quentin Neill <quentin.neill@amd.com>
426 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
427 * i386-init.h: Regenerated.
429 2011-04-27 Nick Clifton <nickc@redhat.com>
431 * po/da.po: Updated Danish translation.
433 2011-04-26 Anton Blanchard <anton@samba.org>
435 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
437 2011-04-21 DJ Delorie <dj@redhat.com>
439 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
440 * rx-decode.c: Regenerate.
442 2011-04-20 H.J. Lu <hongjiu.lu@intel.com>
444 * i386-init.h: Regenerated.
446 2011-04-19 Quentin Neill <quentin.neill@amd.com>
448 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
451 2011-04-13 Nick Clifton <nickc@redhat.com>
453 * v850-dis.c (disassemble): Always print a closing square brace if
454 an opening square brace was printed.
456 2011-04-12 Nick Clifton <nickc@redhat.com>
459 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
461 (print_insn_thumb32): Handle %L.
463 2011-04-11 Julian Brown <julian@codesourcery.com>
465 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
466 (print_insn_thumb32): Add APSR bitmask support.
468 2011-04-07 Paul Carroll<pcarroll@codesourcery.com>
470 * arm-dis.c (print_insn): init vars moved into private_data structure.
472 2011-03-24 Mike Frysinger <vapier@gentoo.org>
474 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
476 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
478 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
479 post-increment to support LPM Z+ instruction. Add support for 'E'
480 constraint for DES instruction.
481 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
483 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
485 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
487 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
489 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
490 Use branch types instead.
491 (print_insn): Likewise.
493 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
495 * mips-opc.c (mips_builtin_opcodes): Correct register use
496 annotation of "alnv.ps".
498 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
500 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
502 2011-02-22 Mike Frysinger <vapier@gentoo.org>
504 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
506 2011-02-22 Mike Frysinger <vapier@gentoo.org>
508 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
510 2011-02-19 Mike Frysinger <vapier@gentoo.org>
512 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
513 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
514 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
515 exception, end_of_registers, msize, memory, bfd_mach.
516 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
517 LB0REG, LC1REG, LT1REG, LB1REG): Delete
518 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
519 (get_allreg): Change to new defines. Fallback to abort().
521 2011-02-14 Mike Frysinger <vapier@gentoo.org>
523 * bfin-dis.c: Add whitespace/parenthesis where needed.
525 2011-02-14 Mike Frysinger <vapier@gentoo.org>
527 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
530 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
532 * configure: Regenerate.
534 2011-02-13 Mike Frysinger <vapier@gentoo.org>
536 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
538 2011-02-13 Mike Frysinger <vapier@gentoo.org>
540 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
541 dregs only when P is set, and dregs_lo otherwise.
543 2011-02-13 Mike Frysinger <vapier@gentoo.org>
545 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
547 2011-02-12 Mike Frysinger <vapier@gentoo.org>
549 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
551 2011-02-12 Mike Frysinger <vapier@gentoo.org>
553 * bfin-dis.c (machine_registers): Delete REG_GP.
554 (reg_names): Delete "GP".
555 (decode_allregs): Change REG_GP to REG_LASTREG.
557 2011-02-12 Mike Frysinger <vapier@gentoo.org>
559 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
562 2011-02-11 Mike Frysinger <vapier@gentoo.org>
564 * bfin-dis.c (reg_names): Add const.
565 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
566 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
567 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
568 decode_counters, decode_allregs): Likewise.
570 2011-02-09 Michael Snyder <msnyder@vmware.com>
572 * i386-dis.c (OP_J): Parenthesize expression to prevent
574 (print_insn): Fix indentation off-by-one.
576 2011-02-01 Nick Clifton <nickc@redhat.com>
578 * po/da.po: Updated Danish translation.
580 2011-01-21 Dave Murphy <davem@devkitpro.org>
582 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
584 2011-01-18 H.J. Lu <hongjiu.lu@intel.com>
586 * i386-dis.c (sIbT): New.
587 (b_T_mode): Likewise.
588 (dis386): Replace sIb with sIbT on "pushT".
589 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
590 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
592 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
594 * i386-init.h: Regenerated.
595 * i386-tbl.h: Regenerated
597 2011-01-17 Quentin Neill <quentin.neill@amd.com>
599 * i386-dis.c (REG_XOP_TBM_01): New.
600 (REG_XOP_TBM_02): New.
601 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
602 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
603 entries, and add bextr instruction.
605 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
606 (cpu_flags): Add CpuTBM.
608 * i386-opc.h (CpuTBM) New.
609 (i386_cpu_flags): Add bit cputbm.
611 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
612 blcs, blsfill, blsic, t1mskc, and tzmsk.
614 2011-01-12 DJ Delorie <dj@redhat.com>
616 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
618 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
620 * mips-dis.c (print_insn_args): Adjust the value to print the real
621 offset for "+c" argument.
623 2011-01-10 Nick Clifton <nickc@redhat.com>
625 * po/da.po: Updated Danish translation.
627 2011-01-05 Nathan Sidwell <nathan@codesourcery.com>
629 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
631 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
633 * i386-dis.c (REG_VEX_38F3): New.
634 (PREFIX_0FBC): Likewise.
635 (PREFIX_VEX_38F2): Likewise.
636 (PREFIX_VEX_38F3_REG_1): Likewise.
637 (PREFIX_VEX_38F3_REG_2): Likewise.
638 (PREFIX_VEX_38F3_REG_3): Likewise.
639 (PREFIX_VEX_38F7): Likewise.
640 (VEX_LEN_38F2_P_0): Likewise.
641 (VEX_LEN_38F3_R_1_P_0): Likewise.
642 (VEX_LEN_38F3_R_2_P_0): Likewise.
643 (VEX_LEN_38F3_R_3_P_0): Likewise.
644 (VEX_LEN_38F7_P_0): Likewise.
645 (dis386_twobyte): Use PREFIX_0FBC.
646 (reg_table): Add REG_VEX_38F3.
647 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
648 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
649 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
650 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
652 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
653 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
656 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
657 (cpu_flags): Add CpuBMI.
659 * i386-opc.h (CpuBMI): New.
660 (i386_cpu_flags): Add cpubmi.
662 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
663 * i386-init.h: Regenerated.
664 * i386-tbl.h: Likewise.
666 2011-01-04 H.J. Lu <hongjiu.lu@intel.com>
668 * i386-dis.c (VexGdq): New.
669 (OP_VEX): Handle dq_mode.
671 2011-01-01 H.J. Lu <hongjiu.lu@intel.com>
673 * i386-gen.c (process_copyright): Update copyright to 2011.
675 For older changes see ChangeLog-2010
681 version-control: never