1 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
7 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
8 modified immediate group.
10 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15 * aarch64-tbl.h (QL_XLANES_FP_H): New.
16 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
17 fminnmv, fminv to the Adv.SIMD across lanes group.
19 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
21 * aarch64-asm-2.c: Regenerate.
22 * aarch64-dis-2.c: Regenerate.
23 * aarch64-opc-2.c: Regenerate.
24 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
25 fmls, fmul and fmulx to the scalar indexed element group.
27 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
29 * aarch64-asm-2.c: Regenerate.
30 * aarch64-dis-2.c: Regenerate.
31 * aarch64-opc-2.c: Regenerate.
32 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
33 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
34 fmulx to the vector indexed element group.
36 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
38 * aarch64-asm-2.c: Regenerate.
39 * aarch64-dis-2.c: Regenerate.
40 * aarch64-opc-2.c: Regenerate.
41 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
43 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
44 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
45 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
46 fcvtzu and frsqrte to the scalar two register misc. group.
48 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
50 * aarch64-asm-2.c: Regenerate.
51 * aarch64-dis-2.c: Regenerate.
52 * aarch64-opc-2.c: Regenerate.
53 * aarch64-tbl.h (QL_V2SAMEH): New.
54 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
55 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
56 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
57 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
58 and fsqrt to the vector register misc. group.
60 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
62 * aarch64-asm-2.c: Regenerate.
63 * aarch64-dis-2.c: Regenerate.
64 * aarch64-opc-2.c: Regenerate.
65 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
66 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
67 to the scalar three same group.
69 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
71 * aarch64-asm-2.c: Regenerate.
72 * aarch64-dis-2.c: Regenerate.
73 * aarch64-opc-2.c: Regenerate.
74 * aarch64-tbl.h (QL_V3SAMEH): New.
75 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
76 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
77 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
78 fcmgt, facgt and fminp to the vector three same group.
80 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
82 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
85 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
87 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
89 (aarch64_pstatefield_supported_p): Move feature checks for AT
91 (aarch64_sys_ins_reg_supported_p): .. to here.
93 2015-12-12 Alan Modra <amodra@gmail.com>
96 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
97 (powerpc_opcodes): Remove single-operand mfcr.
99 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
101 * aarch64-asm.c (aarch64_ins_hint): New.
102 * aarch64-asm.h (aarch64_ins_hint): Declare.
103 * aarch64-dis.c (aarch64_ext_hint): New.
104 * aarch64-dis.h (aarch64_ext_hint): Declare.
105 * aarch64-opc-2.c: Regenerate.
106 * aarch64-opc.c (aarch64_hint_options): New.
107 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
109 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
111 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
113 2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
115 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
116 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
117 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
119 (aarch64_sys_reg_supported_p): Add architecture feature tests for
122 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
124 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
125 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
126 feature test for "s1e1rp" and "s1e1wp".
128 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
130 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
131 (aarch64_sys_ins_reg_supported_p): New.
133 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
135 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
136 with aarch64_sys_ins_reg_has_xt.
137 (aarch64_ext_sysins_op): Likewise.
138 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
140 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
141 (aarch64_sys_regs_dc): Likewise.
142 (aarch64_sys_regs_at): Likewise.
143 (aarch64_sys_regs_tlbi): Likewise.
144 (aarch64_sys_ins_reg_has_xt): New.
146 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
148 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
149 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
150 (aarch64_pstatefields): Add "uao".
151 (aarch64_pstatefield_supported_p): Add checks for "uao".
153 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
155 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
156 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
157 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
158 (aarch64_sys_reg_supported_p): Add architecture feature tests for
161 2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
163 * aarch64-asm-2.c: Regenerate.
164 * aarch64-dis-2.c: Regenerate.
165 * aarch64-tbl.h (aarch64_feature_ras): New.
167 (aarch64_opcode_table): Add "esb".
169 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
171 * i386-dis.c (MOD_0F01_REG_5): New.
172 (RM_0F01_REG_5): Likewise.
173 (reg_table): Use MOD_0F01_REG_5.
174 (mod_table): Add MOD_0F01_REG_5.
175 (rm_table): Add RM_0F01_REG_5.
176 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
177 (cpu_flags): Add CpuOSPKE.
178 * i386-opc.h (CpuOSPKE): New.
179 (i386_cpu_flags): Add cpuospke.
180 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
181 * i386-init.h: Regenerated.
182 * i386-tbl.h: Likewise.
184 2015-12-07 DJ Delorie <dj@redhat.com>
186 * rl78-decode.opc: Enable MULU for all ISAs.
187 * rl78-decode.c: Regenerate.
189 2015-12-07 Alan Modra <amodra@gmail.com>
191 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
194 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
196 * arc-dis.c (special_flag_p): Match full mnemonic.
197 * arc-opc.c (print_insn_arc): Check section size to read
198 appropriate number of bytes. Fix printing.
199 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
202 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
204 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
207 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
209 * aarch64-asm-2.c: Regenerate.
210 * aarch64-dis-2.c: Regenerate.
211 * aarch64-opc-2.c: Regenerate.
212 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
213 (QL_INT2FP_H, QL_FP2INT_H): New.
214 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
217 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
218 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
219 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
220 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
221 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
222 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
225 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
227 * aarch64-opc.c (half_conv_t): New.
228 (expand_fp_imm): Replace is_dp flag with the parameter size to
229 specify the number of bytes for the required expansion. Treat
230 a 16-bit expansion like a 32-bit expansion. Add check for an
231 unsupported size request. Update comment.
232 (aarch64_print_operand): Update to support 16-bit floating point
233 values. Update for changes to expand_fp_imm.
235 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
237 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
240 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
242 * aarch64-asm-2.c: Regenerate.
243 * aarch64-dis-2.c: Regenerate.
244 * aarch64-opc-2.c: Regenerate.
245 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
248 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
250 * aarch64-asm-2.c: Regenerate.
251 * aarch64-asm.c (convert_bfc_to_bfm): New.
252 (convert_to_real): Add case for OP_BFC.
253 * aarch64-dis-2.c: Regenerate.
254 * aarch64-dis.c: (convert_bfm_to_bfc): New.
255 (convert_to_alias): Add case for OP_BFC.
256 * aarch64-opc-2.c: Regenerate.
257 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
258 to allow width operand in three-operand instructions.
259 * aarch64-tbl.h (QL_BF1): New.
260 (aarch64_feature_v8_2): New.
262 (aarch64_opcode_table): Add "bfc".
264 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
266 * aarch64-asm-2.c: Regenerate.
267 * aarch64-dis-2.c: Regenerate.
268 * aarch64-dis.c: Weaken assert.
269 * aarch64-gen.c: Include the instruction in the list of its
272 2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
274 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
275 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
278 2015-11-23 Tristan Gingold <gingold@adacore.com>
280 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
282 2015-11-20 Matthew Wahab <matthew.wahab@arm.com>
284 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
285 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
286 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
287 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
288 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
289 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
290 cnthv_ctl_el2, cnthv_cval_el2.
291 (aarch64_sys_reg_supported_p): Update for the new system
294 2015-11-20 Nick Clifton <nickc@redhat.com>
297 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
299 2015-11-20 Nick Clifton <nickc@redhat.com>
301 * po/zh_CN.po: Updated simplified Chinese translation.
303 2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
305 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
306 of MSR PAN immediate operand.
308 2015-11-16 Nick Clifton <nickc@redhat.com>
310 * rx-dis.c (condition_names): Replace always and never with
311 invalid, since the always/never conditions can never be legal.
313 2015-11-13 Tristan Gingold <gingold@adacore.com>
315 * configure: Regenerate.
317 2015-11-11 Alan Modra <amodra@gmail.com>
318 Peter Bergner <bergner@vnet.ibm.com>
320 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
321 Add PPC_OPCODE_VSX3 to the vsx entry.
322 (powerpc_init_dialect): Set default dialect to power9.
323 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
324 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
325 extract_l1 insert_xtq6, extract_xtq6): New static functions.
326 (insert_esync): Test for illegal L operand value.
327 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
328 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
329 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
330 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
331 PPCVSX3): New defines.
332 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
333 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
334 <mcrxr>: Use XBFRARB_MASK.
335 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
336 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
337 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
338 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
339 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
340 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
341 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
342 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
343 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
344 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
345 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
346 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
347 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
348 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
349 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
350 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
351 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
352 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
353 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
354 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
355 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
356 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
357 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
358 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
359 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
360 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
361 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
362 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
363 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
364 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
365 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
366 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
368 2015-11-02 Nick Clifton <nickc@redhat.com>
370 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
372 * rx-decode.c: Regenerate.
374 2015-11-02 Nick Clifton <nickc@redhat.com>
376 * rx-decode.opc (rx_disp): If the displacement is zero, set the
377 type to RX_Operand_Zero_Indirect.
378 * rx-decode.c: Regenerate.
379 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
381 2015-10-28 Yao Qi <yao.qi@linaro.org>
383 * aarch64-dis.c (aarch64_decode_insn): Add one argument
384 noaliases_p. Update comments. Pass noaliases_p rather than
385 no_aliases to aarch64_opcode_decode.
386 (print_insn_aarch64_word): Pass no_aliases to
389 2015-10-27 Vinay <Vinay.G@kpit.com>
392 * rl78-decode.opc (MOV): Added offset to DE register in index
394 * rl78-decode.c: Regenerate.
396 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
399 * rl78-decode.opc: Add 's' print operator to instructions that
400 access system registers.
401 * rl78-decode.c: Regenerate.
402 * rl78-dis.c (print_insn_rl78_common): Decode all system
405 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
408 * rl78-decode.opc: Add 'a' print operator to mov instructions
409 using stack pointer plus index addressing.
410 * rl78-decode.c: Regenerate.
412 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
414 * s390-opc.c: Fix comment.
415 * s390-opc.txt: Change instruction type for troo, trot, trto, and
416 trtt to RRF_U0RER since the second parameter does not need to be a
419 2015-10-08 Nick Clifton <nickc@redhat.com>
421 * arc-dis.c (print_insn_arc): Initiallise insn array.
423 2015-10-07 Yao Qi <yao.qi@linaro.org>
425 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
426 'name' rather than 'template'.
427 * aarch64-opc.c (aarch64_print_operand): Likewise.
429 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
431 * arc-dis.c: Revamped file for ARC support
432 * arc-dis.h: Likewise.
433 * arc-ext.c: Likewise.
434 * arc-ext.h: Likewise.
435 * arc-opc.c: Likewise.
436 * arc-fxi.h: New file.
437 * arc-regs.h: Likewise.
438 * arc-tbl.h: Likewise.
440 2015-10-02 Yao Qi <yao.qi@linaro.org>
442 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
443 argument insn type to aarch64_insn. Rename to ...
444 (aarch64_decode_insn): ... it.
445 (print_insn_aarch64_word): Caller updated.
447 2015-10-02 Yao Qi <yao.qi@linaro.org>
449 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
450 (print_insn_aarch64_word): Caller updated.
452 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
454 * s390-mkopc.c (main): Parse htm and vx flag.
455 * s390-opc.txt: Mark instructions from the hardware transactional
456 memory and vector facilities with the "htm"/"vx" flag.
458 2015-09-28 Nick Clifton <nickc@redhat.com>
460 * po/de.po: Updated German translation.
462 2015-09-28 Tom Rix <tom@bumblecow.com>
464 * ppc-opc.c (PPC500): Mark some opcodes as invalid
466 2015-09-23 Nick Clifton <nickc@redhat.com>
468 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
470 * tic30-dis.c (print_branch): Likewise.
471 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
472 value before left shifting.
473 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
474 * hppa-dis.c (print_insn_hppa): Likewise.
475 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
477 * msp430-dis.c (msp430_singleoperand): Likewise.
478 (msp430_doubleoperand): Likewise.
479 (print_insn_msp430): Likewise.
480 * nds32-asm.c (parse_operand): Likewise.
481 * sh-opc.h (MASK): Likewise.
482 * v850-dis.c (get_operand_value): Likewise.
484 2015-09-22 Nick Clifton <nickc@redhat.com>
486 * rx-decode.opc (bwl): Use RX_Bad_Size.
488 (ubwl): Likewise. Rename to ubw.
489 (uBWL): Rename to uBW.
490 Replace all references to uBWL with uBW.
491 * rx-decode.c: Regenerate.
492 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
493 (opsize_names): Likewise.
494 (print_insn_rx): Detect and report RX_Bad_Size.
496 2015-09-22 Anton Blanchard <anton@samba.org>
498 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
500 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
502 * sparc-dis.c (print_insn_sparc): Handle the privileged register
505 2015-08-24 Jan Stancek <jstancek@redhat.com>
507 * i386-dis.c (print_insn): Fix decoding of three byte operands.
509 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
512 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
513 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
514 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
515 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
516 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
517 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
518 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
519 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
520 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
521 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
522 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
523 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
524 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
525 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
526 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
527 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
528 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
529 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
530 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
531 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
532 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
533 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
534 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
535 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
536 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
537 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
538 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
539 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
540 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
541 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
542 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
543 (vex_w_table): Replace terminals with MOD_TABLE entries for
544 most of mask instructions.
546 2015-08-17 Alan Modra <amodra@gmail.com>
548 * cgen.sh: Trim trailing space from cgen output.
549 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
550 (print_dis_table): Likewise.
551 * opc2c.c (dump_lines): Likewise.
552 (orig_filename): Warning fix.
553 * ia64-asmtab.c: Regenerate.
555 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
557 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
558 and higher with ARM instruction set will now mark the 26-bit
559 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
560 (arm_opcodes): Fix for unpredictable nop being recognized as a
563 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
565 * micromips-opc.c (micromips_opcodes): Re-order table so that move
566 based on 'or' is first.
567 * mips-opc.c (mips_builtin_opcodes): Ditto.
569 2015-08-11 Nick Clifton <nickc@redhat.com>
572 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
575 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
577 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
579 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
581 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
582 * i386-init.h: Regenerated.
584 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
587 * i386-dis.c (MOD_0FC3): New.
588 (PREFIX_0FC3): Renamed to ...
589 (PREFIX_MOD_0_0FC3): This.
590 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
591 (prefix_table): Replace Ma with Ev on movntiS.
592 (mod_table): Add MOD_0FC3.
594 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
596 * configure: Regenerated.
598 2015-07-23 Alan Modra <amodra@gmail.com>
601 * i386-dis.c (get64): Avoid signed integer overflow.
603 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
606 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
607 "EXEvexHalfBcstXmmq" for the second operand.
608 (EVEX_W_0F79_P_2): Likewise.
609 (EVEX_W_0F7A_P_2): Likewise.
610 (EVEX_W_0F7B_P_2): Likewise.
612 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
614 * arm-dis.c (print_insn_coprocessor): Added support for quarter
615 float bitfield format.
616 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
617 quarter float bitfield format.
619 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
621 * configure: Regenerated.
623 2015-07-03 Alan Modra <amodra@gmail.com>
625 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
626 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
627 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
629 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
630 Cesar Philippidis <cesar@codesourcery.com>
632 * nios2-dis.c (nios2_extract_opcode): New.
633 (nios2_disassembler_state): New.
634 (nios2_find_opcode_hash): Use mach parameter to select correct
636 (nios2_print_insn_arg): Extend to support new R2 argument letters
638 (print_insn_nios2): Check for 16-bit instruction at end of memory.
639 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
640 (NIOS2_NUM_OPCODES): Rename to...
641 (NIOS2_NUM_R1_OPCODES): This.
642 (nios2_r2_opcodes): New.
643 (NIOS2_NUM_R2_OPCODES): New.
644 (nios2_num_r2_opcodes): New.
645 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
646 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
647 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
648 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
649 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
651 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
653 * i386-dis.c (OP_Mwaitx): New.
654 (rm_table): Add monitorx/mwaitx.
655 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
656 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
657 (operand_type_init): Add CpuMWAITX.
658 * i386-opc.h (CpuMWAITX): New.
659 (i386_cpu_flags): Add cpumwaitx.
660 * i386-opc.tbl: Add monitorx and mwaitx.
661 * i386-init.h: Regenerated.
662 * i386-tbl.h: Likewise.
664 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
666 * ppc-opc.c (insert_ls): Test for invalid LS operands.
667 (insert_esync): New function.
668 (LS, WC): Use insert_ls.
669 (ESYNC): Use insert_esync.
671 2015-06-22 Nick Clifton <nickc@redhat.com>
673 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
674 requested region lies beyond it.
675 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
676 looking for 32-bit insns.
677 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
679 * sh-dis.c (print_insn_sh): Likewise.
680 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
681 blocks of instructions.
682 * vax-dis.c (print_insn_vax): Check that the requested address
683 does not clash with the stop_vma.
685 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
687 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
688 * ppc-opc.c (FXM4): Add non-zero optional value.
691 (insert_fxm): Handle new default operand value.
692 (extract_fxm): Likewise.
693 (insert_tbr): Likewise.
694 (extract_tbr): Likewise.
696 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
698 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
700 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
702 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
704 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
706 * ppc-opc.c: Add comment accidentally removed by old commit.
709 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
711 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
713 2015-06-04 Nick Clifton <nickc@redhat.com>
716 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
718 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
720 * arm-dis.c (arm_opcodes): Add "setpan".
721 (thumb_opcodes): Add "setpan".
723 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
725 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
728 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
730 * aarch64-tbl.h (aarch64_feature_rdma): New.
732 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
733 * aarch64-asm-2.c: Regenerate.
734 * aarch64-dis-2.c: Regenerate.
735 * aarch64-opc-2.c: Regenerate.
737 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
739 * aarch64-tbl.h (aarch64_feature_lor): New.
741 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
743 * aarch64-asm-2.c: Regenerate.
744 * aarch64-dis-2.c: Regenerate.
745 * aarch64-opc-2.c: Regenerate.
747 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
749 * aarch64-opc.c (F_ARCHEXT): New.
750 (aarch64_sys_regs): Add "pan".
751 (aarch64_sys_reg_supported_p): New.
752 (aarch64_pstatefields): Add "pan".
753 (aarch64_pstatefield_supported_p): New.
755 2015-06-01 Jan Beulich <jbeulich@suse.com>
757 * i386-tbl.h: Regenerate.
759 2015-06-01 Jan Beulich <jbeulich@suse.com>
761 * i386-dis.c (print_insn): Swap rounding mode specifier and
762 general purpose register in Intel mode.
764 2015-06-01 Jan Beulich <jbeulich@suse.com>
766 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
767 * i386-tbl.h: Regenerate.
769 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
771 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
772 * i386-init.h: Regenerated.
774 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
777 * i386-dis.c: Add comments for '@'.
778 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
779 (enum x86_64_isa): New.
781 (print_i386_disassembler_options): Add amd64 and intel64.
782 (print_insn): Handle amd64 and intel64.
784 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
785 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
786 * i386-opc.h (AMD64): New.
787 (CpuIntel64): Likewise.
788 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
789 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
790 Mark direct call/jmp without Disp16|Disp32 as Intel64.
791 * i386-init.h: Regenerated.
792 * i386-tbl.h: Likewise.
794 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
796 * ppc-opc.c (IH) New define.
797 (powerpc_opcodes) <wait>: Do not enable for POWER7.
798 <tlbie>: Add RS operand for POWER7.
799 <slbia>: Add IH operand for POWER6.
801 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
803 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
806 * i386-tbl.h: Regenerated.
808 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
810 * configure.ac: Support bfd_iamcu_arch.
811 * disassemble.c (disassembler): Support bfd_iamcu_arch.
812 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
813 CPU_IAMCU_COMPAT_FLAGS.
814 (cpu_flags): Add CpuIAMCU.
815 * i386-opc.h (CpuIAMCU): New.
816 (i386_cpu_flags): Add cpuiamcu.
817 * configure: Regenerated.
818 * i386-init.h: Likewise.
819 * i386-tbl.h: Likewise.
821 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
824 * i386-dis.c (X86_64_E8): New.
825 (X86_64_E9): Likewise.
826 Update comments on 'T', 'U', 'V'. Add comments for '^'.
827 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
828 (x86_64_table): Add X86_64_E8 and X86_64_E9.
829 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
831 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
834 2015-04-30 DJ Delorie <dj@redhat.com>
836 * disassemble.c (disassembler): Choose suitable disassembler based
838 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
839 it to decode mul/div insns.
840 * rl78-decode.c: Regenerate.
841 * rl78-dis.c (print_insn_rl78): Rename to...
842 (print_insn_rl78_common): ...this, take ISA parameter.
843 (print_insn_rl78): New.
844 (print_insn_rl78_g10): New.
845 (print_insn_rl78_g13): New.
846 (print_insn_rl78_g14): New.
847 (rl78_get_disassembler): New.
849 2015-04-29 Nick Clifton <nickc@redhat.com>
851 * po/fr.po: Updated French translation.
853 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
855 * ppc-opc.c (DCBT_EO): New define.
856 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
860 <waitrsv>: Do not enable for POWER7 and later.
861 <waitimpl>: Likewise.
862 <dcbt>: Default to the two operand form of the instruction for all
863 "old" cpus. For "new" cpus, use the operand ordering that matches
864 whether the cpu is server or embedded.
867 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
869 * s390-opc.c: New instruction type VV0UU2.
870 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
873 2015-04-23 Jan Beulich <jbeulich@suse.com>
875 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
876 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
877 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
878 (vfpclasspd, vfpclassps): Add %XZ.
880 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
882 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
883 (PREFIX_UD_REPZ): Likewise.
884 (PREFIX_UD_REPNZ): Likewise.
885 (PREFIX_UD_DATA): Likewise.
886 (PREFIX_UD_ADDR): Likewise.
887 (PREFIX_UD_LOCK): Likewise.
889 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
891 * i386-dis.c (prefix_requirement): Removed.
892 (print_insn): Don't set prefix_requirement. Check
893 dp->prefix_requirement instead of prefix_requirement.
895 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
898 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
899 (PREFIX_MOD_0_0FC7_REG_6): This.
900 (PREFIX_MOD_3_0FC7_REG_6): New.
901 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
902 (prefix_table): Replace PREFIX_0FC7_REG_6 with
903 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
904 PREFIX_MOD_3_0FC7_REG_7.
905 (mod_table): Replace PREFIX_0FC7_REG_6 with
906 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
907 PREFIX_MOD_3_0FC7_REG_7.
909 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
911 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
912 (PREFIX_MANDATORY_REPNZ): Likewise.
913 (PREFIX_MANDATORY_DATA): Likewise.
914 (PREFIX_MANDATORY_ADDR): Likewise.
915 (PREFIX_MANDATORY_LOCK): Likewise.
916 (PREFIX_MANDATORY): Likewise.
917 (PREFIX_UD_SHIFT): Set to 8
918 (PREFIX_UD_REPZ): Updated.
919 (PREFIX_UD_REPNZ): Likewise.
920 (PREFIX_UD_DATA): Likewise.
921 (PREFIX_UD_ADDR): Likewise.
922 (PREFIX_UD_LOCK): Likewise.
923 (PREFIX_IGNORED_SHIFT): New.
924 (PREFIX_IGNORED_REPZ): Likewise.
925 (PREFIX_IGNORED_REPNZ): Likewise.
926 (PREFIX_IGNORED_DATA): Likewise.
927 (PREFIX_IGNORED_ADDR): Likewise.
928 (PREFIX_IGNORED_LOCK): Likewise.
929 (PREFIX_OPCODE): Likewise.
930 (PREFIX_IGNORED): Likewise.
931 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
932 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
933 (three_byte_table): Likewise.
934 (mod_table): Likewise.
935 (mandatory_prefix): Renamed to ...
936 (prefix_requirement): This.
937 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
938 Update PREFIX_90 entry.
939 (get_valid_dis386): Check prefix_requirement to see if a prefix
941 (print_insn): Replace mandatory_prefix with prefix_requirement.
943 2015-04-15 Renlin Li <renlin.li@arm.com>
945 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
946 use it for ssat and ssat16.
947 (print_insn_thumb32): Add handle case for 'D' control code.
949 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
950 H.J. Lu <hongjiu.lu@intel.com>
952 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
953 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
954 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
955 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
956 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
957 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
958 Fill prefix_requirement field.
959 (struct dis386): Add prefix_requirement field.
960 (dis386): Fill prefix_requirement field.
961 (dis386_twobyte): Ditto.
962 (twobyte_has_mandatory_prefix_: Remove.
963 (reg_table): Fill prefix_requirement field.
964 (prefix_table): Ditto.
965 (x86_64_table): Ditto.
966 (three_byte_table): Ditto.
969 (vex_len_table): Ditto.
970 (vex_w_table): Ditto.
973 (print_insn): Use prefix_requirement.
974 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
975 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
978 2015-03-30 Mike Frysinger <vapier@gentoo.org>
980 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
982 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
984 * Makefile.in: Regenerated.
986 2015-03-25 Anton Blanchard <anton@samba.org>
988 * ppc-dis.c (disassemble_init_powerpc): Only initialise
989 powerpc_opcd_indices and vle_opcd_indices once.
991 2015-03-25 Anton Blanchard <anton@samba.org>
993 * ppc-opc.c (powerpc_opcodes): Add slbfee.
995 2015-03-24 Terry Guo <terry.guo@arm.com>
997 * arm-dis.c (opcode32): Updated to use new arm feature struct.
998 (opcode16): Likewise.
999 (coprocessor_opcodes): Replace bit with feature struct.
1000 (neon_opcodes): Likewise.
1001 (arm_opcodes): Likewise.
1002 (thumb_opcodes): Likewise.
1003 (thumb32_opcodes): Likewise.
1004 (print_insn_coprocessor): Likewise.
1005 (print_insn_arm): Likewise.
1006 (select_arm_features): Follow new feature struct.
1008 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1010 * i386-dis.c (rm_table): Add clzero.
1011 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1012 Add CPU_CLZERO_FLAGS.
1013 (cpu_flags): Add CpuCLZERO.
1014 * i386-opc.h: Add CpuCLZERO.
1015 * i386-opc.tbl: Add clzero.
1016 * i386-init.h: Re-generated.
1017 * i386-tbl.h: Re-generated.
1019 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1021 * mips-opc.c (decode_mips_operand): Fix constraint issues
1022 with u and y operands.
1024 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1026 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1028 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1030 * s390-opc.c: Add new IBM z13 instructions.
1031 * s390-opc.txt: Likewise.
1033 2015-03-10 Renlin Li <renlin.li@arm.com>
1035 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1036 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1038 * aarch64-asm-2.c: Regenerate.
1039 * aarch64-dis-2.c: Likewise.
1040 * aarch64-opc-2.c: Likewise.
1042 2015-03-03 Jiong Wang <jiong.wang@arm.com>
1044 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1046 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1048 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1050 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1051 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1053 2015-02-23 Vinay <Vinay.G@kpit.com>
1055 * rl78-decode.opc (MOV): Added space between two operands for
1056 'mov' instruction in index addressing mode.
1057 * rl78-decode.c: Regenerate.
1059 2015-02-19 Pedro Alves <palves@redhat.com>
1061 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1063 2015-02-10 Pedro Alves <palves@redhat.com>
1064 Tom Tromey <tromey@redhat.com>
1066 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1067 microblaze_and, microblaze_xor.
1068 * microblaze-opc.h (opcodes): Adjust.
1070 2015-01-28 James Bowman <james.bowman@ftdichip.com>
1072 * Makefile.am: Add FT32 files.
1073 * configure.ac: Handle FT32.
1074 * disassemble.c (disassembler): Call print_insn_ft32.
1075 * ft32-dis.c: New file.
1076 * ft32-opc.c: New file.
1077 * Makefile.in: Regenerate.
1078 * configure: Regenerate.
1079 * po/POTFILES.in: Regenerate.
1081 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1083 * nds32-asm.c (keyword_sr): Add new system registers.
1085 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1087 * s390-dis.c (s390_extract_operand): Support vector register
1089 (s390_print_insn_with_opcode): Support new operands types and add
1090 new handling of optional operands.
1091 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1092 and include opcode/s390.h instead.
1093 (struct op_struct): New field `flags'.
1094 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1095 (dumpTable): Dump flags.
1096 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1098 * s390-opc.c: Add new operands types, instruction formats, and
1100 (s390_opformats): Add new formats for .insn.
1101 * s390-opc.txt: Add new instructions.
1103 2015-01-01 Alan Modra <amodra@gmail.com>
1105 Update year range in copyright notice of all files.
1107 For older changes see ChangeLog-2014
1109 Copyright (C) 2015 Free Software Foundation, Inc.
1111 Copying and distribution of this file, with or without modification,
1112 are permitted in any medium without royalty provided the copyright
1113 notice and this notice are preserved.
1119 version-control: never