1 2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
3 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
4 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
5 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
8 (micromips_opcodes): Add MSA instructions.
9 * mips-dis.c (msa_control_names): New array.
10 (mips_abi_choice): Add ASE_MSA to mips32r2.
11 Remove ASE_MDMX from mips64r2.
12 Add ASE_MSA and ASE_MSA64 to mips64r2.
13 (parse_mips_dis_option): Handle -Mmsa.
14 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
15 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
16 (print_mips_disassembler_options): Print -Mmsa.
17 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
18 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
21 (mips_builtin_op): Add MSA instructions.
23 2013-10-13 Sandra Loosemore <sandra@codesourcery.com>
25 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
26 as the primary name of r30.
28 2013-10-12 Jan Beulich <jbeulich@suse.com>
30 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
32 (OP_E_register): Move v_bnd_mode alongside m_mode.
33 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
34 Drop Reg16 and Disp16. Add NoRex64.
35 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
36 * i386-tbl.h: Re-generate.
38 2013-10-10 Sean Keys <skeys@ipdatasys.com>
40 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
42 * xgate-dis.c (print_insn): Refactor to work with table change.
44 2013-10-10 Roland McGrath <mcgrathr@google.com>
46 * i386-dis.c (oappend_maybe_intel): New function.
47 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
48 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
49 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
51 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
52 possible compiler warnings when the union's initializer is
53 actually meant for the 'preg' enum typed member.
54 * crx-opc.c (REG): Likewise.
56 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
57 Remove duplicate const qualifier.
59 2013-10-08 Jan Beulich <jbeulich@suse.com>
61 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
62 (clflush): Use Anysize instead of Byte|Unspecified.
63 (prefetch*): Likewise.
64 * i386-tbl.h: Re-generate.
66 2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
68 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
70 2013-09-30 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
73 * i386-init.h: Regenerated.
75 2013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
77 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
78 * i386-init.h: Regenerated.
80 2013-09-20 Alan Modra <amodra@gmail.com>
82 * configure: Regenerate.
84 2013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
86 * s390-opc.txt (clih): Make the immediate unsigned.
88 2013-09-04 Roland McGrath <mcgrathr@google.com>
91 * arm-dis.c (arm_opcodes): Add udf.
92 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
93 (thumb32_opcodes): Add udf.w.
94 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
96 2013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
98 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
99 For the load fp integer instructions only the suppression flag was
100 new with z196 version.
102 2013-08-28 Nick Clifton <nickc@redhat.com>
104 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
105 immediate is not suitable for the 32-bit ABI.
107 2013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
109 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
112 2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
115 * aarch64-asm.c: Fix typos.
116 * aarch64-dis.c: Likewise.
117 * msp430-dis.c: Likewise.
119 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
121 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
122 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
123 Use +H rather than +C for the real "dext".
124 * mips-opc.c (mips_builtin_opcodes): Likewise.
126 2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
128 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
129 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
130 and OPTIONAL_MAPPED_REG.
131 * mips-opc.c (decode_mips_operand): Likewise.
132 * mips16-opc.c (decode_mips16_operand): Likewise.
133 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
135 2013-08-19 H.J. Lu <hongjiu.lu@intel.com>
137 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
138 (PREFIX_EVEX_0F3A3F): Likewise.
139 * i386-dis-evex.h (evex_table): Updated.
141 2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
143 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
146 2013-08-05 Eric Botcazou <ebotcazou@adacore.com>
147 Konrad Eisele <konrad@gaisler.com>
149 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
151 * sparc-opc.c (MASK_LEON): Define.
152 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
153 (letandleon): New macro.
154 (v9andleon): Likewise.
155 (sparc_opc): Add leon.
156 (umac): Enable for letandleon.
158 (casa): Enable for v9andleon.
162 2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
163 Richard Sandiford <rdsandiford@googlemail.com>
165 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
166 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
167 (print_vu0_channel): New function.
168 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
169 (print_insn_args): Handle '#'.
170 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
171 * mips-opc.c (mips_vu0_channel_mask): New constant.
172 (decode_mips_operand): Handle new VU0 operand types.
173 (VU0, VU0CH): New macros.
174 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
175 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
176 Use "+6" rather than "G" for QMFC2 and QMTC2.
178 2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
180 * mips-formats.h (PCREL): Reorder parameters and update the definition
181 to match new mips_pcrel_operand layout.
182 (JUMP, JALX, BRANCH): Update accordingly.
183 * mips16-opc.c (decode_mips16_operand): Likewise.
185 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
187 * micromips-opc.c (WR_s): Delete.
189 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
191 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
193 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
194 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
195 (mips_builtin_opcodes): Use the new position-based read-write flags
196 instead of field-based ones. Use UDI for "udi..." instructions.
197 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
199 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
200 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
201 (WR_SP, RD_16): New macros.
202 (RD_SP): Redefine as an INSN2_* flag.
203 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
204 (mips16_opcodes): Use the new position-based read-write flags
205 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
207 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
209 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
210 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
211 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
212 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
213 (micromips_opcodes): Use the new position-based read-write flags
214 instead of field-based ones.
215 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
216 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
217 of field-based flags.
219 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
221 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
222 (WR_SP): Replace with...
224 (mips16_opcodes): Update accordingly.
225 * mips-dis.c (print_insn_mips16): Likewise.
227 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
229 * mips16-opc.c (mips16_opcodes): Reformat.
231 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
233 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
234 for operands that are hard-coded to $0.
235 * micromips-opc.c (micromips_opcodes): Likewise.
237 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
239 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
240 for the single-operand forms of JALR and JALR.HB.
241 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
244 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
246 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
247 instructions. Fix them to use WR_MACC instead of WR_CC and
248 add missing RD_MACCs.
250 2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
252 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
254 2013-07-29 Peter Bergner <bergner@vnet.ibm.com>
256 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
258 2013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
259 Alexander Ivchenko <alexander.ivchenko@intel.com>
260 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
261 Sergey Lega <sergey.s.lega@intel.com>
262 Anna Tikhonova <anna.tikhonova@intel.com>
263 Ilya Tocar <ilya.tocar@intel.com>
264 Andrey Turetskiy <andrey.turetskiy@intel.com>
265 Ilya Verbin <ilya.verbin@intel.com>
266 Kirill Yukhin <kirill.yukhin@intel.com>
267 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
269 * i386-dis-evex.h: New.
270 * i386-dis.c (OP_Rounding): New.
277 (EXEvexHalfBcstXmmq): New.
280 (EXEvexXNoBcst): New.
289 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
290 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
291 evex_rounding_mode, evex_sae_mode, mask_mode.
292 (USE_EVEX_TABLE): New.
295 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
297 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
298 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
299 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
300 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
301 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
302 MOD_EVEX_0F38C7_REG_6.
303 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
304 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
305 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
306 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
307 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
308 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
309 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
310 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
311 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
312 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
313 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
314 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
315 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
316 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
317 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
318 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
319 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
320 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
321 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
322 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
323 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
324 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
325 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
326 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
327 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
328 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
329 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
330 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
331 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
332 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
333 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
334 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
335 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
336 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
337 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
338 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
339 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
340 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
341 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
342 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
343 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
344 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
345 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
346 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
347 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
348 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
349 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
350 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
351 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
352 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
353 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
354 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
355 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
356 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
357 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
358 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
359 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
360 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
361 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
362 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
363 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
364 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
365 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
366 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
367 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
368 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
369 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
370 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
371 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
372 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
373 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
374 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
375 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
376 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
377 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
378 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
380 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
381 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
382 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
383 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
384 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
385 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
386 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
387 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
388 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
389 VEX_W_0F3A32_P_2_LEN_0.
390 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
391 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
392 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
393 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
394 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
395 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
396 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
397 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
398 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
399 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
400 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
401 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
402 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
403 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
404 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
405 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
406 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
407 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
408 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
409 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
410 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
411 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
412 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
413 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
414 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
415 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
416 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
417 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
418 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
419 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
420 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
421 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
422 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
423 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
424 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
425 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
426 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
427 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
428 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
429 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
430 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
431 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
432 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
433 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
434 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
435 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
436 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
437 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
438 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
439 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
440 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
441 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
442 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
443 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
444 (struct vex): Add fields evex, r, v, mask_register_specifier,
446 (intel_names_xmm): Add upper 16 registers.
447 (att_names_xmm): Ditto.
448 (intel_names_ymm): Ditto.
449 (att_names_ymm): Ditto.
451 (intel_names_zmm): Ditto.
452 (att_names_zmm): Ditto.
454 (intel_names_mask): Ditto.
455 (att_names_mask): Ditto.
456 (names_rounding): Ditto.
457 (names_broadcast): Ditto.
458 (x86_64_table): Add escape to evex-table.
459 (reg_table): Include reg_table evex-entries from
460 i386-dis-evex.h. Fix prefetchwt1 instruction.
461 (prefix_table): Add entries for new instructions.
463 (vex_len_table): Ditto.
464 (vex_w_table): Ditto.
466 (get_valid_dis386): Properly handle new instructions.
467 (print_insn): Handle zmm and mask registers, print mask operand.
468 (intel_operand_size): Support EVEX, new modes and sizes.
469 (OP_E_register): Handle new modes.
470 (OP_E_memory): Ditto.
475 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
476 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
477 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
478 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
479 CpuAVX512PF and CpuVREX.
480 (operand_type_init): Add OPERAND_TYPE_REGZMM,
481 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
482 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
483 StaticRounding, SAE, Disp8MemShift, NoDefMask.
484 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
485 * i386-init.h: Regenerate.
486 * i386-opc.h (CpuAVX512F): New.
491 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
492 cpuavx512pf and cpuvrex fields.
493 (VecSIB): Add VecSIB512.
498 (StaticRounding): New.
500 (Disp8MemShift): New.
502 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
503 staticrounding, sae, disp8memshift and nodefmask.
507 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
510 * i386-opc.tbl: Add AVX512 instructions.
511 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
512 registers, mask registers.
513 * i386-tbl.h: Regenerate.
515 2013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
518 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
519 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
521 2013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
523 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
524 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
526 (prefix_table): Updated.
527 (three_byte_table): Likewise.
528 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
529 (cpu_flags): Add CpuSHA.
530 (i386_cpu_flags): Add cpusha.
531 * i386-init.h: Regenerate.
532 * i386-opc.h (CpuSHA): New.
533 (CpuUnused): Restored.
534 (i386_cpu_flags): Add cpusha.
535 * i386-opc.tbl: Add SHA instructions.
536 * i386-tbl.h: Regenerate.
538 2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
539 Kirill Yukhin <kirill.yukhin@intel.com>
540 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
542 * i386-dis.c (BND_Fixup): New.
549 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
551 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
552 (dis tables): Replace XX with BND for near branch and call
554 (prefix_table): Add new entries.
555 (mod_table): Likewise.
557 (intel_names_bnd): New.
558 (att_names_bnd): New.
560 (prefix_name): Handle BND_PREFIX.
561 (print_insn): Initialize names_bnd.
562 (intel_operand_size): Handle new modes.
563 (OP_E_register): Likewise.
564 (OP_E_memory): Likewise.
566 * i386-gen.c (cpu_flag_init): Add CpuMPX.
567 (cpu_flags): Add CpuMPX.
568 (operand_type_init): Add RegBND.
569 (opcode_modifiers): Add BNDPrefixOk.
570 (operand_types): Add RegBND.
571 * i386-init.h: Regenerate.
572 * i386-opc.h (CpuMPX): New.
573 (CpuUnused): Comment out.
574 (i386_cpu_flags): Add cpumpx.
576 (i386_opcode_modifier): Add bndprefixok.
578 (i386_operand_type): Add regbnd.
579 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
580 Add MPX instructions and bnd prefix.
581 * i386-reg.tbl: Add bnd0-bnd3 registers.
582 * i386-tbl.h: Regenerate.
584 2013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
586 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
589 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
591 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
593 * Makefile.in: Regenerate.
594 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
595 all fields. Reformat.
597 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
599 * mips16-opc.c: Include mips-formats.h.
600 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
602 (decode_mips16_operand): New function.
603 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
604 (print_insn_arg): Handle OP_ENTRY_EXIT list.
605 Abort for OP_SAVE_RESTORE_LIST.
606 (print_mips16_insn_arg): Change interface. Use mips_operand
607 structures. Delete GET_OP_S. Move GET_OP definition to...
608 (print_insn_mips16): ...here. Call init_print_arg_state.
609 Update the call to print_mips16_insn_arg.
611 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
613 * mips-formats.h: New file.
614 * mips-opc.c: Include mips-formats.h.
615 (reg_0_map): New static array.
616 (decode_mips_operand): New function.
617 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
618 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
619 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
620 (int_c_map): New static arrays.
621 (decode_micromips_operand): New function.
622 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
623 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
624 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
625 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
626 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
627 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
628 (micromips_imm_b_map, micromips_imm_c_map): Delete.
629 (print_reg): New function.
630 (mips_print_arg_state): New structure.
631 (init_print_arg_state, print_insn_arg): New functions.
632 (print_insn_args): Change interface and use mips_operand structures.
633 Delete GET_OP_S. Move GET_OP definition to...
634 (print_insn_mips): ...here. Update the call to print_insn_args.
635 (print_insn_micromips): Use print_insn_args.
637 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
639 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
642 2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
644 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
645 ADDA.S, MULA.S and SUBA.S.
647 2013-07-08 H.J. Lu <hongjiu.lu@intel.com>
650 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
651 * i386-tbl.h: Regenerated.
653 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
655 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
656 and SD A(B) macros up.
657 * micromips-opc.c (micromips_opcodes): Likewise.
659 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
661 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
664 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
666 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
667 MDMX-like instructions.
668 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
669 printing "Q" operands for INSN_5400 instructions.
671 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
673 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
675 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
678 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
680 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
682 * mips16-opc.c (mips16_opcodes): Likewise.
683 * micromips-opc.c (micromips_opcodes): Likewise.
684 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
685 (print_insn_mips16): Handle "+i".
686 (print_insn_micromips): Likewise. Conditionally preserve the
687 ISA bit for "a" but not for "+i".
689 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
691 * micromips-opc.c (WR_mhi): Rename to..
693 (micromips_opcodes): Update "movep" entry accordingly. Replace
695 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
696 (micromips_to_32_reg_h_map1): ...this.
697 (micromips_to_32_reg_i_map): Rename to...
698 (micromips_to_32_reg_h_map2): ...this.
699 (print_micromips_insn): Remove "mi" case. Print both registers
700 in the pair for "mh".
702 2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
704 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
705 * micromips-opc.c (micromips_opcodes): Likewise.
706 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
707 and "+T" handling. Check for a "0" suffix when deciding whether to
708 use coprocessor 0 names. In that case, also check for ",H" selectors.
710 2013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
712 * s390-opc.c (J12_12, J24_24): New macros.
713 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
714 (MASK_MII_UPI): Rename to MASK_MII_UPP.
715 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
717 2013-07-04 Alan Modra <amodra@gmail.com>
719 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
721 2013-06-26 Nick Clifton <nickc@redhat.com>
723 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
724 field when checking for type 2 nop.
725 * rx-decode.c: Regenerate.
727 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
729 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
732 2013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
734 * mips-dis.c (is_mips16_plt_tail): New function.
735 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
737 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
739 2013-06-21 DJ Delorie <dj@redhat.com>
741 * msp430-decode.opc: New.
742 * msp430-decode.c: New/generated.
743 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
744 (MAINTAINER_CLEANFILES): Likewise.
745 Add rule to build msp430-decode.c frommsp430decode.opc
746 using the opc2c program.
747 * Makefile.in: Regenerate.
748 * configure.in: Add msp430-decode.lo to msp430 architecture files.
749 * configure: Regenerate.
751 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
753 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
754 (SYMTAB_AVAILABLE): Removed.
755 (#include "elf/aarch64.h): Ditto.
757 2013-06-17 Catherine Moore <clm@codesourcery.com>
758 Maciej W. Rozycki <macro@codesourcery.com>
759 Chao-Ying Fu <fu@mips.com>
761 * micromips-opc.c (EVA): Define.
763 (micromips_opcodes): Add EVA opcodes.
764 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
765 (print_insn_args): Handle EVA offsets.
766 (print_insn_micromips): Likewise.
767 * mips-opc.c (EVA): Define.
769 (mips_builtin_opcodes): Add EVA opcodes.
771 2013-06-17 Alan Modra <amodra@gmail.com>
773 * Makefile.am (mips-opc.lo): Add rules to create automatic
774 dependency files. Pass archdefs.
775 (micromips-opc.lo, mips16-opc.lo): Likewise.
776 * Makefile.in: Regenerate.
778 2013-06-14 DJ Delorie <dj@redhat.com>
780 * rx-decode.opc (rx_decode_opcode): Bit operations on
781 registers are 32-bit operations, not 8-bit operations.
782 * rx-decode.c: Regenerate.
784 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
786 * micromips-opc.c (IVIRT): New define.
787 (IVIRT64): New define.
788 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
789 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
791 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
792 dmtgc0 to print cp0 names.
794 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
796 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
799 2013-06-08 Catherine Moore <clm@codesourcery.com>
800 Richard Sandiford <rdsandiford@googlemail.com>
802 * micromips-opc.c (D32, D33, MC): Update definitions.
803 (micromips_opcodes): Initialize ase field.
804 * mips-dis.c (mips_arch_choice): Add ase field.
805 (mips_arch_choices): Initialize ase field.
806 (set_default_mips_dis_options): Declare and setup mips_ase.
807 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
808 MT32, MC): Update definitions.
809 (mips_builtin_opcodes): Initialize ase field.
811 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
813 * s390-opc.txt (flogr): Require a register pair destination.
815 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
817 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
820 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
822 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
824 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
826 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
827 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
828 XLS_MASK, PPCVSX2): New defines.
829 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
830 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
831 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
832 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
833 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
834 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
835 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
836 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
837 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
838 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
839 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
840 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
841 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
842 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
843 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
844 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
845 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
846 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
847 <lxvx, stxvx>: New extended mnemonics.
849 2013-05-17 Alan Modra <amodra@gmail.com>
851 * ia64-raw.tbl: Replace non-ASCII char.
852 * ia64-waw.tbl: Likewise.
853 * ia64-asmtab.c: Regenerate.
855 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
857 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
858 * i386-init.h: Regenerated.
860 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
862 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
863 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
864 check from [0, 255] to [-128, 255].
866 2013-05-09 Andrew Pinski <apinski@cavium.com>
868 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
869 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
870 (parse_mips_dis_option): Handle the virt option.
871 (print_insn_args): Handle "+J".
872 (print_mips_disassembler_options): Print out message about virt64.
873 * mips-opc.c (IVIRT): New define.
874 (IVIRT64): New define.
875 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
876 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
877 Move rfe to the bottom as it conflicts with tlbgp.
879 2013-05-09 Alan Modra <amodra@gmail.com>
881 * ppc-opc.c (extract_vlesi): Properly sign extend.
882 (extract_vlensi): Likewise. Comment reason for setting invalid.
884 2013-05-02 Nick Clifton <nickc@redhat.com>
886 * msp430-dis.c: Add support for MSP430X instructions.
888 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
890 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
893 2013-04-17 Wei-chen Wang <cole945@gmail.com>
896 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
898 (hash_insns_list): Likewise.
900 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
902 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
905 2013-04-08 Jan Beulich <jbeulich@suse.com>
907 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
908 * i386-tbl.h: Re-generate.
910 2013-04-06 David S. Miller <davem@davemloft.net>
912 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
913 of an opcode, prefer the one with F_PREFERRED set.
914 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
915 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
916 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
917 mark existing mnenomics as aliases. Add "cc" suffix to edge
918 instructions generating condition codes, mark existing mnenomics
919 as aliases. Add "fp" prefix to VIS compare instructions, mark
920 existing mnenomics as aliases.
922 2013-04-03 Nick Clifton <nickc@redhat.com>
924 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
925 destination address by subtracting the operand from the current
927 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
928 a positive value in the insn.
929 (extract_u16_loop): Do not negate the returned value.
930 (D16_LOOP): Add V850_INVERSE_PCREL flag.
932 (ceilf.sw): Remove duplicate entry.
933 (cvtf.hs): New entry.
939 (maddf.s): Restrict to E3V5 architectures.
941 (nmaddf.s): Likewise.
942 (nmsubf.s): Likewise.
944 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
946 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
948 (print_insn): Pass sizeflag to get_sib.
950 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
953 * tic6x-dis.c: Add support for displaying 16-bit insns.
955 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
958 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
959 individual msb and lsb halves in src1 & src2 fields. Discard the
960 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
961 follow what Ti SDK does in that case as any value in the src1
962 field yields the same output with SDK disassembler.
964 2013-03-12 Michael Eager <eager@eagercon.com>
966 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
968 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
970 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
972 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
974 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
976 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
978 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
980 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
982 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
983 (thumb32_opcodes): Likewise.
984 (print_insn_thumb32): Handle 'S' control char.
986 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
988 * lm32-desc.c: Regenerate.
990 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
992 * i386-reg.tbl (riz): Add RegRex64.
993 * i386-tbl.h: Regenerated.
995 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
997 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
998 (aarch64_feature_crc): New static.
1000 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1001 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1002 * aarch64-asm-2.c: Re-generate.
1003 * aarch64-dis-2.c: Ditto.
1004 * aarch64-opc-2.c: Ditto.
1006 2013-02-27 Alan Modra <amodra@gmail.com>
1008 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1009 * rl78-decode.c: Regenerate.
1011 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1013 * rl78-decode.opc: Fix encoding of DIVWU insn.
1014 * rl78-decode.c: Regenerate.
1016 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1019 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1021 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1022 (cpu_flags): Add CpuSMAP.
1024 * i386-opc.h (CpuSMAP): New.
1025 (i386_cpu_flags): Add cpusmap.
1027 * i386-opc.tbl: Add clac and stac.
1029 * i386-init.h: Regenerated.
1030 * i386-tbl.h: Likewise.
1032 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1034 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1035 which also makes the disassembler output be in little
1036 endian like it should be.
1038 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1040 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1042 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1044 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
1046 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1047 section disassembled.
1049 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1051 * arm-dis.c: Update strht pattern.
1053 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1055 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1056 single-float. Disable ll, lld, sc and scd for EE. Disable the
1057 trunc.w.s macro for EE.
1059 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1060 Andrew Jenner <andrew@codesourcery.com>
1062 Based on patches from Altera Corporation.
1064 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1066 * Makefile.in: Regenerated.
1067 * configure.in: Add case for bfd_nios2_arch.
1068 * configure: Regenerated.
1069 * disassemble.c (ARCH_nios2): Define.
1070 (disassembler): Add case for bfd_arch_nios2.
1071 * nios2-dis.c: New file.
1072 * nios2-opc.c: New file.
1074 2013-02-04 Alan Modra <amodra@gmail.com>
1076 * po/POTFILES.in: Regenerate.
1077 * rl78-decode.c: Regenerate.
1078 * rx-decode.c: Regenerate.
1080 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1082 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1083 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1084 * aarch64-asm.c (convert_xtl_to_shll): New function.
1085 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1086 calling convert_xtl_to_shll.
1087 * aarch64-dis.c (convert_shll_to_xtl): New function.
1088 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1089 calling convert_shll_to_xtl.
1090 * aarch64-gen.c: Update copyright year.
1091 * aarch64-asm-2.c: Re-generate.
1092 * aarch64-dis-2.c: Re-generate.
1093 * aarch64-opc-2.c: Re-generate.
1095 2013-01-24 Nick Clifton <nickc@redhat.com>
1097 * v850-dis.c: Add support for e3v5 architecture.
1098 * v850-opc.c: Likewise.
1100 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1102 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1103 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1104 * aarch64-opc.c (operand_general_constraint_met_p): For
1105 AARCH64_MOD_LSL, move the range check on the shift amount before the
1106 alignment check; change to call set_sft_amount_out_of_range_error
1107 instead of set_imm_out_of_range_error.
1108 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1109 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1110 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1113 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1117 * i386-init.h: Regenerated.
1118 * i386-tbl.h: Likewise.
1120 2013-01-15 Nick Clifton <nickc@redhat.com>
1122 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1124 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1126 2013-01-14 Will Newton <will.newton@imgtec.com>
1128 * metag-dis.c (REG_WIDTH): Increase to 64.
1130 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1132 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1133 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1134 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1136 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1137 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1138 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1139 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1141 2013-01-10 Will Newton <will.newton@imgtec.com>
1143 * Makefile.am: Add Meta.
1144 * configure.in: Add Meta.
1145 * disassemble.c: Add Meta support.
1146 * metag-dis.c: New file.
1147 * Makefile.in: Regenerate.
1148 * configure: Regenerate.
1150 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1152 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1153 (match_opcode): Rename to cr16_match_opcode.
1155 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1157 * mips-dis.c: Add names for CP0 registers of r5900.
1158 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1159 instructions sq and lq.
1160 Add support for MIPS r5900 CPU.
1161 Add support for 128 bit MMI (Multimedia Instructions).
1162 Add support for EE instructions (Emotion Engine).
1163 Disable unsupported floating point instructions (64 bit and
1164 undefined compare operations).
1165 Enable instructions of MIPS ISA IV which are supported by r5900.
1166 Disable 64 bit co processor instructions.
1167 Disable 64 bit multiplication and division instructions.
1168 Disable instructions for co-processor 2 and 3, because these are
1169 not supported (preparation for later VU0 support (Vector Unit)).
1170 Disable cvt.w.s because this behaves like trunc.w.s and the
1171 correct execution can't be ensured on r5900.
1172 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1173 will confuse less developers and compilers.
1175 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1177 * aarch64-opc.c (aarch64_print_operand): Change to print
1178 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1180 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1181 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1184 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1186 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1187 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
1189 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1191 * i386-gen.c (process_copyright): Update copyright year to 2013.
1193 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1195 * cr16-dis.c (match_opcode,make_instruction): Remove static
1197 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1198 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
1200 For older changes see ChangeLog-2012
1202 Copyright (C) 2013 Free Software Foundation, Inc.
1204 Copying and distribution of this file, with or without modification,
1205 are permitted in any medium without royalty provided the copyright
1206 notice and this notice are preserved.
1212 version-control: never