1 2017-09-27 Nick Clifton <nickc@redhat.com>
4 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
5 names for the fmv.x.s and fmv.s.x instructions respectively.
7 2017-09-26 do <do@nerilex.org>
10 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
11 be used on CPUs that have emacs support.
13 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
15 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
17 2017-09-09 Kamil Rytarowski <n54@gmx.com>
19 * nds32-asm.c: Rename __BIT() to N32_BIT().
20 * nds32-asm.h: Likewise.
21 * nds32-dis.c: Likewise.
23 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
25 * i386-dis.c (last_active_prefix): Removed.
26 (ckprefix): Don't set last_active_prefix.
27 (NOTRACK_Fixup): Don't check last_active_prefix.
29 2017-08-31 Nick Clifton <nickc@redhat.com>
31 * po/fr.po: Updated French translation.
33 2017-08-31 James Bowman <james.bowman@ftdichip.com>
35 * ft32-dis.c (print_insn_ft32): Correct display of non-address
38 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
39 Edmar Wienskoski <edmar.wienskoski@nxp.com>
41 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
42 PPC_OPCODE_EFS2 flag to "e200z4" entry.
43 New entries efs2 and spe2.
44 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
45 (SPE2_OPCD_SEGS): New macro.
46 (spe2_opcd_indices): New.
47 (disassemble_init_powerpc): Handle SPE2 opcodes.
48 (lookup_spe2): New function.
49 (print_insn_powerpc): call lookup_spe2.
50 * ppc-opc.c (insert_evuimm1_ex0): New function.
51 (extract_evuimm1_ex0): Likewise.
52 (insert_evuimm_lt8): Likewise.
53 (extract_evuimm_lt8): Likewise.
54 (insert_off_spe2): Likewise.
55 (extract_off_spe2): Likewise.
56 (insert_Ddd): Likewise.
57 (extract_Ddd): Likewise.
59 (EVUIMM_LT8): Likewise.
60 (EVUIMM_LT16): Adjust.
63 (EVUIMM_1_EX0): Likewise.
66 (VX_OFF_SPE2): Likewise.
69 (VX_MASK_DDD): New mask.
71 (VX_RA_CONST): New macro.
72 (VX_RA_CONST_MASK): Likewise.
73 (VX_RB_CONST): Likewise.
74 (VX_RB_CONST_MASK): Likewise.
75 (VX_OFF_SPE2_MASK): Likewise.
76 (VX_SPE_CRFD): Likewise.
77 (VX_SPE_CRFD_MASK VX): Likewise.
78 (VX_SPE2_CLR): Likewise.
79 (VX_SPE2_CLR_MASK): Likewise.
80 (VX_SPE2_SPLATB): Likewise.
81 (VX_SPE2_SPLATB_MASK): Likewise.
82 (VX_SPE2_OCTET): Likewise.
83 (VX_SPE2_OCTET_MASK): Likewise.
84 (VX_SPE2_DDHH): Likewise.
85 (VX_SPE2_DDHH_MASK): Likewise.
86 (VX_SPE2_HH): Likewise.
87 (VX_SPE2_HH_MASK): Likewise.
88 (VX_SPE2_EVMAR): Likewise.
89 (VX_SPE2_EVMAR_MASK): Likewise.
92 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
93 (powerpc_macros): Map old SPE instructions have new names
94 with the same opcodes. Add SPE2 instructions which just are
96 (spe2_opcodes): Add SPE2 opcodes.
98 2017-08-23 Alan Modra <amodra@gmail.com>
100 * ppc-opc.c: Formatting and comment fixes. Move insert and
101 extract functions earlier, deleting forward declarations.
102 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
105 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
107 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
109 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
110 Edmar Wienskoski <edmar.wienskoski@nxp.com>
112 * ppc-opc.c (insert_evuimm2_ex0): New function.
113 (extract_evuimm2_ex0): Likewise.
114 (insert_evuimm4_ex0): Likewise.
115 (extract_evuimm4_ex0): Likewise.
116 (insert_evuimm8_ex0): Likewise.
117 (extract_evuimm8_ex0): Likewise.
118 (insert_evuimm_lt16): Likewise.
119 (extract_evuimm_lt16): Likewise.
120 (insert_rD_rS_even): Likewise.
121 (extract_rD_rS_even): Likewise.
122 (insert_off_lsp): Likewise.
123 (extract_off_lsp): Likewise.
124 (RD_EVEN): New operand.
127 (EVUIMM_LT16): New operand.
129 (EVUIMM_2_EX0): New operand.
131 (EVUIMM_4_EX0): New operand.
133 (EVUIMM_8_EX0): New operand.
135 (VX_OFF): New operand.
137 (VX_LSP_MASK): Likewise.
138 (VX_LSP_OFF_MASK): Likewise.
139 (PPC_OPCODE_LSP): Likewise.
140 (vle_opcodes): Add LSP opcodes.
141 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
143 2017-08-09 Jiong Wang <jiong.wang@arm.com>
145 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
146 register operands in CRC instructions.
147 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
150 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
152 * disassemble.c (disassembler): Mark big and mach with
155 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
157 * disassemble.c (disassembler): Remove arch/mach/endian
160 2017-07-25 Nick Clifton <nickc@redhat.com>
163 * arc-opc.c (insert_rhv2): Use lower case first letter in error
165 (insert_r0): Likewise.
166 (insert_r1): Likewise.
167 (insert_r2): Likewise.
168 (insert_r3): Likewise.
169 (insert_sp): Likewise.
170 (insert_gp): Likewise.
171 (insert_pcl): Likewise.
172 (insert_blink): Likewise.
173 (insert_ilink1): Likewise.
174 (insert_ilink2): Likewise.
175 (insert_ras): Likewise.
176 (insert_rbs): Likewise.
177 (insert_rcs): Likewise.
178 (insert_simm3s): Likewise.
179 (insert_rrange): Likewise.
180 (insert_r13el): Likewise.
181 (insert_fpel): Likewise.
182 (insert_blinkel): Likewise.
183 (insert_pclel): Likewise.
184 (insert_nps_bitop_size_2b): Likewise.
185 (insert_nps_imm_offset): Likewise.
186 (insert_nps_imm_entry): Likewise.
187 (insert_nps_size_16bit): Likewise.
188 (insert_nps_##NAME##_pos): Likewise.
189 (insert_nps_##NAME): Likewise.
190 (insert_nps_bitop_ins_ext): Likewise.
191 (insert_nps_##NAME): Likewise.
192 (insert_nps_min_hofs): Likewise.
193 (insert_nps_##NAME): Likewise.
194 (insert_nps_rbdouble_64): Likewise.
195 (insert_nps_misc_imm_offset): Likewise.
196 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
199 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
200 Jiong Wang <jiong.wang@arm.com>
202 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
204 * aarch64-dis-2.c: Regenerated.
206 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
208 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
211 2017-07-20 Nick Clifton <nickc@redhat.com>
213 * po/de.po: Updated German translation.
215 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
217 * arc-regs.h (sec_stat): New aux register.
218 (aux_kernel_sp): Likewise.
219 (aux_sec_u_sp): Likewise.
220 (aux_sec_k_sp): Likewise.
221 (sec_vecbase_build): Likewise.
222 (nsc_table_top): Likewise.
223 (nsc_table_base): Likewise.
224 (ersec_stat): Likewise.
225 (aux_sec_except): Likewise.
227 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
229 * arc-opc.c (extract_uimm12_20): New function.
230 (UIMM12_20): New operand.
232 * arc-tbl.h (sjli): Add new instruction.
234 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
235 John Eric Martin <John.Martin@emmicro-us.com>
237 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
238 (UIMM3_23): Adjust accordingly.
239 * arc-regs.h: Add/correct jli_base register.
240 * arc-tbl.h (jli_s): Likewise.
242 2017-07-18 Nick Clifton <nickc@redhat.com>
245 * aarch64-opc.c: Fix spelling typos.
246 * i386-dis.c: Likewise.
248 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
250 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
251 max_addr_offset and octets variables to size_t.
253 2017-07-12 Alan Modra <amodra@gmail.com>
255 * po/da.po: Update from translationproject.org/latest/opcodes/.
256 * po/de.po: Likewise.
257 * po/es.po: Likewise.
258 * po/fi.po: Likewise.
259 * po/fr.po: Likewise.
260 * po/id.po: Likewise.
261 * po/it.po: Likewise.
262 * po/nl.po: Likewise.
263 * po/pt_BR.po: Likewise.
264 * po/ro.po: Likewise.
265 * po/sv.po: Likewise.
266 * po/tr.po: Likewise.
267 * po/uk.po: Likewise.
268 * po/vi.po: Likewise.
269 * po/zh_CN.po: Likewise.
271 2017-07-11 Yao Qi <yao.qi@linaro.org>
272 Alan Modra <amodra@gmail.com>
274 * cgen.sh: Mark generated files read-only.
275 * epiphany-asm.c: Regenerate.
276 * epiphany-desc.c: Regenerate.
277 * epiphany-desc.h: Regenerate.
278 * epiphany-dis.c: Regenerate.
279 * epiphany-ibld.c: Regenerate.
280 * epiphany-opc.c: Regenerate.
281 * epiphany-opc.h: Regenerate.
282 * fr30-asm.c: Regenerate.
283 * fr30-desc.c: Regenerate.
284 * fr30-desc.h: Regenerate.
285 * fr30-dis.c: Regenerate.
286 * fr30-ibld.c: Regenerate.
287 * fr30-opc.c: Regenerate.
288 * fr30-opc.h: Regenerate.
289 * frv-asm.c: Regenerate.
290 * frv-desc.c: Regenerate.
291 * frv-desc.h: Regenerate.
292 * frv-dis.c: Regenerate.
293 * frv-ibld.c: Regenerate.
294 * frv-opc.c: Regenerate.
295 * frv-opc.h: Regenerate.
296 * ip2k-asm.c: Regenerate.
297 * ip2k-desc.c: Regenerate.
298 * ip2k-desc.h: Regenerate.
299 * ip2k-dis.c: Regenerate.
300 * ip2k-ibld.c: Regenerate.
301 * ip2k-opc.c: Regenerate.
302 * ip2k-opc.h: Regenerate.
303 * iq2000-asm.c: Regenerate.
304 * iq2000-desc.c: Regenerate.
305 * iq2000-desc.h: Regenerate.
306 * iq2000-dis.c: Regenerate.
307 * iq2000-ibld.c: Regenerate.
308 * iq2000-opc.c: Regenerate.
309 * iq2000-opc.h: Regenerate.
310 * lm32-asm.c: Regenerate.
311 * lm32-desc.c: Regenerate.
312 * lm32-desc.h: Regenerate.
313 * lm32-dis.c: Regenerate.
314 * lm32-ibld.c: Regenerate.
315 * lm32-opc.c: Regenerate.
316 * lm32-opc.h: Regenerate.
317 * lm32-opinst.c: Regenerate.
318 * m32c-asm.c: Regenerate.
319 * m32c-desc.c: Regenerate.
320 * m32c-desc.h: Regenerate.
321 * m32c-dis.c: Regenerate.
322 * m32c-ibld.c: Regenerate.
323 * m32c-opc.c: Regenerate.
324 * m32c-opc.h: Regenerate.
325 * m32r-asm.c: Regenerate.
326 * m32r-desc.c: Regenerate.
327 * m32r-desc.h: Regenerate.
328 * m32r-dis.c: Regenerate.
329 * m32r-ibld.c: Regenerate.
330 * m32r-opc.c: Regenerate.
331 * m32r-opc.h: Regenerate.
332 * m32r-opinst.c: Regenerate.
333 * mep-asm.c: Regenerate.
334 * mep-desc.c: Regenerate.
335 * mep-desc.h: Regenerate.
336 * mep-dis.c: Regenerate.
337 * mep-ibld.c: Regenerate.
338 * mep-opc.c: Regenerate.
339 * mep-opc.h: Regenerate.
340 * mt-asm.c: Regenerate.
341 * mt-desc.c: Regenerate.
342 * mt-desc.h: Regenerate.
343 * mt-dis.c: Regenerate.
344 * mt-ibld.c: Regenerate.
345 * mt-opc.c: Regenerate.
346 * mt-opc.h: Regenerate.
347 * or1k-asm.c: Regenerate.
348 * or1k-desc.c: Regenerate.
349 * or1k-desc.h: Regenerate.
350 * or1k-dis.c: Regenerate.
351 * or1k-ibld.c: Regenerate.
352 * or1k-opc.c: Regenerate.
353 * or1k-opc.h: Regenerate.
354 * or1k-opinst.c: Regenerate.
355 * xc16x-asm.c: Regenerate.
356 * xc16x-desc.c: Regenerate.
357 * xc16x-desc.h: Regenerate.
358 * xc16x-dis.c: Regenerate.
359 * xc16x-ibld.c: Regenerate.
360 * xc16x-opc.c: Regenerate.
361 * xc16x-opc.h: Regenerate.
362 * xstormy16-asm.c: Regenerate.
363 * xstormy16-desc.c: Regenerate.
364 * xstormy16-desc.h: Regenerate.
365 * xstormy16-dis.c: Regenerate.
366 * xstormy16-ibld.c: Regenerate.
367 * xstormy16-opc.c: Regenerate.
368 * xstormy16-opc.h: Regenerate.
370 2017-07-07 Alan Modra <amodra@gmail.com>
372 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
373 * m32c-dis.c: Regenerate.
374 * mep-dis.c: Regenerate.
376 2017-07-05 Borislav Petkov <bp@suse.de>
378 * i386-dis.c: Enable ModRM.reg /6 aliases.
380 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
382 * opcodes/arm-dis.c: Support MVFR2 in disassembly
385 2017-07-04 Tristan Gingold <gingold@adacore.com>
387 * configure: Regenerate.
389 2017-07-03 Tristan Gingold <gingold@adacore.com>
391 * po/opcodes.pot: Regenerate.
393 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
395 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
396 entries to the MSA ASE instruction block.
398 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
399 Maciej W. Rozycki <macro@imgtec.com>
401 * micromips-opc.c (XPA, XPAVZ): New macros.
402 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
405 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
406 Maciej W. Rozycki <macro@imgtec.com>
408 * micromips-opc.c (I36): New macro.
409 (micromips_opcodes): Add "eretnc".
411 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
412 Andrew Bennett <andrew.bennett@imgtec.com>
414 * mips-dis.c (mips_calculate_combination_ases): Handle the
416 (parse_mips_ase_option): New function.
417 (parse_mips_dis_option): Factor out ASE option handling to the
418 new function. Call `mips_calculate_combination_ases'.
419 * mips-opc.c (XPAVZ): New macro.
420 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
421 "mfhgc0", "mthc0" and "mthgc0".
423 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
425 * mips-dis.c (mips_calculate_combination_ases): New function.
426 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
427 calculation to the new function.
428 (set_default_mips_dis_options): Call the new function.
430 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
432 * arc-dis.c (parse_disassembler_options): Use
433 FOR_EACH_DISASSEMBLER_OPTION.
435 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
437 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
438 disassembler option strings.
439 (parse_cpu_option): Likewise.
441 2017-06-28 Tamar Christina <tamar.christina@arm.com>
443 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
444 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
445 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
446 (aarch64_feature_dotprod, DOT_INSN): New.
448 * aarch64-dis-2.c: Regenerated.
450 2017-06-28 Jiong Wang <jiong.wang@arm.com>
452 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
454 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
455 Matthew Fortune <matthew.fortune@imgtec.com>
456 Andrew Bennett <andrew.bennett@imgtec.com>
458 * mips-formats.h (INT_BIAS): New macro.
459 (INT_ADJ): Redefine in INT_BIAS terms.
460 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
461 (mips_print_save_restore): New function.
462 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
463 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
465 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
466 (print_mips16_insn_arg): Call `mips_print_save_restore' for
467 OP_SAVE_RESTORE_LIST handling, factored out from here.
468 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
469 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
470 (mips_builtin_opcodes): Add "restore" and "save" entries.
471 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
473 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
475 2017-06-23 Andrew Waterman <andrew@sifive.com>
477 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
478 alias; do not mark SLTI instruction as an alias.
480 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
482 * i386-dis.c (RM_0FAE_REG_5): Removed.
483 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
484 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
485 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
486 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
487 PREFIX_MOD_3_0F01_REG_5_RM_0.
488 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
489 PREFIX_MOD_3_0FAE_REG_5.
490 (mod_table): Update MOD_0FAE_REG_5.
491 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
492 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
493 * i386-tbl.h: Regenerated.
495 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
497 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
498 * i386-opc.tbl: Likewise.
499 * i386-tbl.h: Regenerated.
501 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
503 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
505 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
508 2017-06-19 Nick Clifton <nickc@redhat.com>
511 * score-dis.c (score_opcodes): Add sentinel.
513 2017-06-16 Alan Modra <amodra@gmail.com>
515 * rx-decode.c: Regenerate.
517 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-dis.c (OP_E_register): Check valid bnd register.
523 2017-06-15 Nick Clifton <nickc@redhat.com>
526 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
529 2017-06-15 Nick Clifton <nickc@redhat.com>
532 * rl78-decode.opc (OP_BUF_LEN): Define.
533 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
534 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
536 * rl78-decode.c: Regenerate.
538 2017-06-15 Nick Clifton <nickc@redhat.com>
541 * bfin-dis.c (gregs): Clip index to prevent overflow.
546 2017-06-14 Nick Clifton <nickc@redhat.com>
549 * score7-dis.c (score_opcodes): Add sentinel.
551 2017-06-14 Yao Qi <yao.qi@linaro.org>
553 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
554 * arm-dis.c: Likewise.
555 * ia64-dis.c: Likewise.
556 * mips-dis.c: Likewise.
557 * spu-dis.c: Likewise.
558 * disassemble.h (print_insn_aarch64): New declaration, moved from
560 (print_insn_big_arm, print_insn_big_mips): Likewise.
561 (print_insn_i386, print_insn_ia64): Likewise.
562 (print_insn_little_arm, print_insn_little_mips): Likewise.
564 2017-06-14 Nick Clifton <nickc@redhat.com>
567 * rx-decode.opc: Include libiberty.h
568 (GET_SCALE): New macro - validates access to SCALE array.
569 (GET_PSCALE): New macro - validates access to PSCALE array.
570 (DIs, SIs, S2Is, rx_disp): Use new macros.
571 * rx-decode.c: Regenerate.
573 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
575 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
577 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
579 * arc-dis.c (enforced_isa_mask): Declare.
580 (cpu_types): Likewise.
581 (parse_cpu_option): New function.
582 (parse_disassembler_options): Use it.
583 (print_insn_arc): Use enforced_isa_mask.
584 (print_arc_disassembler_options): Document new options.
586 2017-05-24 Yao Qi <yao.qi@linaro.org>
588 * alpha-dis.c: Include disassemble.h, don't include
590 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
591 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
592 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
593 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
594 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
595 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
596 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
597 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
598 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
599 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
600 * moxie-dis.c, msp430-dis.c, mt-dis.c:
601 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
602 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
603 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
604 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
605 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
606 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
607 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
608 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
609 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
610 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
611 * z80-dis.c, z8k-dis.c: Likewise.
612 * disassemble.h: New file.
614 2017-05-24 Yao Qi <yao.qi@linaro.org>
616 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
617 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
619 2017-05-24 Yao Qi <yao.qi@linaro.org>
621 * disassemble.c (disassembler): Add arguments a, big and mach.
624 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
626 * i386-dis.c (NOTRACK_Fixup): New.
628 (NOTRACK_PREFIX): Likewise.
629 (last_active_prefix): Likewise.
630 (reg_table): Use NOTRACK on indirect call and jmp.
631 (ckprefix): Set last_active_prefix.
632 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
633 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
634 * i386-opc.h (NoTrackPrefixOk): New.
635 (i386_opcode_modifier): Add notrackprefixok.
636 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
638 * i386-tbl.h: Regenerated.
640 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
642 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
644 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
646 (print_insn_sparc): Handle new operand types.
647 * sparc-opc.c (MASK_M8): Define.
649 (v6notlet): Likewise.
660 (v9andleon): Likewise.
663 (HWS2_VM8): Likewise.
664 (sparc_opcode_archs): Add entry for "m8".
665 (sparc_opcodes): Add OSA2017 and M8 instructions
666 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
668 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
669 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
670 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
671 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
672 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
673 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
674 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
675 ASI_CORE_SELECT_COMMIT_NHT.
677 2017-05-18 Alan Modra <amodra@gmail.com>
679 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
680 * aarch64-dis.c: Likewise.
681 * aarch64-gen.c: Likewise.
682 * aarch64-opc.c: Likewise.
684 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
685 Matthew Fortune <matthew.fortune@imgtec.com>
687 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
688 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
689 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
690 (print_insn_arg) <OP_REG28>: Add handler.
691 (validate_insn_args) <OP_REG28>: Handle.
692 (print_mips16_insn_arg): Handle MIPS16 instructions that require
693 32-bit encoding and 9-bit immediates.
694 (print_insn_mips16): Handle MIPS16 instructions that require
695 32-bit encoding and MFC0/MTC0 operand decoding.
696 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
697 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
698 (RD_C0, WR_C0, E2, E2MT): New macros.
699 (mips16_opcodes): Add entries for MIPS16e2 instructions:
700 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
701 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
702 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
703 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
704 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
705 instructions, "swl", "swr", "sync" and its "sync_acquire",
706 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
707 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
708 regular/extended entries for original MIPS16 ISA revision
709 instructions whose extended forms are subdecoded in the MIPS16e2
710 ISA revision: "li", "sll" and "srl".
712 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
714 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
715 reference in CP0 move operand decoding.
717 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
719 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
721 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
723 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
725 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
726 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
727 "sync_rmb" and "sync_wmb" as aliases.
728 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
729 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
731 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
733 * arc-dis.c (parse_option): Update quarkse_em option..
734 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
736 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
738 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
740 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
742 2017-05-01 Michael Clark <michaeljclark@mac.com>
744 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
747 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
749 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
750 and branches and not synthetic data instructions.
752 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
754 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
756 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
758 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
759 * arc-opc.c (insert_r13el): New function.
761 * arc-tbl.h: Add new enter/leave variants.
763 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
765 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
767 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
769 * mips-dis.c (print_mips_disassembler_options): Add
772 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
774 * mips16-opc.c (AL): New macro.
775 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
776 of "ld" and "lw" as aliases.
778 2017-04-24 Tamar Christina <tamar.christina@arm.com>
780 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
783 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
784 Alan Modra <amodra@gmail.com>
786 * ppc-opc.c (ELEV): Define.
787 (vle_opcodes): Add se_rfgi and e_sc.
788 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
791 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
793 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
795 2017-04-21 Nick Clifton <nickc@redhat.com>
798 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
801 2017-04-13 Alan Modra <amodra@gmail.com>
803 * epiphany-desc.c: Regenerate.
804 * fr30-desc.c: Regenerate.
805 * frv-desc.c: Regenerate.
806 * ip2k-desc.c: Regenerate.
807 * iq2000-desc.c: Regenerate.
808 * lm32-desc.c: Regenerate.
809 * m32c-desc.c: Regenerate.
810 * m32r-desc.c: Regenerate.
811 * mep-desc.c: Regenerate.
812 * mt-desc.c: Regenerate.
813 * or1k-desc.c: Regenerate.
814 * xc16x-desc.c: Regenerate.
815 * xstormy16-desc.c: Regenerate.
817 2017-04-11 Alan Modra <amodra@gmail.com>
819 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
820 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
821 PPC_OPCODE_TMR for e6500.
822 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
823 (PPCVEC3): Define as PPC_OPCODE_POWER9.
824 (PPCVSX2): Define as PPC_OPCODE_POWER8.
825 (PPCVSX3): Define as PPC_OPCODE_POWER9.
826 (PPCHTM): Define as PPC_OPCODE_POWER8.
827 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
829 2017-04-10 Alan Modra <amodra@gmail.com>
831 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
832 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
833 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
834 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
836 2017-04-09 Pip Cet <pipcet@gmail.com>
838 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
839 appropriate floating-point precision directly.
841 2017-04-07 Alan Modra <amodra@gmail.com>
843 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
844 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
845 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
846 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
847 vector instructions with E6500 not PPCVEC2.
849 2017-04-06 Pip Cet <pipcet@gmail.com>
851 * Makefile.am: Add wasm32-dis.c.
852 * configure.ac: Add wasm32-dis.c to wasm32 target.
853 * disassemble.c: Add wasm32 disassembler code.
854 * wasm32-dis.c: New file.
855 * Makefile.in: Regenerate.
856 * configure: Regenerate.
857 * po/POTFILES.in: Regenerate.
858 * po/opcodes.pot: Regenerate.
860 2017-04-05 Pedro Alves <palves@redhat.com>
862 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
863 * arm-dis.c (parse_arm_disassembler_options): Constify.
864 * ppc-dis.c (powerpc_init_dialect): Constify local.
865 * vax-dis.c (parse_disassembler_options): Constify.
867 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
869 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
872 2017-03-30 Pip Cet <pipcet@gmail.com>
874 * configure.ac: Add (empty) bfd_wasm32_arch target.
875 * configure: Regenerate
876 * po/opcodes.pot: Regenerate.
878 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
880 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
882 * opcodes/sparc-opc.c (asi_table): New ASIs.
884 2017-03-29 Alan Modra <amodra@gmail.com>
886 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
888 (lookup_powerpc): Don't special case -1 dialect. Handle
890 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
891 lookup_powerpc call, pass it on second.
893 2017-03-27 Alan Modra <amodra@gmail.com>
896 * ppc-dis.c (struct ppc_mopt): Comment.
897 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
899 2017-03-27 Rinat Zelig <rinat@mellanox.com>
901 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
902 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
903 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
904 (insert_nps_misc_imm_offset): New function.
905 (extract_nps_misc imm_offset): New function.
906 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
907 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
909 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
911 * s390-mkopc.c (main): Remove vx2 check.
912 * s390-opc.txt: Remove vx2 instruction flags.
914 2017-03-21 Rinat Zelig <rinat@mellanox.com>
916 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
917 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
918 (insert_nps_imm_offset): New function.
919 (extract_nps_imm_offset): New function.
920 (insert_nps_imm_entry): New function.
921 (extract_nps_imm_entry): New function.
923 2017-03-17 Alan Modra <amodra@gmail.com>
926 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
927 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
928 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
930 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
932 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
936 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
938 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
940 2017-03-13 Andrew Waterman <andrew@sifive.com>
942 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
947 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
949 * i386-gen.c (opcode_modifiers): Replace S with Load.
950 * i386-opc.h (S): Removed.
952 (i386_opcode_modifier): Replace s with load.
953 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
954 and {evex}. Replace S with Load.
955 * i386-tbl.h: Regenerated.
957 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
959 * i386-opc.tbl: Use CpuCET on rdsspq.
960 * i386-tbl.h: Regenerated.
962 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
964 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
965 <vsx>: Do not use PPC_OPCODE_VSX3;
967 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
969 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
971 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
973 * i386-dis.c (REG_0F1E_MOD_3): New enum.
974 (MOD_0F1E_PREFIX_1): Likewise.
975 (MOD_0F38F5_PREFIX_2): Likewise.
976 (MOD_0F38F6_PREFIX_0): Likewise.
977 (RM_0F1E_MOD_3_REG_7): Likewise.
978 (PREFIX_MOD_0_0F01_REG_5): Likewise.
979 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
980 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
981 (PREFIX_0F1E): Likewise.
982 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
983 (PREFIX_0F38F5): Likewise.
984 (dis386_twobyte): Use PREFIX_0F1E.
985 (reg_table): Add REG_0F1E_MOD_3.
986 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
987 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
988 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
989 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
990 (three_byte_table): Use PREFIX_0F38F5.
991 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
992 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
993 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
994 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
995 PREFIX_MOD_3_0F01_REG_5_RM_2.
996 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
997 (cpu_flags): Add CpuCET.
998 * i386-opc.h (CpuCET): New enum.
999 (CpuUnused): Commented out.
1000 (i386_cpu_flags): Add cpucet.
1001 * i386-opc.tbl: Add Intel CET instructions.
1002 * i386-init.h: Regenerated.
1003 * i386-tbl.h: Likewise.
1005 2017-03-06 Alan Modra <amodra@gmail.com>
1008 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1009 (extract_raq, extract_ras, extract_rbx): New functions.
1010 (powerpc_operands): Use opposite corresponding insert function.
1012 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1013 register restriction.
1015 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1017 * disassemble.c Include "safe-ctype.h".
1018 (disassemble_init_for_target): Handle s390 init.
1019 (remove_whitespace_and_extra_commas): New function.
1020 (disassembler_options_cmp): Likewise.
1021 * arm-dis.c: Include "libiberty.h".
1023 (regnames): Use long disassembler style names.
1024 Add force-thumb and no-force-thumb options.
1025 (NUM_ARM_REGNAMES): Rename from this...
1026 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1027 (get_arm_regname_num_options): Delete.
1028 (set_arm_regname_option): Likewise.
1029 (get_arm_regnames): Likewise.
1030 (parse_disassembler_options): Likewise.
1031 (parse_arm_disassembler_option): Rename from this...
1032 (parse_arm_disassembler_options): ...to this. Make static.
1033 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1034 (print_insn): Use parse_arm_disassembler_options.
1035 (disassembler_options_arm): New function.
1036 (print_arm_disassembler_options): Handle updated regnames.
1037 * ppc-dis.c: Include "libiberty.h".
1038 (ppc_opts): Add "32" and "64" entries.
1039 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1040 (powerpc_init_dialect): Add break to switch statement.
1041 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1042 (disassembler_options_powerpc): New function.
1043 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1044 Remove printing of "32" and "64".
1045 * s390-dis.c: Include "libiberty.h".
1046 (init_flag): Remove unneeded variable.
1047 (struct s390_options_t): New structure type.
1048 (options): New structure.
1049 (init_disasm): Rename from this...
1050 (disassemble_init_s390): ...to this. Add initializations for
1051 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1052 (print_insn_s390): Delete call to init_disasm.
1053 (disassembler_options_s390): New function.
1054 (print_s390_disassembler_options): Print using information from
1056 * po/opcodes.pot: Regenerate.
1058 2017-02-28 Jan Beulich <jbeulich@suse.com>
1060 * i386-dis.c (PCMPESTR_Fixup): New.
1061 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1062 (prefix_table): Use PCMPESTR_Fixup.
1063 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1065 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1066 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1067 Split 64-bit and non-64-bit variants.
1068 * opcodes/i386-tbl.h: Re-generate.
1070 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1072 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1073 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1074 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1075 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1076 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1077 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1078 (OP_SVE_V_HSD): New macros.
1079 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1080 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1081 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1082 (aarch64_opcode_table): Add new SVE instructions.
1083 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1084 for rotation operands. Add new SVE operands.
1085 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1086 (ins_sve_quad_index): Likewise.
1087 (ins_imm_rotate): Split into...
1088 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1089 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1090 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1092 (aarch64_ins_sve_addr_ri_s4): New function.
1093 (aarch64_ins_sve_quad_index): Likewise.
1094 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1095 * aarch64-asm-2.c: Regenerate.
1096 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1097 (ext_sve_quad_index): Likewise.
1098 (ext_imm_rotate): Split into...
1099 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1100 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1101 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1103 (aarch64_ext_sve_addr_ri_s4): New function.
1104 (aarch64_ext_sve_quad_index): Likewise.
1105 (aarch64_ext_sve_index): Allow quad indices.
1106 (do_misc_decoding): Likewise.
1107 * aarch64-dis-2.c: Regenerate.
1108 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1109 aarch64_field_kinds.
1110 (OPD_F_OD_MASK): Widen by one bit.
1111 (OPD_F_NO_ZR): Bump accordingly.
1112 (get_operand_field_width): New function.
1113 * aarch64-opc.c (fields): Add new SVE fields.
1114 (operand_general_constraint_met_p): Handle new SVE operands.
1115 (aarch64_print_operand): Likewise.
1116 * aarch64-opc-2.c: Regenerate.
1118 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1120 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1121 (aarch64_feature_compnum): ...this.
1122 (SIMD_V8_3): Replace with...
1124 (CNUM_INSN): New macro.
1125 (aarch64_opcode_table): Use it for the complex number instructions.
1127 2017-02-24 Jan Beulich <jbeulich@suse.com>
1129 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1131 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1133 Add support for associating SPARC ASIs with an architecture level.
1134 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1135 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1136 decoding of SPARC ASIs.
1138 2017-02-23 Jan Beulich <jbeulich@suse.com>
1140 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1141 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1143 2017-02-21 Jan Beulich <jbeulich@suse.com>
1145 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1146 1 (instead of to itself). Correct typo.
1148 2017-02-14 Andrew Waterman <andrew@sifive.com>
1150 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1153 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1155 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1156 (aarch64_sys_reg_supported_p): Handle them.
1158 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1160 * arc-opc.c (UIMM6_20R): Define.
1161 (SIMM12_20): Use above.
1162 (SIMM12_20R): Define.
1163 (SIMM3_5_S): Use above.
1164 (UIMM7_A32_11R_S): Define.
1165 (UIMM7_9_S): Use above.
1166 (UIMM3_13R_S): Define.
1167 (SIMM11_A32_7_S): Use above.
1169 (UIMM10_A32_8_S): Use above.
1170 (UIMM8_8R_S): Define.
1172 (arc_relax_opcodes): Use all above defines.
1174 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1176 * arc-regs.h: Distinguish some of the registers different on
1177 ARC700 and HS38 cpus.
1179 2017-02-14 Alan Modra <amodra@gmail.com>
1182 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1183 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1185 2017-02-11 Stafford Horne <shorne@gmail.com>
1186 Alan Modra <amodra@gmail.com>
1188 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1189 Use insn_bytes_value and insn_int_value directly instead. Don't
1190 free allocated memory until function exit.
1192 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1194 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1196 2017-02-03 Nick Clifton <nickc@redhat.com>
1199 * aarch64-opc.c (print_register_list): Ensure that the register
1200 list index will fir into the tb buffer.
1201 (print_register_offset_address): Likewise.
1202 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1204 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1207 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1208 instructions when the previous fetch packet ends with a 32-bit
1211 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1213 * pru-opc.c: Remove vague reference to a future GDB port.
1215 2017-01-20 Nick Clifton <nickc@redhat.com>
1217 * po/ga.po: Updated Irish translation.
1219 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1221 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1223 2017-01-13 Yao Qi <yao.qi@linaro.org>
1225 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1226 if FETCH_DATA returns 0.
1227 (m68k_scan_mask): Likewise.
1228 (print_insn_m68k): Update code to handle -1 return value.
1230 2017-01-13 Yao Qi <yao.qi@linaro.org>
1232 * m68k-dis.c (enum print_insn_arg_error): New.
1233 (NEXTBYTE): Replace -3 with
1234 PRINT_INSN_ARG_MEMORY_ERROR.
1235 (NEXTULONG): Likewise.
1236 (NEXTSINGLE): Likewise.
1237 (NEXTDOUBLE): Likewise.
1238 (NEXTDOUBLE): Likewise.
1239 (NEXTPACKED): Likewise.
1240 (FETCH_ARG): Likewise.
1241 (FETCH_DATA): Update comments.
1242 (print_insn_arg): Update comments. Replace magic numbers with
1244 (match_insn_m68k): Likewise.
1246 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1248 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1249 * i386-dis-evex.h (evex_table): Updated.
1250 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1251 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1252 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1253 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1254 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1255 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1256 * i386-init.h: Regenerate.
1257 * i386-tbl.h: Ditto.
1259 2017-01-12 Yao Qi <yao.qi@linaro.org>
1261 * msp430-dis.c (msp430_singleoperand): Return -1 if
1262 msp430dis_opcode_signed returns false.
1263 (msp430_doubleoperand): Likewise.
1264 (msp430_branchinstr): Return -1 if
1265 msp430dis_opcode_unsigned returns false.
1266 (msp430x_calla_instr): Likewise.
1267 (print_insn_msp430): Likewise.
1269 2017-01-05 Nick Clifton <nickc@redhat.com>
1272 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1273 could not be matched.
1274 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1277 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1279 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1280 (aarch64_opcode_table): Use RCPC_INSN.
1282 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1284 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1286 * riscv-opcodes/all-opcodes: Likewise.
1288 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1290 * riscv-dis.c (print_insn_args): Add fall through comment.
1292 2017-01-03 Nick Clifton <nickc@redhat.com>
1294 * po/sr.po: New Serbian translation.
1295 * configure.ac (ALL_LINGUAS): Add sr.
1296 * configure: Regenerate.
1298 2017-01-02 Alan Modra <amodra@gmail.com>
1300 * epiphany-desc.h: Regenerate.
1301 * epiphany-opc.h: Regenerate.
1302 * fr30-desc.h: Regenerate.
1303 * fr30-opc.h: Regenerate.
1304 * frv-desc.h: Regenerate.
1305 * frv-opc.h: Regenerate.
1306 * ip2k-desc.h: Regenerate.
1307 * ip2k-opc.h: Regenerate.
1308 * iq2000-desc.h: Regenerate.
1309 * iq2000-opc.h: Regenerate.
1310 * lm32-desc.h: Regenerate.
1311 * lm32-opc.h: Regenerate.
1312 * m32c-desc.h: Regenerate.
1313 * m32c-opc.h: Regenerate.
1314 * m32r-desc.h: Regenerate.
1315 * m32r-opc.h: Regenerate.
1316 * mep-desc.h: Regenerate.
1317 * mep-opc.h: Regenerate.
1318 * mt-desc.h: Regenerate.
1319 * mt-opc.h: Regenerate.
1320 * or1k-desc.h: Regenerate.
1321 * or1k-opc.h: Regenerate.
1322 * xc16x-desc.h: Regenerate.
1323 * xc16x-opc.h: Regenerate.
1324 * xstormy16-desc.h: Regenerate.
1325 * xstormy16-opc.h: Regenerate.
1327 2017-01-02 Alan Modra <amodra@gmail.com>
1329 Update year range in copyright notice of all files.
1331 For older changes see ChangeLog-2016
1333 Copyright (C) 2017 Free Software Foundation, Inc.
1335 Copying and distribution of this file, with or without modification,
1336 are permitted in any medium without royalty provided the copyright
1337 notice and this notice are preserved.
1343 version-control: never