1 2024-01-15 Nick Clifton <nickc@redhat.com>
5 2023-11-15 Arsen Arsenović <arsen@aarsen.me>
7 * aclocal.m4: Regenerate.
8 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
9 temporary file to suppress xgettext checking charset names.
10 * configure.ac (SHARED_LIBADD): Use LTLIBINTL rather than
12 * configure: Regenerate.
13 * po/Make-in ($(srcdir)/$(PACKAGE).pot): Output to a .pot
14 temporary file, to suppress xgettext checking charset names.
16 2023-10-05 Neal frager <neal.frager@amd.com>
18 * microblaze-opcm.h (struct op_code_struct): Tidy and remove
20 * microblaze-opc.h (MAX_OPCODES): Increase to 300.
21 (op_code_struct): Add address extension instructions.
23 2023-10-04 Neal frager <neal.frager@amd.com>
25 * microblaze-opc.h (struct op_code_struct): Add hiberante
27 * microblaze-opcm.h (enum microblaze_instr): Add microblaze_sleep,
28 hibernate, suspend entries.
30 2023-08-24 Tom Tromey <tom@tromey.com>
32 * cgen.sh: Don't pass "-s" to cgen.
33 * Makefile.in: Rebuild.
34 * Makefile.am (GUILE): Simplify.
36 2023-07-31 Jose E. Marchesi <jose.marchesi@oracle.com>
39 * bpf-dis.c (print_insn_bpf): Check that info->section->owner is
40 actually available before using it.
42 2023-07-30 Jose E. Marchesi <jose.marchesi@oracle.com>
44 * bpf-dis.c: Initialize asm_bpf_version to -1.
45 (print_insn_bpf): Set BPF ISA version from the cpu version ELF
46 header flags if no explicit version set in the command line.
47 * disassemble.c (disassemble_init_for_target): Remove unused code.
49 2023-07-26 Jose E. Marchesi <jose.marchesi@oracle.com>
51 * bpf-opc.c (bpf_opcodes): Fix BPF_INSN_NEGR to not use a src
54 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
56 * bpf-opc.c (bpf_opcodes): Add entries for the BSWAP*
59 2023-07-24 Jose E. Marchesi <jose.marchesi@oracle.com>
61 * bpf-opc.c (bpf_opcodes): Fix pseudo-c syntax for MOVS* and LDXS*
64 2023-07-23 Jose E. Marchesi <jose.marchesi@oracle.com>
66 * bpf-opc.c (bpf_opcodes): Add entry for jal.
68 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
70 * bpf-opc.c (bpf_opcodes): Add entries for LDXS{B,W,H,DW}
73 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
75 * bpf-opc.c (bpf_opcodes): Add entries for MOVS{8,16,32}R and
76 MOVS32{8,16,32}R instructions. and MOVS32I instructions.
78 2023-07-21 Jose E. Marchesi <jose.marchesi@oracle.com>
80 * Makefile.am (TARGET64_LIBOPCODES_CFILES): Add missing bpf-dis.c
81 * Makefile.in: Regenerate.
83 2023-07-03 Nick Clifton <nickc@redhat.com>
85 * configure: Regenerate.
86 * po/opcodes.pot: Regenerate.
88 2023-07-03 Nick Clifton <nickc@redhat.com>
92 2023-05-23 Nick Clifton <nickc@redhat.com>
94 * po/sv.po: Updated translation.
96 2023-04-21 Tom Tromey <tromey@adacore.com>
98 * i386-dis.c (OP_J): Check result of get16.
100 2023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
102 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
103 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
104 vsubs2h, and vsubs4h instructions.
106 2023-04-11 Nick Clifton <nickc@redhat.com>
109 * nfp-dis.c (init_nfp6000_priv): Check that the output section
112 2023-03-15 Nick Clifton <nickc@redhat.com>
115 * mep-dis.c: Regenerate.
117 2023-03-15 Nick Clifton <nickc@redhat.com>
120 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
122 2023-02-28 Richard Ball <richard.ball@arm.com>
124 * aarch64-opc.c: Add MEC system registers.
126 2023-01-03 Nick Clifton <nickc@redhat.com>
128 * po/de.po: Updated German translation.
129 * po/ro.po: Updated Romainian translation.
130 * po/uk.po: Updated Ukrainian translation.
132 2022-12-31 Nick Clifton <nickc@redhat.com>
134 * 2.40 branch created.
136 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
138 * arc-regs.h: Change isa_config address to 0xc1.
139 isa_config exists for ARC700 and ARCV2 and not ARCALL.
141 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
143 * rx-decode.opc: Switch arguments of the MVTACGU insn.
144 * rx-decode.c: Regenerate.
146 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
148 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
149 Rm_BANK,Rn is always 1.
151 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
153 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
154 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
155 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
156 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
157 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
158 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
159 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
161 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
163 * disassemble.c (disassemble_init_for_target): Set
164 created_styled_output for ARC based targets.
165 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
166 instead of fprintf_ftype throughout.
167 (find_format): Likewise.
168 (print_flags): Likewise.
169 (print_insn_arc): Likewise.
171 2022-07-08 Nick Clifton <nickc@redhat.com>
173 * 2.39 branch created.
175 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
177 * disassemble.c: (disassemble_init_for_target): Set
178 created_styled_output for AVR based targets.
179 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
180 instead of fprintf_ftype throughout.
181 (avr_operand): Pass in and fill disassembler_style when
184 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
186 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
189 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
191 * configure.ac: Handle bfd_amdgcn_arch.
192 * configure: Re-generate.
194 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
195 Maciej W. Rozycki <macro@orcam.me.uk>
197 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
198 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
199 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
202 2022-02-17 Nick Clifton <nickc@redhat.com>
204 * po/sr.po: Updated Serbian translation.
206 2022-02-14 Sergei Trofimovich <siarheit@google.com>
208 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
209 * microblaze-opc.h: Follow 'fsqrt' rename.
211 2022-01-24 Nick Clifton <nickc@redhat.com>
213 * po/ro.po: Updated Romanian translation.
214 * po/uk.po: Updated Ukranian translation.
216 2022-01-22 Nick Clifton <nickc@redhat.com>
218 * configure: Regenerate.
219 * po/opcodes.pot: Regenerate.
221 2022-01-22 Nick Clifton <nickc@redhat.com>
223 * 2.38 release branch created.
225 2022-01-17 Nick Clifton <nickc@redhat.com>
227 * Makefile.in: Regenerate.
228 * po/opcodes.pot: Regenerate.
230 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
232 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
233 in insn_type on branching instructions.
235 2021-11-25 Andrew Burgess <aburgess@redhat.com>
236 Simon Cook <simon.cook@embecosm.com>
238 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
239 (riscv_options): New static global.
240 (disassembler_options_riscv): New function.
241 (print_riscv_disassembler_options): Rewrite to use
242 disassembler_options_riscv.
244 2021-11-25 Nick Clifton <nickc@redhat.com>
247 * aarch64-asm.c: Replace assert(0) with real code.
248 * aarch64-dis.c: Likewise.
249 * aarch64-opc.c: Likewise.
251 2021-11-25 Nick Clifton <nickc@redhat.com>
253 * po/fr.po; Updated French translation.
255 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
257 * Makefile.am: Remove obsolete comment.
258 * configure.ac: Refer `libbfd.la' to link shared BFD library
260 * Makefile.in: Regenerate.
261 * configure: Regenerate.
263 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
265 * configure: Regenerate.
267 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
269 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
272 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
274 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
275 before an unknown instruction, '%d' is replaced with the
278 2021-09-02 Nick Clifton <nickc@redhat.com>
281 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
284 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
286 * arc-regs.h (DEF): Fix the register numbers.
288 2021-08-10 Nick Clifton <nickc@redhat.com>
290 * po/sr.po: Updated Serbian translation.
292 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
294 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
296 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
298 * s390-opc.txt: Add qpaci.
300 2021-07-03 Nick Clifton <nickc@redhat.com>
302 * configure: Regenerate.
303 * po/opcodes.pot: Regenerate.
305 2021-07-03 Nick Clifton <nickc@redhat.com>
307 * 2.37 release branch created.
309 2021-07-02 Alan Modra <amodra@gmail.com>
311 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
312 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
313 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
314 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
315 (nds32_keyword_gpr): Move declarations to..
316 * nds32-asm.h: ..here, constifying to match definitions.
318 2021-07-01 Mike Frysinger <vapier@gentoo.org>
320 * Makefile.am (GUILE): New variable.
321 (CGEN): Use $(GUILE).
322 * Makefile.in: Regenerate.
324 2021-07-01 Mike Frysinger <vapier@gentoo.org>
326 * mep-asm.c (macros): Mark static & const.
327 (lookup_macro): Change return & m to const.
328 (expand_macro): Change mac to const.
329 (expand_string): Change pmacro to const.
331 2021-07-01 Mike Frysinger <vapier@gentoo.org>
333 * nds32-asm.c (operand_fields): Rename to ...
334 (nds32_operand_fields): ... this.
335 (keyword_gpr): Rename to ...
336 (nds32_keyword_gpr): ... this.
337 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
338 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
339 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
340 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
341 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
343 (keywords): Rename to ...
344 (nds32_keywords): ... this.
345 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
346 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
348 2021-07-01 Mike Frysinger <vapier@gentoo.org>
350 * z80-dis.c (opc_ed): Make const.
351 (pref_ed): Make p const.
353 2021-07-01 Mike Frysinger <vapier@gentoo.org>
355 * microblaze-dis.c (get_field_special): Make op const.
356 (read_insn_microblaze): Make opr & op const. Rename opcodes to
358 (print_insn_microblaze): Make op & pop const.
359 (get_insn_microblaze): Make op const. Rename opcodes to
361 (microblaze_get_target_address): Likewise.
362 * microblaze-opc.h (struct op_code_struct): Make const.
363 Rename opcodes to microblaze_opcodes.
365 2021-07-01 Mike Frysinger <vapier@gentoo.org>
367 * aarch64-gen.c (aarch64_opcode_table): Add const.
368 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
370 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
372 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
375 2021-06-22 Alan Modra <amodra@gmail.com>
377 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
378 print separator for pcrel insns.
380 2021-06-19 Alan Modra <amodra@gmail.com>
382 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
384 2021-06-19 Alan Modra <amodra@gmail.com>
386 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
389 2021-06-17 Alan Modra <amodra@gmail.com>
391 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
394 2021-06-03 Alan Modra <amodra@gmail.com>
397 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
398 Use unsigned int for inst.
400 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
402 * arc-dis.c (arc_option_arg_t): New enumeration.
403 (arc_options): New variable.
404 (disassembler_options_arc): New function.
405 (print_arc_disassembler_options): Reimplement in terms of
406 "disassembler_options_arc".
408 2021-05-29 Alan Modra <amodra@gmail.com>
410 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
411 Don't special case PPC_OPCODE_RAW.
412 (lookup_prefix): Likewise.
413 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
414 (print_insn_powerpc): ..update caller.
415 * ppc-opc.c (EXT): Define.
416 (powerpc_opcodes): Mark extended mnemonics with EXT.
417 (prefix_opcodes, vle_opcodes): Likewise.
418 (XISEL, XISEL_MASK): Add cr field and simplify.
419 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
420 all isel variants to where the base mnemonic belongs. Sort dstt,
423 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
425 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
426 COP3 opcode instructions.
428 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
430 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
431 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
432 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
433 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
434 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
435 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
436 "cop2", and "cop3" entries.
438 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
440 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
441 entries and associated comments.
443 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
445 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
448 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
450 * mips-dis.c (mips_cp1_names_mips): New variable.
451 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
452 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
453 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
454 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
455 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
458 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
460 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
461 handling code over to...
462 <OP_REG_CONTROL>: ... this new case.
463 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
464 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
465 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
466 replacing the `G' operand code with `g'. Update "cftc1" and
467 "cftc2" entries replacing the `E' operand code with `y'.
468 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
469 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
470 entries replacing the `G' operand code with `g'.
472 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
474 * mips-dis.c (mips_cp0_names_r3900): New variable.
475 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
478 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
480 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
481 and "mtthc2" to using the `G' rather than `g' operand code for
482 the coprocessor control register referred.
484 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
486 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
487 entries with each other.
489 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
491 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
493 2021-05-25 Alan Modra <amodra@gmail.com>
495 * cris-desc.c: Regenerate.
496 * cris-desc.h: Regenerate.
497 * cris-opc.h: Regenerate.
498 * po/POTFILES.in: Regenerate.
500 2021-05-24 Mike Frysinger <vapier@gentoo.org>
502 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
503 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
504 (CGEN_CPUS): Add cris.
506 (stamp-cris): New rule.
507 * cgen.sh: Handle desc action.
508 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
509 * Makefile.in, configure: Regenerate.
511 2021-05-18 Job Noorman <mtvec@pm.me>
514 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
517 2021-05-17 Alex Coplan <alex.coplan@arm.com>
519 * arm-dis.c (mve_opcodes): Fix disassembly of
520 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
521 (is_mve_encoding_conflict): MVE vector loads should not match
523 (is_mve_unpredictable): It's not unpredictable to use the same
524 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
526 2021-05-11 Nick Clifton <nickc@redhat.com>
529 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
530 the end of the code buffer.
532 2021-05-06 Stafford Horne <shorne@gmail.com>
535 * or1k-asm.c: Regenerate.
537 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
539 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
540 info->insn_info_valid.
542 2021-04-26 Jan Beulich <jbeulich@suse.com>
544 * i386-opc.tbl (lea): Add Optimize.
545 * opcodes/i386-tbl.h: Re-generate.
547 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
549 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
550 of l32r fetch and display referenced literal value.
552 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
554 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
555 to 4 for literal disassembly.
557 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
559 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
560 for TLBI instruction.
562 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
564 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
567 2021-04-19 Jan Beulich <jbeulich@suse.com>
569 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
571 (convert_mov_to_movewide): Add initializer for "value".
573 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
575 * aarch64-opc.c: Add RME system registers.
577 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
579 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
580 "addi d,CV,z" to "c.mv d,CV".
582 2021-04-12 Alan Modra <amodra@gmail.com>
584 * configure.ac (--enable-checking): Add support.
585 * config.in: Regenerate.
586 * configure: Regenerate.
588 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
590 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
591 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
593 2021-04-09 Alan Modra <amodra@gmail.com>
595 * ppc-dis.c (struct dis_private): Add "special".
596 (POWERPC_DIALECT): Delete. Replace uses with..
597 (private_data): ..this. New inline function.
598 (disassemble_init_powerpc): Init "special" names.
599 (skip_optional_operands): Add is_pcrel arg, set when detecting R
600 field of prefix instructions.
601 (bsearch_reloc, print_got_plt): New functions.
602 (print_insn_powerpc): For pcrel instructions, print target address
603 and symbol if known, and decode plt and got loads too.
605 2021-04-08 Alan Modra <amodra@gmail.com>
608 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
610 2021-04-08 Alan Modra <amodra@gmail.com>
613 * ppc-opc.c (DCBT_EO): Move earlier.
614 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
615 (powerpc_operands): Add THCT and THDS entries.
616 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
618 2021-04-06 Alan Modra <amodra@gmail.com>
620 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
621 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
622 symbol_at_address_func.
624 2021-04-05 Alan Modra <amodra@gmail.com>
626 * configure.ac: Don't check for limits.h, string.h, strings.h or
628 (AC_ISC_POSIX): Don't invoke.
629 * sysdep.h: Include stdlib.h and string.h unconditionally.
630 * i386-opc.h: Include limits.h unconditionally.
631 * wasm32-dis.c: Likewise.
632 * cgen-opc.c: Don't include alloca-conf.h.
633 * config.in: Regenerate.
634 * configure: Regenerate.
636 2021-04-01 Martin Liska <mliska@suse.cz>
638 * arm-dis.c (strneq): Remove strneq and use startswith.
639 * cr16-dis.c (print_insn_cr16): Likewise.
640 * score-dis.c (streq): Likewise.
642 * score7-dis.c (strneq): Likewise.
644 2021-04-01 Alan Modra <amodra@gmail.com>
647 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
649 2021-03-31 Alan Modra <amodra@gmail.com>
651 * sysdep.h (POISON_BFD_BOOLEAN): Define.
652 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
653 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
654 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
655 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
656 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
657 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
658 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
659 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
660 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
661 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
662 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
663 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
664 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
665 and TRUE with true throughout.
667 2021-03-31 Alan Modra <amodra@gmail.com>
669 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
670 * aarch64-dis.h: Likewise.
671 * aarch64-opc.c: Likewise.
672 * avr-dis.c: Likewise.
673 * csky-dis.c: Likewise.
674 * nds32-asm.c: Likewise.
675 * nds32-dis.c: Likewise.
676 * nfp-dis.c: Likewise.
677 * riscv-dis.c: Likewise.
678 * s12z-dis.c: Likewise.
679 * wasm32-dis.c: Likewise.
681 2021-03-30 Jan Beulich <jbeulich@suse.com>
683 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
684 (i386_seg_prefixes): New.
685 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
686 (i386_seg_prefixes): Declare.
688 2021-03-30 Jan Beulich <jbeulich@suse.com>
690 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
692 2021-03-30 Jan Beulich <jbeulich@suse.com>
694 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
695 * i386-reg.tbl (st): Move down.
696 (st(0)): Delete. Extend comment.
697 * i386-tbl.h: Re-generate.
699 2021-03-29 Jan Beulich <jbeulich@suse.com>
701 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
702 (cmpsd): Move next to cmps.
703 (movsd): Move next to movs.
704 (cmpxchg16b): Move to separate section.
705 (fisttp, fisttpll): Likewise.
706 (monitor, mwait): Likewise.
707 * i386-tbl.h: Re-generate.
709 2021-03-29 Jan Beulich <jbeulich@suse.com>
711 * i386-opc.tbl (psadbw): Add <sse2:comm>.
713 * i386-tbl.h: Re-generate.
715 2021-03-29 Jan Beulich <jbeulich@suse.com>
717 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
718 pclmul, gfni): New templates. Use them wherever possible. Move
719 SSE4.1 pextrw into respective section.
720 * i386-tbl.h: Re-generate.
722 2021-03-29 Jan Beulich <jbeulich@suse.com>
724 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
725 strtoull(). Bump upper loop bound. Widen masks. Sanity check
727 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
728 Convert all of their uses to representation in opcode.
730 2021-03-29 Jan Beulich <jbeulich@suse.com>
732 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
733 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
734 value of None. Shrink operands to 3 bits.
736 2021-03-29 Jan Beulich <jbeulich@suse.com>
738 * i386-gen.c (process_i386_opcode_modifier): New parameter
740 (output_i386_opcode): New local variable "space". Adjust
741 process_i386_opcode_modifier() invocation.
742 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
744 * i386-tbl.h: Re-generate.
746 2021-03-29 Alan Modra <amodra@gmail.com>
748 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
749 (fp_qualifier_p, get_data_pattern): Likewise.
750 (aarch64_get_operand_modifier_from_value): Likewise.
751 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
752 (operand_variant_qualifier_p): Likewise.
753 (qualifier_value_in_range_constraint_p): Likewise.
754 (aarch64_get_qualifier_esize): Likewise.
755 (aarch64_get_qualifier_nelem): Likewise.
756 (aarch64_get_qualifier_standard_value): Likewise.
757 (get_lower_bound, get_upper_bound): Likewise.
758 (aarch64_find_best_match, match_operands_qualifier): Likewise.
759 (aarch64_print_operand): Likewise.
760 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
761 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
762 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
763 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
764 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
765 (print_insn_tic6x): Likewise.
767 2021-03-29 Alan Modra <amodra@gmail.com>
769 * arc-dis.c (extract_operand_value): Correct NULL cast.
770 * frv-opc.h: Regenerate.
772 2021-03-26 Jan Beulich <jbeulich@suse.com>
774 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
776 * i386-tbl.h: Re-generate.
778 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
780 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
781 immediate in br.n instruction.
783 2021-03-25 Jan Beulich <jbeulich@suse.com>
785 * i386-dis.c (XMGatherD, VexGatherD): New.
786 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
787 (print_insn): Check masking for S/G insns.
788 (OP_E_memory): New local variable check_gather. Extend mandatory
789 SIB check. Check register conflicts for (EVEX-encoded) gathers.
790 Extend check for disallowed 16-bit addressing.
791 (OP_VEX): New local variables modrm_reg and sib_index. Convert
792 if()s to switch(). Check register conflicts for (VEX-encoded)
793 gathers. Drop no longer reachable cases.
794 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
797 2021-03-25 Jan Beulich <jbeulich@suse.com>
799 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
800 zeroing-masking without masking.
802 2021-03-25 Jan Beulich <jbeulich@suse.com>
804 * i386-opc.tbl (invlpgb): Fix multi-operand form.
805 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
806 single-operand forms as deprecated.
807 * i386-tbl.h: Re-generate.
809 2021-03-25 Alan Modra <amodra@gmail.com>
812 * ppc-opc.c (XLOCB_MASK): Delete.
813 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
815 (powerpc_opcodes): Accept a BH field on all extended forms of
816 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
818 2021-03-24 Jan Beulich <jbeulich@suse.com>
820 * i386-gen.c (output_i386_opcode): Drop processing of
821 opcode_length. Calculate length from base_opcode. Adjust prefix
822 encoding determination.
823 (process_i386_opcodes): Drop output of fake opcode_length.
824 * i386-opc.h (struct insn_template): Drop opcode_length field.
825 * i386-opc.tbl: Drop opcode length field from all templates.
826 * i386-tbl.h: Re-generate.
828 2021-03-24 Jan Beulich <jbeulich@suse.com>
830 * i386-gen.c (process_i386_opcode_modifier): Return void. New
831 parameter "prefix". Drop local variable "regular_encoding".
832 Record prefix setting / check for consistency.
833 (output_i386_opcode): Parse opcode_length and base_opcode
834 earlier. Derive prefix encoding. Drop no longer applicable
835 consistency checking. Adjust process_i386_opcode_modifier()
837 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
839 * i386-tbl.h: Re-generate.
841 2021-03-24 Jan Beulich <jbeulich@suse.com>
843 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
845 * i386-opc.h (Prefix_*): Move #define-s.
846 * i386-opc.tbl: Move pseudo prefix enumerator values to
847 extension opcode field. Introduce pseudopfx template.
848 * i386-tbl.h: Re-generate.
850 2021-03-23 Jan Beulich <jbeulich@suse.com>
852 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
854 * i386-tbl.h: Re-generate.
856 2021-03-23 Jan Beulich <jbeulich@suse.com>
858 * i386-opc.h (struct insn_template): Move cpu_flags field past
860 * i386-tbl.h: Re-generate.
862 2021-03-23 Jan Beulich <jbeulich@suse.com>
864 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
865 * i386-opc.h (OpcodeSpace): New enumerator.
866 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
867 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
868 SPACE_XOP09, SPACE_XOP0A): ... respectively.
869 (struct i386_opcode_modifier): New field opcodespace. Shrink
871 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
872 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
874 * i386-tbl.h: Re-generate.
876 2021-03-22 Martin Liska <mliska@suse.cz>
878 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
879 * arc-dis.c (parse_option): Likewise.
880 * arm-dis.c (parse_arm_disassembler_options): Likewise.
881 * cris-dis.c (print_with_operands): Likewise.
882 * h8300-dis.c (bfd_h8_disassemble): Likewise.
883 * i386-dis.c (print_insn): Likewise.
884 * ia64-gen.c (fetch_insn_class): Likewise.
885 (parse_resource_users): Likewise.
886 (in_iclass): Likewise.
887 (lookup_specifier): Likewise.
888 (insert_opcode_dependencies): Likewise.
889 * mips-dis.c (parse_mips_ase_option): Likewise.
890 (parse_mips_dis_option): Likewise.
891 * s390-dis.c (disassemble_init_s390): Likewise.
892 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
894 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
896 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
898 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
900 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
901 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
903 2021-03-12 Alan Modra <amodra@gmail.com>
905 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
907 2021-03-11 Jan Beulich <jbeulich@suse.com>
909 * i386-dis.c (OP_XMM): Re-order checks.
911 2021-03-11 Jan Beulich <jbeulich@suse.com>
913 * i386-dis.c (putop): Drop need_vex check when also checking
915 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
918 2021-03-11 Jan Beulich <jbeulich@suse.com>
920 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
921 checks. Move case label past broadcast check.
923 2021-03-10 Jan Beulich <jbeulich@suse.com>
925 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
926 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
927 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
928 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
929 EVEX_W_0F38C7_M_0_L_2): Delete.
930 (REG_EVEX_0F38C7_M_0_L_2): New.
931 (intel_operand_size): Handle VEX and EVEX the same for
932 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
933 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
934 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
935 vex_vsib_q_w_d_mode uses.
936 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
937 0F38A1, and 0F38A3 entries.
938 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
940 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
941 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
944 2021-03-10 Jan Beulich <jbeulich@suse.com>
946 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
947 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
948 MOD_VEX_0FXOP_09_12): Rename to ...
949 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
950 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
951 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
952 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
953 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
954 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
955 (reg_table): Adjust comments.
956 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
957 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
958 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
959 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
960 (vex_len_table): Adjust opcode 0A_12 entry.
961 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
962 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
963 (rm_table): Move hreset entry.
965 2021-03-10 Jan Beulich <jbeulich@suse.com>
967 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
968 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
969 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
970 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
971 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
972 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
973 (get_valid_dis386): Also handle 512-bit vector length when
974 vectoring into vex_len_table[].
975 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
976 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
978 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
979 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
980 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
981 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
984 2021-03-10 Jan Beulich <jbeulich@suse.com>
986 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
987 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
988 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
989 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
991 * i386-dis-evex-len.h (evex_len_table): Likewise.
992 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
994 2021-03-10 Jan Beulich <jbeulich@suse.com>
996 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
997 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
998 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
999 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
1000 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
1001 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
1002 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
1003 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
1004 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
1005 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
1006 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
1007 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
1008 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
1009 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
1010 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
1011 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
1012 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
1013 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
1014 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
1015 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
1016 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
1017 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
1018 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
1019 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
1020 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
1021 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
1022 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
1023 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
1024 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
1025 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
1026 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
1027 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
1028 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
1029 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
1030 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
1031 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
1032 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
1033 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
1034 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
1035 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
1036 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
1037 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
1038 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
1039 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
1040 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
1041 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
1042 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
1043 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
1044 EVEX_W_0F3A43_L_n): New.
1045 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
1046 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
1047 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
1048 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
1049 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
1050 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
1051 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
1052 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
1053 0F385B, 0F38C6, and 0F38C7 entries.
1054 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
1056 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
1057 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
1058 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
1059 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
1061 2021-03-10 Jan Beulich <jbeulich@suse.com>
1063 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
1064 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
1065 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
1066 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
1067 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
1068 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
1069 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
1070 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
1071 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
1072 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
1073 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
1074 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
1075 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1076 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1077 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1078 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1079 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1080 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1081 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1082 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1083 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1084 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1085 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1086 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1087 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1088 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1089 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1090 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1091 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1092 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1093 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1094 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1095 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1096 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1097 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1098 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1099 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1100 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1101 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1102 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1103 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1104 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1105 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1106 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1107 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1108 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1109 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1110 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1111 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1112 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1113 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1114 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1115 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1116 VEX_W_0F99_P_2_LEN_0): Delete.
1117 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1118 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1119 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1120 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1121 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1122 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1123 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1124 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1125 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1126 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1127 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1128 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1129 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1130 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1131 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1132 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1133 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1134 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1135 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1136 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1137 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1138 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1139 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1140 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1141 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1142 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1143 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1144 (prefix_table): No longer link to vex_len_table[] for opcodes
1145 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1146 0F92, 0F93, 0F98, and 0F99.
1147 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1148 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1150 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1151 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1153 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1154 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1156 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1157 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1160 2021-03-10 Jan Beulich <jbeulich@suse.com>
1162 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1163 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1164 REG_VEX_0F73_M_0 respectively.
1165 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1166 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1167 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1168 MOD_VEX_0F73_REG_7): Delete.
1169 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1170 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1171 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1172 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1173 PREFIX_VEX_0F3AF0_L_0 respectively.
1174 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1175 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1176 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1177 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1178 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1179 VEX_LEN_0F38F7): New.
1180 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1181 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1182 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1184 (prefix_table): No longer link to vex_len_table[] for opcodes
1185 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1186 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1187 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1188 0F38F6, 0F38F7, and 0F3AF0.
1189 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1190 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1191 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1194 2021-03-10 Jan Beulich <jbeulich@suse.com>
1196 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1197 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1198 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1199 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1200 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1201 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1202 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1204 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1206 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1209 2021-03-10 Jan Beulich <jbeulich@suse.com>
1211 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1212 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1213 (reg_table): Don't link to mod_table[] where not needed. Add
1214 PREFIX_IGNORED to nop entries.
1215 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1216 (mod_table): Add nop entries next to prefetch ones. Drop
1217 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1218 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1219 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1220 PREFIX_OPCODE from endbr* entries.
1221 (get_valid_dis386): Also consider entry's name when zapping
1223 (print_insn): Handle PREFIX_IGNORED.
1225 2021-03-09 Jan Beulich <jbeulich@suse.com>
1227 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1228 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1230 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1231 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1232 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1233 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1234 (struct i386_opcode_modifier): Delete notrackprefixok,
1235 islockable, hleprefixok, and repprefixok fields. Add prefixok
1237 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1238 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1239 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1240 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1241 Replace HLEPrefixOk.
1242 * opcodes/i386-tbl.h: Re-generate.
1244 2021-03-09 Jan Beulich <jbeulich@suse.com>
1246 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1247 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1249 * opcodes/i386-tbl.h: Re-generate.
1251 2021-03-03 Jan Beulich <jbeulich@suse.com>
1253 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1254 for {} instead of {0}. Don't look for '0'.
1255 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1258 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1261 * riscv-dis.c (print_insn_args): Updated encoding macros.
1262 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1263 (match_c_addi16sp): Updated encoding macros.
1264 (match_c_lui): Likewise.
1265 (match_c_lui_with_hint): Likewise.
1266 (match_c_addi4spn): Likewise.
1267 (match_c_slli): Likewise.
1268 (match_slli_as_c_slli): Likewise.
1269 (match_c_slli64): Likewise.
1270 (match_srxi_as_c_srxi): Likewise.
1271 (riscv_insn_types): Added .insn css/cl/cs.
1273 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1275 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1276 (default_priv_spec): Updated type to riscv_spec_class.
1277 (parse_riscv_dis_option): Updated.
1278 * riscv-opc.c: Moved stuff and make the file tidy.
1280 2021-02-17 Alan Modra <amodra@gmail.com>
1282 * wasm32-dis.c: Include limits.h.
1283 (CHAR_BIT): Provide backup define.
1284 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1285 Correct signed overflow checking.
1287 2021-02-16 Jan Beulich <jbeulich@suse.com>
1289 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1290 * i386-tbl.h: Re-generate.
1292 2021-02-16 Jan Beulich <jbeulich@suse.com>
1294 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1296 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1298 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1300 * s390-mkopc.c (main): Accept arch14 as cpu string.
1301 * s390-opc.txt: Add new arch14 instructions.
1303 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1305 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1307 * configure: Regenerated.
1309 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1311 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1312 * tic54x-opc.c (regs): Rename to ...
1313 (tic54x_regs): ... this.
1314 (mmregs): Rename to ...
1315 (tic54x_mmregs): ... this.
1316 (condition_codes): Rename to ...
1317 (tic54x_condition_codes): ... this.
1318 (cc2_codes): Rename to ...
1319 (tic54x_cc2_codes): ... this.
1320 (cc3_codes): Rename to ...
1321 (tic54x_cc3_codes): ... this.
1322 (status_bits): Rename to ...
1323 (tic54x_status_bits): ... this.
1324 (misc_symbols): Rename to ...
1325 (tic54x_misc_symbols): ... this.
1327 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1329 * riscv-opc.c (MASK_RVB_IMM): Removed.
1330 (riscv_opcodes): Removed zb* instructions.
1331 (riscv_ext_version_table): Removed versions for zb*.
1333 2021-01-26 Alan Modra <amodra@gmail.com>
1335 * i386-gen.c (parse_template): Ensure entire template_instance
1338 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1340 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1341 (riscv_fpr_names_abi): Likewise.
1342 (riscv_opcodes): Likewise.
1343 (riscv_insn_types): Likewise.
1345 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1347 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1349 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1351 * riscv-dis.c: Comments tidy and improvement.
1352 * riscv-opc.c: Likewise.
1354 2021-01-13 Alan Modra <amodra@gmail.com>
1356 * Makefile.in: Regenerate.
1358 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1361 * configure.ac: Use GNU_MAKE_JOBSERVER.
1362 * aclocal.m4: Regenerated.
1363 * configure: Likewise.
1365 2021-01-12 Nick Clifton <nickc@redhat.com>
1367 * po/sr.po: Updated Serbian translation.
1369 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1372 * configure: Regenerated.
1374 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1376 * aarch64-asm-2.c: Regenerate.
1377 * aarch64-dis-2.c: Likewise.
1378 * aarch64-opc-2.c: Likewise.
1379 * aarch64-opc.c (aarch64_print_operand):
1380 Delete handling of AARCH64_OPND_CSRE_CSR.
1381 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1383 (_CSRE_INSN): Likewise.
1384 (aarch64_opcode_table): Delete csr.
1386 2021-01-11 Nick Clifton <nickc@redhat.com>
1388 * po/de.po: Updated German translation.
1389 * po/fr.po: Updated French translation.
1390 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1391 * po/sv.po: Updated Swedish translation.
1392 * po/uk.po: Updated Ukranian translation.
1394 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1396 * configure: Regenerated.
1398 2021-01-09 Nick Clifton <nickc@redhat.com>
1400 * configure: Regenerate.
1401 * po/opcodes.pot: Regenerate.
1403 2021-01-09 Nick Clifton <nickc@redhat.com>
1405 * 2.36 release branch crated.
1407 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1409 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1410 (DW, (XRC_MASK): Define.
1411 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1413 2021-01-09 Alan Modra <amodra@gmail.com>
1415 * configure: Regenerate.
1417 2021-01-08 Nick Clifton <nickc@redhat.com>
1419 * po/sv.po: Updated Swedish translation.
1421 2021-01-08 Nick Clifton <nickc@redhat.com>
1424 * aarch64-dis.c (determine_disassembling_preference): Move call to
1425 aarch64_match_operands_constraint outside of the assertion.
1426 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1427 Replace with a return of FALSE.
1430 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1431 core system register.
1433 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1435 * configure: Regenerate.
1437 2021-01-07 Nick Clifton <nickc@redhat.com>
1439 * po/fr.po: Updated French translation.
1441 2021-01-07 Fredrik Noring <noring@nocrew.org>
1443 * m68k-opc.c (chkl): Change minimum architecture requirement to
1446 2021-01-07 Philipp Tomsich <prt@gnu.org>
1448 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1450 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1451 Jim Wilson <jimw@sifive.com>
1452 Andrew Waterman <andrew@sifive.com>
1453 Maxim Blinov <maxim.blinov@embecosm.com>
1454 Kito Cheng <kito.cheng@sifive.com>
1455 Nelson Chu <nelson.chu@sifive.com>
1457 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1458 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1460 2021-01-01 Alan Modra <amodra@gmail.com>
1462 Update year range in copyright notice of all files.
1464 For older changes see ChangeLog-2020
1466 Copyright (C) 2021-2024 Free Software Foundation, Inc.
1468 Copying and distribution of this file, with or without modification,
1469 are permitted in any medium without royalty provided the copyright
1470 notice and this notice are preserved.
1476 version-control: never