1 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
3 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
4 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
5 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
6 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
9 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
11 * aarch64-opc.c (get_offset_int_reg_name): New function.
12 (print_immediate_offset_address): Likewise.
13 (print_register_offset_address): Take the base and offset
14 registers as parameters.
15 (aarch64_print_operand): Update caller accordingly. Use
16 print_immediate_offset_address.
18 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
20 * aarch64-opc.c (BANK): New macro.
21 (R32, R64): Take a register number as argument
24 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
26 * aarch64-opc.c (print_register_list): Add a prefix parameter.
27 (aarch64_print_operand): Update accordingly.
29 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
31 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
33 * aarch64-asm.h (ins_fpimm): New inserter.
34 * aarch64-asm.c (aarch64_ins_fpimm): New function.
35 * aarch64-asm-2.c: Regenerate.
36 * aarch64-dis.h (ext_fpimm): New extractor.
37 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
38 (aarch64_ext_fpimm): New function.
39 * aarch64-dis-2.c: Regenerate.
41 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
43 * aarch64-asm.c: Include libiberty.h.
44 (insert_fields): New function.
45 (aarch64_ins_imm): Use it.
46 * aarch64-dis.c (extract_fields): New function.
47 (aarch64_ext_imm): Use it.
49 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
51 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
52 with an esize parameter.
53 (operand_general_constraint_met_p): Update accordingly.
55 * aarch64-asm.c (aarch64_ins_limm): Update call to
56 aarch64_logical_immediate_p.
58 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
60 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
62 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
64 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
66 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
68 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
70 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
72 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
73 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
74 xor3>: Delete mnemonics.
75 <cp_abort>: Rename mnemonic from ...
76 <cpabort>: ...to this.
77 <setb>: Change to a X form instruction.
78 <sync>: Change to 1 operand form.
79 <copy>: Delete mnemonic.
80 <copy_first>: Rename mnemonic from ...
82 <paste, paste.>: Delete mnemonics.
83 <paste_last>: Rename mnemonic from ...
86 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
88 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
90 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
92 * s390-mkopc.c (main): Support alternate arch strings.
94 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
96 * s390-opc.txt: Fix kmctr instruction type.
98 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
100 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
101 * i386-init.h: Regenerated.
103 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
105 * opcodes/arc-dis.c (print_insn_arc): Changed.
107 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
109 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
112 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
114 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
115 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
116 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
118 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
120 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
121 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
122 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
123 PREFIX_MOD_3_0FAE_REG_4.
124 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
125 PREFIX_MOD_3_0FAE_REG_4.
126 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
127 (cpu_flags): Add CpuPTWRITE.
128 * i386-opc.h (CpuPTWRITE): New.
129 (i386_cpu_flags): Add cpuptwrite.
130 * i386-opc.tbl: Add ptwrite instruction.
131 * i386-init.h: Regenerated.
132 * i386-tbl.h: Likewise.
134 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
136 * arc-dis.h: Wrap around in extern "C".
138 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
140 * aarch64-tbl.h (V8_2_INSN): New macro.
141 (aarch64_opcode_table): Use it.
143 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
145 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
146 CORE_INSN, __FP_INSN and SIMD_INSN.
148 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
150 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
151 (aarch64_opcode_table): Update uses accordingly.
153 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
154 Kwok Cheung Yeung <kcy@codesourcery.com>
157 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
158 'e_cmplwi' to 'e_cmpli' instead.
159 (OPVUPRT, OPVUPRT_MASK): Define.
160 (powerpc_opcodes): Add E200Z4 insns.
161 (vle_opcodes): Add context save/restore insns.
163 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
165 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
166 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
169 2016-07-27 Graham Markall <graham.markall@embecosm.com>
171 * arc-nps400-tbl.h: Change block comments to GNU format.
172 * arc-dis.c: Add new globals addrtypenames,
173 addrtypenames_max, and addtypeunknown.
174 (get_addrtype): New function.
175 (print_insn_arc): Print colons and address types when
177 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
178 define insert and extract functions for all address types.
179 (arc_operands): Add operands for colon and all address
181 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
182 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
183 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
184 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
185 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
186 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
188 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
190 * configure: Regenerated.
192 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
194 * arc-dis.c (skipclass): New structure.
195 (decodelist): New variable.
196 (is_compatible_p): New function.
197 (new_element): Likewise.
198 (skip_class_p): Likewise.
199 (find_format_from_table): Use skip_class_p function.
200 (find_format): Decode first the extension instructions.
201 (print_insn_arc): Select either ARCEM or ARCHS based on elf
203 (parse_option): New function.
204 (parse_disassembler_options): Likewise.
205 (print_arc_disassembler_options): Likewise.
206 (print_insn_arc): Use parse_disassembler_options function. Proper
207 select ARCv2 cpu variant.
208 * disassemble.c (disassembler_usage): Add ARC disassembler
211 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
213 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
214 annotation from the "nal" entry and reorder it beyond "bltzal".
216 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
218 * sparc-opc.c (ldtxa): New macro.
219 (sparc_opcodes): Use the macro defined above to add entries for
220 the LDTXA instructions.
221 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
224 2016-07-07 James Bowman <james.bowman@ftdichip.com>
226 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
229 2016-07-01 Jan Beulich <jbeulich@suse.com>
231 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
232 (movzb): Adjust to cover all permitted suffixes.
234 * i386-tbl.h: Re-generate.
236 2016-07-01 Jan Beulich <jbeulich@suse.com>
238 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
239 (lgdt): Remove Tbyte from non-64-bit variant.
240 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
241 xsaves64, xsavec64): Remove Disp16.
242 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
243 Remove Disp32S from non-64-bit variants. Remove Disp16 from
245 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
246 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
247 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
249 * i386-tbl.h: Re-generate.
251 2016-07-01 Jan Beulich <jbeulich@suse.com>
253 * i386-opc.tbl (xlat): Remove RepPrefixOk.
254 * i386-tbl.h: Re-generate.
256 2016-06-30 Yao Qi <yao.qi@linaro.org>
258 * arm-dis.c (print_insn): Fix typo in comment.
260 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
262 * aarch64-opc.c (operand_general_constraint_met_p): Check the
263 range of ldst_elemlist operands.
264 (print_register_list): Use PRIi64 to print the index.
265 (aarch64_print_operand): Likewise.
267 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
269 * mcore-opc.h: Remove sentinal.
270 * mcore-dis.c (print_insn_mcore): Adjust.
272 2016-06-23 Graham Markall <graham.markall@embecosm.com>
274 * arc-opc.c: Correct description of availability of NPS400
277 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
279 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
280 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
281 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
282 xor3>: New mnemonics.
283 <setb>: Change to a VX form instruction.
284 (insert_sh6): Add support for rldixor.
285 (extract_sh6): Likewise.
287 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
289 * arc-ext.h: Wrap in extern C.
291 2016-06-21 Graham Markall <graham.markall@embecosm.com>
293 * arc-dis.c (arc_insn_length): Add comment on instruction length.
294 Use same method for determining instruction length on ARC700 and
296 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
297 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
298 with the NPS400 subclass.
299 * arc-opc.c: Likewise.
301 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
303 * sparc-opc.c (rdasr): New macro.
309 (sparc_opcodes): Use the macros above to fix and expand the
310 definition of read/write instructions from/to
311 asr/privileged/hyperprivileged instructions.
312 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
313 %hva_mask_nz. Prefer softint_set and softint_clear over
314 set_softint and clear_softint.
315 (print_insn_sparc): Support %ver in Rd.
317 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
319 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
320 architecture according to the hardware capabilities they require.
322 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
324 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
325 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
326 bfd_mach_sparc_v9{c,d,e,v,m}.
327 * sparc-opc.c (MASK_V9C): Define.
328 (MASK_V9D): Likewise.
329 (MASK_V9E): Likewise.
330 (MASK_V9V): Likewise.
331 (MASK_V9M): Likewise.
332 (v6): Add MASK_V9{C,D,E,V,M}.
333 (v6notlet): Likewise.
337 (v9andleon): Likewise.
345 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
347 2016-06-15 Nick Clifton <nickc@redhat.com>
349 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
350 constants to match expected behaviour.
351 (nds32_parse_opcode): Likewise. Also for whitespace.
353 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
355 * arc-opc.c (extract_rhv1): Extract value from insn.
357 2016-06-14 Graham Markall <graham.markall@embecosm.com>
359 * arc-nps400-tbl.h: Add ldbit instruction.
360 * arc-opc.c: Add flag classes required for ldbit.
362 2016-06-14 Graham Markall <graham.markall@embecosm.com>
364 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
365 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
366 support the above instructions.
368 2016-06-14 Graham Markall <graham.markall@embecosm.com>
370 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
371 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
372 csma, cbba, zncv, and hofs.
373 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
374 support the above instructions.
376 2016-06-06 Graham Markall <graham.markall@embecosm.com>
378 * arc-nps400-tbl.h: Add andab and orab instructions.
380 2016-06-06 Graham Markall <graham.markall@embecosm.com>
382 * arc-nps400-tbl.h: Add addl-like instructions.
384 2016-06-06 Graham Markall <graham.markall@embecosm.com>
386 * arc-nps400-tbl.h: Add mxb and imxb instructions.
388 2016-06-06 Graham Markall <graham.markall@embecosm.com>
390 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
393 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
395 * s390-dis.c (option_use_insn_len_bits_p): New file scope
397 (init_disasm): Handle new command line option "insnlength".
398 (print_s390_disassembler_options): Mention new option in help
400 (print_insn_s390): Use the encoded insn length when dumping
401 unknown instructions.
403 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
405 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
406 to the address and set as symbol address for LDS/ STS immediate operands.
408 2016-06-07 Alan Modra <amodra@gmail.com>
410 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
411 cpu for "vle" to e500.
412 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
413 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
414 (PPCNONE): Delete, substitute throughout.
415 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
416 except for major opcode 4 and 31.
417 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
419 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
421 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
422 ARM_EXT_RAS in relevant entries.
424 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
427 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
430 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
433 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
435 Add comments for '&'.
436 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
438 (intel_operand_size): Handle indir_v_mode.
439 (OP_E_register): Likewise.
440 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
441 64-bit indirect call/jmp for AMD64.
442 * i386-tbl.h: Regenerated
444 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
446 * arc-dis.c (struct arc_operand_iterator): New structure.
447 (find_format_from_table): All the old content from find_format,
448 with some minor adjustments, and parameter renaming.
449 (find_format_long_instructions): New function.
450 (find_format): Rewritten.
451 (arc_insn_length): Add LSB parameter.
452 (extract_operand_value): New function.
453 (operand_iterator_next): New function.
454 (print_insn_arc): Use new functions to find opcode, and iterator
456 * arc-opc.c (insert_nps_3bit_dst_short): New function.
457 (extract_nps_3bit_dst_short): New function.
458 (insert_nps_3bit_src2_short): New function.
459 (extract_nps_3bit_src2_short): New function.
460 (insert_nps_bitop1_size): New function.
461 (extract_nps_bitop1_size): New function.
462 (insert_nps_bitop2_size): New function.
463 (extract_nps_bitop2_size): New function.
464 (insert_nps_bitop_mod4_msb): New function.
465 (extract_nps_bitop_mod4_msb): New function.
466 (insert_nps_bitop_mod4_lsb): New function.
467 (extract_nps_bitop_mod4_lsb): New function.
468 (insert_nps_bitop_dst_pos3_pos4): New function.
469 (extract_nps_bitop_dst_pos3_pos4): New function.
470 (insert_nps_bitop_ins_ext): New function.
471 (extract_nps_bitop_ins_ext): New function.
472 (arc_operands): Add new operands.
473 (arc_long_opcodes): New global array.
474 (arc_num_long_opcodes): New global.
475 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
477 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
479 * nds32-asm.h: Add extern "C".
480 * sh-opc.h: Likewise.
482 2016-06-01 Graham Markall <graham.markall@embecosm.com>
484 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
485 0,b,limm to the rflt instruction.
487 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
489 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
492 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
495 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
496 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
497 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
498 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
499 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
500 * i386-init.h: Regenerated.
502 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
505 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
506 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
507 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
508 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
509 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
510 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
511 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
512 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
513 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
514 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
515 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
516 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
517 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
518 CpuRegMask for AVX512.
519 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
521 (set_bitfield_from_cpu_flag_init): New function.
522 (set_bitfield): Remove const on f. Call
523 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
524 * i386-opc.h (CpuRegMMX): New.
525 (CpuRegXMM): Likewise.
526 (CpuRegYMM): Likewise.
527 (CpuRegZMM): Likewise.
528 (CpuRegMask): Likewise.
529 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
531 * i386-init.h: Regenerated.
532 * i386-tbl.h: Likewise.
534 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
537 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
538 (opcode_modifiers): Add AMD64 and Intel64.
539 (main): Properly verify CpuMax.
540 * i386-opc.h (CpuAMD64): Removed.
541 (CpuIntel64): Likewise.
542 (CpuMax): Set to CpuNo64.
543 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
546 (i386_opcode_modifier): Add amd64 and intel64.
547 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
549 * i386-init.h: Regenerated.
550 * i386-tbl.h: Likewise.
552 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
555 * i386-gen.c (main): Fail if CpuMax is incorrect.
556 * i386-opc.h (CpuMax): Set to CpuIntel64.
557 * i386-tbl.h: Regenerated.
559 2016-05-27 Nick Clifton <nickc@redhat.com>
562 * msp430-dis.c (msp430dis_read_two_bytes): New function.
563 (msp430dis_opcode_unsigned): New function.
564 (msp430dis_opcode_signed): New function.
565 (msp430_singleoperand): Use the new opcode reading functions.
566 Only disassenmble bytes if they were successfully read.
567 (msp430_doubleoperand): Likewise.
568 (msp430_branchinstr): Likewise.
569 (msp430x_callx_instr): Likewise.
570 (print_insn_msp430): Check that it is safe to read bytes before
571 attempting disassembly. Use the new opcode reading functions.
573 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
575 * ppc-opc.c (CY): New define. Document it.
576 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
578 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
580 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
581 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
582 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
583 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
585 * i386-init.h: Regenerated.
587 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
590 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
591 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
592 * i386-init.h: Regenerated.
594 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
596 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
597 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
598 * i386-init.h: Regenerated.
600 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
602 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
604 (print_insn_arc): Set insn_type information.
605 * arc-opc.c (C_CC): Add F_CLASS_COND.
606 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
607 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
608 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
609 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
610 (brne, brne_s, jeq_s, jne_s): Likewise.
612 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
614 * arc-tbl.h (neg): New instruction variant.
616 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
618 * arc-dis.c (find_format, find_format, get_auxreg)
619 (print_insn_arc): Changed.
620 * arc-ext.h (INSERT_XOP): Likewise.
622 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
624 * tic54x-dis.c (sprint_mmr): Adjust.
625 * tic54x-opc.c: Likewise.
627 2016-05-19 Alan Modra <amodra@gmail.com>
629 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
631 2016-05-19 Alan Modra <amodra@gmail.com>
633 * ppc-opc.c: Formatting.
634 (NSISIGNOPT): Define.
635 (powerpc_opcodes <subis>): Use NSISIGNOPT.
637 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
639 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
640 replacing references to `micromips_ase' throughout.
641 (_print_insn_mips): Don't use file-level microMIPS annotation to
642 determine the disassembly mode with the symbol table.
644 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
646 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
648 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
650 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
652 * mips-opc.c (D34): New macro.
653 (mips_builtin_opcodes): Define bposge32c for DSPr3.
655 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
657 * i386-dis.c (prefix_table): Add RDPID instruction.
658 * i386-gen.c (cpu_flag_init): Add RDPID flag.
659 (cpu_flags): Add RDPID bitfield.
660 * i386-opc.h (enum): Add RDPID element.
661 (i386_cpu_flags): Add RDPID field.
662 * i386-opc.tbl: Add RDPID instruction.
663 * i386-init.h: Regenerate.
664 * i386-tbl.h: Regenerate.
666 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
668 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
669 branch type of a symbol.
670 (print_insn): Likewise.
672 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
674 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
675 Mainline Security Extensions instructions.
676 (thumb_opcodes): Add entries for narrow ARMv8-M Security
677 Extensions instructions.
678 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
680 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
683 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
685 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
687 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
689 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
690 (arcExtMap_genOpcode): Likewise.
691 * arc-opc.c (arg_32bit_rc): Define new variable.
692 (arg_32bit_u6): Likewise.
693 (arg_32bit_limm): Likewise.
695 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
697 * aarch64-gen.c (VERIFIER): Define.
698 * aarch64-opc.c (VERIFIER): Define.
699 (verify_ldpsw): Use static linkage.
700 * aarch64-opc.h (verify_ldpsw): Remove.
701 * aarch64-tbl.h: Use VERIFIER for verifiers.
703 2016-04-28 Nick Clifton <nickc@redhat.com>
706 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
707 * aarch64-opc.c (verify_ldpsw): New function.
708 * aarch64-opc.h (verify_ldpsw): New prototype.
709 * aarch64-tbl.h: Add initialiser for verifier field.
710 (LDPSW): Set verifier to verify_ldpsw.
712 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
716 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
717 smaller than address size.
719 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
721 * alpha-dis.c: Regenerate.
722 * crx-dis.c: Likewise.
723 * disassemble.c: Likewise.
724 * epiphany-opc.c: Likewise.
725 * fr30-opc.c: Likewise.
726 * frv-opc.c: Likewise.
727 * ip2k-opc.c: Likewise.
728 * iq2000-opc.c: Likewise.
729 * lm32-opc.c: Likewise.
730 * lm32-opinst.c: Likewise.
731 * m32c-opc.c: Likewise.
732 * m32r-opc.c: Likewise.
733 * m32r-opinst.c: Likewise.
734 * mep-opc.c: Likewise.
735 * mt-opc.c: Likewise.
736 * or1k-opc.c: Likewise.
737 * or1k-opinst.c: Likewise.
738 * tic80-opc.c: Likewise.
739 * xc16x-opc.c: Likewise.
740 * xstormy16-opc.c: Likewise.
742 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
744 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
745 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
746 calcsd, and calcxd instructions.
747 * arc-opc.c (insert_nps_bitop_size): Delete.
748 (extract_nps_bitop_size): Delete.
749 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
750 (extract_nps_qcmp_m3): Define.
751 (extract_nps_qcmp_m2): Define.
752 (extract_nps_qcmp_m1): Define.
753 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
754 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
755 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
756 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
757 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
760 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
762 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
764 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
766 * Makefile.in: Regenerated with automake 1.11.6.
767 * aclocal.m4: Likewise.
769 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
771 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
773 * arc-opc.c (insert_nps_cmem_uimm16): New function.
774 (extract_nps_cmem_uimm16): New function.
775 (arc_operands): Add NPS_XLDST_UIMM16 operand.
777 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
779 * arc-dis.c (arc_insn_length): New function.
780 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
781 (find_format): Change insnLen parameter to unsigned.
783 2016-04-13 Nick Clifton <nickc@redhat.com>
786 * v850-opc.c (v850_opcodes): Correct masks for long versions of
787 the LD.B and LD.BU instructions.
789 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
791 * arc-dis.c (find_format): Check for extension flags.
792 (print_flags): New function.
793 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
795 * arc-ext.c (arcExtMap_coreRegName): Use
796 LAST_EXTENSION_CORE_REGISTER.
797 (arcExtMap_coreReadWrite): Likewise.
798 (dump_ARC_extmap): Update printing.
799 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
800 (arc_aux_regs): Add cpu field.
801 * arc-regs.h: Add cpu field, lower case name aux registers.
803 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
805 * arc-tbl.h: Add rtsc, sleep with no arguments.
807 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
809 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
811 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
812 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
813 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
814 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
815 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
816 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
817 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
818 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
819 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
820 (arc_opcode arc_opcodes): Null terminate the array.
821 (arc_num_opcodes): Remove.
822 * arc-ext.h (INSERT_XOP): Define.
823 (extInstruction_t): Likewise.
824 (arcExtMap_instName): Delete.
825 (arcExtMap_insn): New function.
826 (arcExtMap_genOpcode): Likewise.
827 * arc-ext.c (ExtInstruction): Remove.
828 (create_map): Zero initialize instruction fields.
829 (arcExtMap_instName): Remove.
830 (arcExtMap_insn): New function.
831 (dump_ARC_extmap): More info while debuging.
832 (arcExtMap_genOpcode): New function.
833 * arc-dis.c (find_format): New function.
834 (print_insn_arc): Use find_format.
835 (arc_get_disassembler): Enable dump_ARC_extmap only when
838 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
840 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
841 instruction bits out.
843 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
845 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
846 * arc-opc.c (arc_flag_operands): Add new flags.
847 (arc_flag_classes): Add new classes.
849 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
851 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
853 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
855 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
856 encode1, rflt, crc16, and crc32 instructions.
857 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
858 (arc_flag_classes): Add C_NPS_R.
859 (insert_nps_bitop_size_2b): New function.
860 (extract_nps_bitop_size_2b): Likewise.
861 (insert_nps_bitop_uimm8): Likewise.
862 (extract_nps_bitop_uimm8): Likewise.
863 (arc_operands): Add new operand entries.
865 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
867 * arc-regs.h: Add a new subclass field. Add double assist
868 accumulator register values.
869 * arc-tbl.h: Use DPA subclass to mark the double assist
870 instructions. Use DPX/SPX subclas to mark the FPX instructions.
871 * arc-opc.c (RSP): Define instead of SP.
872 (arc_aux_regs): Add the subclass field.
874 2016-04-05 Jiong Wang <jiong.wang@arm.com>
876 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
878 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
880 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
883 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
885 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
886 issues. No functional changes.
888 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
890 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
891 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
892 (RTT): Remove duplicate.
893 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
894 (PCT_CONFIG*): Remove.
895 (D1L, D1H, D2H, D2L): Define.
897 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
899 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
901 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
903 * arc-tbl.h (invld07): Remove.
904 * arc-ext-tbl.h: New file.
905 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
906 * arc-opc.c (arc_opcodes): Add ext-tbl include.
908 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
910 Fix -Wstack-usage warnings.
911 * aarch64-dis.c (print_operands): Substitute size.
912 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
914 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
916 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
917 to get a proper diagnostic when an invalid ASR register is used.
919 2016-03-22 Nick Clifton <nickc@redhat.com>
921 * configure: Regenerate.
923 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
925 * arc-nps400-tbl.h: New file.
926 * arc-opc.c: Add top level comment.
927 (insert_nps_3bit_dst): New function.
928 (extract_nps_3bit_dst): New function.
929 (insert_nps_3bit_src2): New function.
930 (extract_nps_3bit_src2): New function.
931 (insert_nps_bitop_size): New function.
932 (extract_nps_bitop_size): New function.
933 (arc_flag_operands): Add nps400 entries.
934 (arc_flag_classes): Add nps400 entries.
935 (arc_operands): Add nps400 entries.
936 (arc_opcodes): Add nps400 include.
938 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
940 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
941 the new class enum values.
943 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
945 * arc-dis.c (print_insn_arc): Handle nps400.
947 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
949 * arc-opc.c (BASE): Delete.
951 2016-03-18 Nick Clifton <nickc@redhat.com>
954 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
955 of MOV insn that aliases an ORR insn.
957 2016-03-16 Jiong Wang <jiong.wang@arm.com>
959 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
961 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
963 * mcore-opc.h: Add const qualifiers.
964 * microblaze-opc.h (struct op_code_struct): Likewise.
965 * sh-opc.h: Likewise.
966 * tic4x-dis.c (tic4x_print_indirect): Likewise.
967 (tic4x_print_op): Likewise.
969 2016-03-02 Alan Modra <amodra@gmail.com>
971 * or1k-desc.h: Regenerate.
972 * fr30-ibld.c: Regenerate.
973 * rl78-decode.c: Regenerate.
975 2016-03-01 Nick Clifton <nickc@redhat.com>
978 * rl78-dis.c (print_insn_rl78_common): Fix typo.
980 2016-02-24 Renlin Li <renlin.li@arm.com>
982 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
983 (print_insn_coprocessor): Support fp16 instructions.
985 2016-02-24 Renlin Li <renlin.li@arm.com>
987 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
990 2016-02-24 Renlin Li <renlin.li@arm.com>
992 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
993 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
995 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
997 * i386-dis.c (print_insn): Parenthesize expression to prevent
1001 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1002 Janek van Oirschot <jvanoirs@synopsys.com>
1004 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1007 2016-02-04 Nick Clifton <nickc@redhat.com>
1010 * msp430-dis.c (print_insn_msp430): Add a special case for
1011 decoding an RRC instruction with the ZC bit set in the extension
1014 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1016 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1017 * epiphany-ibld.c: Regenerate.
1018 * fr30-ibld.c: Regenerate.
1019 * frv-ibld.c: Regenerate.
1020 * ip2k-ibld.c: Regenerate.
1021 * iq2000-ibld.c: Regenerate.
1022 * lm32-ibld.c: Regenerate.
1023 * m32c-ibld.c: Regenerate.
1024 * m32r-ibld.c: Regenerate.
1025 * mep-ibld.c: Regenerate.
1026 * mt-ibld.c: Regenerate.
1027 * or1k-ibld.c: Regenerate.
1028 * xc16x-ibld.c: Regenerate.
1029 * xstormy16-ibld.c: Regenerate.
1031 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1033 * epiphany-dis.c: Regenerated from latest cpu files.
1035 2016-02-01 Michael McConville <mmcco@mykolab.com>
1037 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1040 2016-01-25 Renlin Li <renlin.li@arm.com>
1042 * arm-dis.c (mapping_symbol_for_insn): New function.
1043 (find_ifthen_state): Call mapping_symbol_for_insn().
1045 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1047 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1048 of MSR UAO immediate operand.
1050 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1052 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1053 instruction support.
1055 2016-01-17 Alan Modra <amodra@gmail.com>
1057 * configure: Regenerate.
1059 2016-01-14 Nick Clifton <nickc@redhat.com>
1061 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1062 instructions that can support stack pointer operations.
1063 * rl78-decode.c: Regenerate.
1064 * rl78-dis.c: Fix display of stack pointer in MOVW based
1067 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1069 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1070 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1071 erxtatus_el1 and erxaddr_el1.
1073 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1075 * arm-dis.c (arm_opcodes): Add "esb".
1076 (thumb_opcodes): Likewise.
1078 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1080 * ppc-opc.c <xscmpnedp>: Delete.
1081 <xvcmpnedp>: Likewise.
1082 <xvcmpnedp.>: Likewise.
1083 <xvcmpnesp>: Likewise.
1084 <xvcmpnesp.>: Likewise.
1086 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1089 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1092 2016-01-01 Alan Modra <amodra@gmail.com>
1094 Update year range in copyright notice of all files.
1096 For older changes see ChangeLog-2015
1098 Copyright (C) 2016 Free Software Foundation, Inc.
1100 Copying and distribution of this file, with or without modification,
1101 are permitted in any medium without royalty provided the copyright
1102 notice and this notice are preserved.
1108 version-control: never