1 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
3 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
4 sve_shift_tsz_bhsd iclass encode.
5 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
6 sve_shift_tsz_bhsd iclass decode.
8 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
10 * aarch64-asm-2.c: Regenerated.
11 * aarch64-dis-2.c: Regenerated.
12 * aarch64-opc-2.c: Regenerated.
13 * aarch64-asm.c (aarch64_ins_sve_shrimm):
14 (aarch64_encode_variant_using_iclass): Handle
15 sve_shift_tsz_hsd iclass encode.
16 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
17 sve_shift_tsz_hsd iclass decode.
18 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
19 for SVE_SHRIMM_UNPRED_22.
20 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
21 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
24 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
26 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
27 sve_size_013 iclass encode.
28 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
29 sve_size_013 iclass decode.
31 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
33 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
34 sve_size_bh iclass encode.
35 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
36 sve_size_bh iclass decode.
38 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
40 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
41 sve_size_sd2 iclass encode.
42 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
43 sve_size_sd2 iclass decode.
44 * aarch64-opc.c (fields): Handle SVE_sz2 field.
45 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
47 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
49 * aarch64-asm-2.c: Regenerated.
50 * aarch64-dis-2.c: Regenerated.
51 * aarch64-opc-2.c: Regenerated.
52 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
54 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
55 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
57 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
59 * aarch64-asm-2.c: Regenerated.
60 * aarch64-dis-2.c: Regenerated.
61 * aarch64-opc-2.c: Regenerated.
62 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
64 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
65 (fields): Handle SVE_i3l and SVE_i3h2 fields.
66 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
68 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
70 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
72 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
73 sve_size_hsd2 iclass encode.
74 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
75 sve_size_hsd2 iclass decode.
76 * aarch64-opc.c (fields): Handle SVE_size field.
77 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
79 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
81 * aarch64-asm-2.c: Regenerated.
82 * aarch64-dis-2.c: Regenerated.
83 * aarch64-opc-2.c: Regenerated.
84 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
86 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
87 (fields): Handle SVE_rot3 field.
88 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
89 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
91 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
93 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
96 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
99 (aarch64_feature_sve2, aarch64_feature_sve2aes,
100 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
101 aarch64_feature_sve2bitperm): New feature sets.
102 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
103 for feature set addresses.
104 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
105 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
107 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
108 Faraz Shahbazker <fshahbazker@wavecomp.com>
110 * mips-dis.c (mips_calculate_combination_ases): Add ISA
111 argument and set ASE_EVA_R6 appropriately.
112 (set_default_mips_dis_options): Pass ISA to above.
113 (parse_mips_dis_option): Likewise.
114 * mips-opc.c (EVAR6): New macro.
115 (mips_builtin_opcodes): Add llwpe, scwpe.
117 2019-05-01 Sudakshina Das <sudi.das@arm.com>
119 * aarch64-asm-2.c: Regenerated.
120 * aarch64-dis-2.c: Regenerated.
121 * aarch64-opc-2.c: Regenerated.
122 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
123 AARCH64_OPND_TME_UIMM16.
124 (aarch64_print_operand): Likewise.
125 * aarch64-tbl.h (QL_IMM_NIL): New.
128 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
130 2019-04-29 John Darrington <john@darrington.wattle.id.au>
132 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
134 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
135 Faraz Shahbazker <fshahbazker@wavecomp.com>
137 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
139 2019-04-24 John Darrington <john@darrington.wattle.id.au>
141 * s12z-opc.h: Add extern "C" bracketing to help
142 users who wish to use this interface in c++ code.
144 2019-04-24 John Darrington <john@darrington.wattle.id.au>
146 * s12z-opc.c (bm_decode): Handle bit map operations with the
149 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
151 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
152 specifier. Add entries for VLDR and VSTR of system registers.
153 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
154 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
155 of %J and %K format specifier.
157 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
159 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
160 Add new entries for VSCCLRM instruction.
161 (print_insn_coprocessor): Handle new %C format control code.
163 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
165 * arm-dis.c (enum isa): New enum.
166 (struct sopcode32): New structure.
167 (coprocessor_opcodes): change type of entries to struct sopcode32 and
168 set isa field of all current entries to ANY.
169 (print_insn_coprocessor): Change type of insn to struct sopcode32.
170 Only match an entry if its isa field allows the current mode.
172 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
174 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
176 (print_insn_thumb32): Add logic to print %n CLRM register list.
178 2019-04-15 Sudakshina Das <sudi.das@arm.com>
180 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
183 2019-04-15 Sudakshina Das <sudi.das@arm.com>
185 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
186 (print_insn_thumb32): Edit the switch case for %Z.
188 2019-04-15 Sudakshina Das <sudi.das@arm.com>
190 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
192 2019-04-15 Sudakshina Das <sudi.das@arm.com>
194 * arm-dis.c (thumb32_opcodes): New instruction bfl.
196 2019-04-15 Sudakshina Das <sudi.das@arm.com>
198 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
200 2019-04-15 Sudakshina Das <sudi.das@arm.com>
202 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
203 Arm register with r13 and r15 unpredictable.
204 (thumb32_opcodes): New instructions for bfx and bflx.
206 2019-04-15 Sudakshina Das <sudi.das@arm.com>
208 * arm-dis.c (thumb32_opcodes): New instructions for bf.
210 2019-04-15 Sudakshina Das <sudi.das@arm.com>
212 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
214 2019-04-15 Sudakshina Das <sudi.das@arm.com>
216 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
218 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
220 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
222 2019-04-12 John Darrington <john@darrington.wattle.id.au>
224 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
225 "optr". ("operator" is a reserved word in c++).
227 2019-04-11 Sudakshina Das <sudi.das@arm.com>
229 * aarch64-opc.c (aarch64_print_operand): Add case for
231 (verify_constraints): Likewise.
232 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
233 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
234 to accept Rt|SP as first operand.
235 (AARCH64_OPERANDS): Add new Rt_SP.
236 * aarch64-asm-2.c: Regenerated.
237 * aarch64-dis-2.c: Regenerated.
238 * aarch64-opc-2.c: Regenerated.
240 2019-04-11 Sudakshina Das <sudi.das@arm.com>
242 * aarch64-asm-2.c: Regenerated.
243 * aarch64-dis-2.c: Likewise.
244 * aarch64-opc-2.c: Likewise.
245 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
247 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
249 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
251 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
253 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
254 * i386-init.h: Regenerated.
256 2019-04-07 Alan Modra <amodra@gmail.com>
258 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
259 op_separator to control printing of spaces, comma and parens
260 rather than need_comma, need_paren and spaces vars.
262 2019-04-07 Alan Modra <amodra@gmail.com>
265 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
266 (print_insn_neon, print_insn_arm): Likewise.
268 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
270 * i386-dis-evex.h (evex_table): Updated to support BF16
272 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
273 and EVEX_W_0F3872_P_3.
274 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
275 (cpu_flags): Add bitfield for CpuAVX512_BF16.
276 * i386-opc.h (enum): Add CpuAVX512_BF16.
277 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
278 * i386-opc.tbl: Add AVX512 BF16 instructions.
279 * i386-init.h: Regenerated.
280 * i386-tbl.h: Likewise.
282 2019-04-05 Alan Modra <amodra@gmail.com>
284 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
285 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
286 to favour printing of "-" branch hint when using the "y" bit.
287 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
289 2019-04-05 Alan Modra <amodra@gmail.com>
291 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
292 opcode until first operand is output.
294 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
297 * ppc-opc.c (valid_bo_pre_v2): Add comments.
298 (valid_bo_post_v2): Add support for 'at' branch hints.
299 (insert_bo): Only error on branch on ctr.
300 (get_bo_hint_mask): New function.
301 (insert_boe): Add new 'branch_taken' formal argument. Add support
302 for inserting 'at' branch hints.
303 (extract_boe): Add new 'branch_taken' formal argument. Add support
304 for extracting 'at' branch hints.
305 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
306 (BOE): Delete operand.
307 (BOM, BOP): New operands.
309 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
310 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
311 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
312 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
313 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
314 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
315 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
316 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
317 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
318 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
319 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
320 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
321 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
322 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
323 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
324 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
325 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
326 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
327 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
328 bttarl+>: New extended mnemonics.
330 2019-03-28 Alan Modra <amodra@gmail.com>
333 * ppc-opc.c (BTF): Define.
334 (powerpc_opcodes): Use for mtfsb*.
335 * ppc-dis.c (print_insn_powerpc): Print fields with both
336 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
338 2019-03-25 Tamar Christina <tamar.christina@arm.com>
340 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
341 (mapping_symbol_for_insn): Implement new algorithm.
342 (print_insn): Remove duplicate code.
344 2019-03-25 Tamar Christina <tamar.christina@arm.com>
346 * aarch64-dis.c (print_insn_aarch64):
349 2019-03-25 Tamar Christina <tamar.christina@arm.com>
351 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
354 2019-03-25 Tamar Christina <tamar.christina@arm.com>
356 * aarch64-dis.c (last_stop_offset): New.
357 (print_insn_aarch64): Use stop_offset.
359 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
362 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
364 * i386-init.h: Regenerated.
366 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
369 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
370 vmovdqu16, vmovdqu32 and vmovdqu64.
371 * i386-tbl.h: Regenerated.
373 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
375 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
376 from vstrszb, vstrszh, and vstrszf.
378 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
380 * s390-opc.txt: Add instruction descriptions.
382 2019-02-08 Jim Wilson <jimw@sifive.com>
384 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
387 2019-02-07 Tamar Christina <tamar.christina@arm.com>
389 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
391 2019-02-07 Tamar Christina <tamar.christina@arm.com>
394 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
395 * aarch64-opc.c (verify_elem_sd): New.
396 (fields): Add FLD_sz entr.
397 * aarch64-tbl.h (_SIMD_INSN): New.
398 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
399 fmulx scalar and vector by element isns.
401 2019-02-07 Nick Clifton <nickc@redhat.com>
403 * po/sv.po: Updated Swedish translation.
405 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
407 * s390-mkopc.c (main): Accept arch13 as cpu string.
408 * s390-opc.c: Add new instruction formats and instruction opcode
410 * s390-opc.txt: Add new arch13 instructions.
412 2019-01-25 Sudakshina Das <sudi.das@arm.com>
414 * aarch64-tbl.h (QL_LDST_AT): Update macro.
415 (aarch64_opcode): Change encoding for stg, stzg
417 * aarch64-asm-2.c: Regenerated.
418 * aarch64-dis-2.c: Regenerated.
419 * aarch64-opc-2.c: Regenerated.
421 2019-01-25 Sudakshina Das <sudi.das@arm.com>
423 * aarch64-asm-2.c: Regenerated.
424 * aarch64-dis-2.c: Likewise.
425 * aarch64-opc-2.c: Likewise.
426 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
428 2019-01-25 Sudakshina Das <sudi.das@arm.com>
429 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
431 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
432 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
433 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
434 * aarch64-dis.h (ext_addr_simple_2): Likewise.
435 * aarch64-opc.c (operand_general_constraint_met_p): Remove
436 case for ldstgv_indexed.
437 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
438 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
439 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
440 * aarch64-asm-2.c: Regenerated.
441 * aarch64-dis-2.c: Regenerated.
442 * aarch64-opc-2.c: Regenerated.
444 2019-01-23 Nick Clifton <nickc@redhat.com>
446 * po/pt_BR.po: Updated Brazilian Portuguese translation.
448 2019-01-21 Nick Clifton <nickc@redhat.com>
450 * po/de.po: Updated German translation.
451 * po/uk.po: Updated Ukranian translation.
453 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
454 * mips-dis.c (mips_arch_choices): Fix typo in
455 gs464, gs464e and gs264e descriptors.
457 2019-01-19 Nick Clifton <nickc@redhat.com>
459 * configure: Regenerate.
460 * po/opcodes.pot: Regenerate.
462 2018-06-24 Nick Clifton <nickc@redhat.com>
466 2019-01-09 John Darrington <john@darrington.wattle.id.au>
468 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
470 -dis.c (opr_emit_disassembly): Do not omit an index if it is
473 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
475 * configure: Regenerate.
477 2019-01-07 Alan Modra <amodra@gmail.com>
479 * configure: Regenerate.
480 * po/POTFILES.in: Regenerate.
482 2019-01-03 John Darrington <john@darrington.wattle.id.au>
484 * s12z-opc.c: New file.
485 * s12z-opc.h: New file.
486 * s12z-dis.c: Removed all code not directly related to display
487 of instructions. Used the interface provided by the new files
489 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
490 * Makefile.in: Regenerate.
491 * configure.ac (bfd_s12z_arch): Correct the dependencies.
492 * configure: Regenerate.
494 2019-01-01 Alan Modra <amodra@gmail.com>
496 Update year range in copyright notice of all files.
498 For older changes see ChangeLog-2018
500 Copyright (C) 2019 Free Software Foundation, Inc.
502 Copying and distribution of this file, with or without modification,
503 are permitted in any medium without royalty provided the copyright
504 notice and this notice are preserved.
510 version-control: never