1 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
2 Andrew Bennett <andrew.bennett@imgtec.com>
4 * mips-dis.c (mips_calculate_combination_ases): Handle the
6 (parse_mips_ase_option): New function.
7 (parse_mips_dis_option): Factor out ASE option handling to the
8 new function. Call `mips_calculate_combination_ases'.
9 * mips-opc.c (XPAVZ): New macro.
10 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
11 "mfhgc0", "mthc0" and "mthgc0".
13 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
15 * mips-dis.c (mips_calculate_combination_ases): New function.
16 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
17 calculation to the new function.
18 (set_default_mips_dis_options): Call the new function.
20 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
22 * arc-dis.c (parse_disassembler_options): Use
23 FOR_EACH_DISASSEMBLER_OPTION.
25 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
27 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
28 disassembler option strings.
29 (parse_cpu_option): Likewise.
31 2017-06-28 Tamar Christina <tamar.christina@arm.com>
33 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
34 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
35 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
36 (aarch64_feature_dotprod, DOT_INSN): New.
38 * aarch64-dis-2.c: Regenerated.
40 2017-06-28 Jiong Wang <jiong.wang@arm.com>
42 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
44 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
45 Matthew Fortune <matthew.fortune@imgtec.com>
46 Andrew Bennett <andrew.bennett@imgtec.com>
48 * mips-formats.h (INT_BIAS): New macro.
49 (INT_ADJ): Redefine in INT_BIAS terms.
50 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
51 (mips_print_save_restore): New function.
52 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
53 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
55 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
56 (print_mips16_insn_arg): Call `mips_print_save_restore' for
57 OP_SAVE_RESTORE_LIST handling, factored out from here.
58 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
59 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
60 (mips_builtin_opcodes): Add "restore" and "save" entries.
61 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
63 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
65 2017-06-23 Andrew Waterman <andrew@sifive.com>
67 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
68 alias; do not mark SLTI instruction as an alias.
70 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
72 * i386-dis.c (RM_0FAE_REG_5): Removed.
73 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
74 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
75 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
76 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
77 PREFIX_MOD_3_0F01_REG_5_RM_0.
78 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
79 PREFIX_MOD_3_0FAE_REG_5.
80 (mod_table): Update MOD_0FAE_REG_5.
81 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
82 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
83 * i386-tbl.h: Regenerated.
85 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
87 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
88 * i386-opc.tbl: Likewise.
89 * i386-tbl.h: Regenerated.
91 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
93 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
95 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
98 2017-06-19 Nick Clifton <nickc@redhat.com>
101 * score-dis.c (score_opcodes): Add sentinel.
103 2017-06-16 Alan Modra <amodra@gmail.com>
105 * rx-decode.c: Regenerate.
107 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
110 * i386-dis.c (OP_E_register): Check valid bnd register.
113 2017-06-15 Nick Clifton <nickc@redhat.com>
116 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
119 2017-06-15 Nick Clifton <nickc@redhat.com>
122 * rl78-decode.opc (OP_BUF_LEN): Define.
123 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
124 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
126 * rl78-decode.c: Regenerate.
128 2017-06-15 Nick Clifton <nickc@redhat.com>
131 * bfin-dis.c (gregs): Clip index to prevent overflow.
136 2017-06-14 Nick Clifton <nickc@redhat.com>
139 * score7-dis.c (score_opcodes): Add sentinel.
141 2017-06-14 Yao Qi <yao.qi@linaro.org>
143 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
144 * arm-dis.c: Likewise.
145 * ia64-dis.c: Likewise.
146 * mips-dis.c: Likewise.
147 * spu-dis.c: Likewise.
148 * disassemble.h (print_insn_aarch64): New declaration, moved from
150 (print_insn_big_arm, print_insn_big_mips): Likewise.
151 (print_insn_i386, print_insn_ia64): Likewise.
152 (print_insn_little_arm, print_insn_little_mips): Likewise.
154 2017-06-14 Nick Clifton <nickc@redhat.com>
157 * rx-decode.opc: Include libiberty.h
158 (GET_SCALE): New macro - validates access to SCALE array.
159 (GET_PSCALE): New macro - validates access to PSCALE array.
160 (DIs, SIs, S2Is, rx_disp): Use new macros.
161 * rx-decode.c: Regenerate.
163 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
165 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
167 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
169 * arc-dis.c (enforced_isa_mask): Declare.
170 (cpu_types): Likewise.
171 (parse_cpu_option): New function.
172 (parse_disassembler_options): Use it.
173 (print_insn_arc): Use enforced_isa_mask.
174 (print_arc_disassembler_options): Document new options.
176 2017-05-24 Yao Qi <yao.qi@linaro.org>
178 * alpha-dis.c: Include disassemble.h, don't include
180 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
181 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
182 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
183 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
184 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
185 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
186 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
187 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
188 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
189 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
190 * moxie-dis.c, msp430-dis.c, mt-dis.c:
191 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
192 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
193 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
194 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
195 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
196 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
197 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
198 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
199 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
200 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
201 * z80-dis.c, z8k-dis.c: Likewise.
202 * disassemble.h: New file.
204 2017-05-24 Yao Qi <yao.qi@linaro.org>
206 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
207 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
209 2017-05-24 Yao Qi <yao.qi@linaro.org>
211 * disassemble.c (disassembler): Add arguments a, big and mach.
214 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
216 * i386-dis.c (NOTRACK_Fixup): New.
218 (NOTRACK_PREFIX): Likewise.
219 (last_active_prefix): Likewise.
220 (reg_table): Use NOTRACK on indirect call and jmp.
221 (ckprefix): Set last_active_prefix.
222 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
223 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
224 * i386-opc.h (NoTrackPrefixOk): New.
225 (i386_opcode_modifier): Add notrackprefixok.
226 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
228 * i386-tbl.h: Regenerated.
230 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
232 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
234 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
236 (print_insn_sparc): Handle new operand types.
237 * sparc-opc.c (MASK_M8): Define.
239 (v6notlet): Likewise.
250 (v9andleon): Likewise.
253 (HWS2_VM8): Likewise.
254 (sparc_opcode_archs): Add entry for "m8".
255 (sparc_opcodes): Add OSA2017 and M8 instructions
256 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
258 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
259 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
260 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
261 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
262 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
263 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
264 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
265 ASI_CORE_SELECT_COMMIT_NHT.
267 2017-05-18 Alan Modra <amodra@gmail.com>
269 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
270 * aarch64-dis.c: Likewise.
271 * aarch64-gen.c: Likewise.
272 * aarch64-opc.c: Likewise.
274 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
275 Matthew Fortune <matthew.fortune@imgtec.com>
277 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
278 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
279 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
280 (print_insn_arg) <OP_REG28>: Add handler.
281 (validate_insn_args) <OP_REG28>: Handle.
282 (print_mips16_insn_arg): Handle MIPS16 instructions that require
283 32-bit encoding and 9-bit immediates.
284 (print_insn_mips16): Handle MIPS16 instructions that require
285 32-bit encoding and MFC0/MTC0 operand decoding.
286 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
287 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
288 (RD_C0, WR_C0, E2, E2MT): New macros.
289 (mips16_opcodes): Add entries for MIPS16e2 instructions:
290 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
291 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
292 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
293 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
294 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
295 instructions, "swl", "swr", "sync" and its "sync_acquire",
296 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
297 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
298 regular/extended entries for original MIPS16 ISA revision
299 instructions whose extended forms are subdecoded in the MIPS16e2
300 ISA revision: "li", "sll" and "srl".
302 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
304 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
305 reference in CP0 move operand decoding.
307 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
309 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
311 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
313 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
315 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
316 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
317 "sync_rmb" and "sync_wmb" as aliases.
318 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
319 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
321 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
323 * arc-dis.c (parse_option): Update quarkse_em option..
324 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
326 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
328 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
330 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
332 2017-05-01 Michael Clark <michaeljclark@mac.com>
334 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
337 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
339 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
340 and branches and not synthetic data instructions.
342 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
344 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
346 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
348 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
349 * arc-opc.c (insert_r13el): New function.
351 * arc-tbl.h: Add new enter/leave variants.
353 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
355 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
357 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
359 * mips-dis.c (print_mips_disassembler_options): Add
362 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
364 * mips16-opc.c (AL): New macro.
365 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
366 of "ld" and "lw" as aliases.
368 2017-04-24 Tamar Christina <tamar.christina@arm.com>
370 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
373 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
374 Alan Modra <amodra@gmail.com>
376 * ppc-opc.c (ELEV): Define.
377 (vle_opcodes): Add se_rfgi and e_sc.
378 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
381 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
383 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
385 2017-04-21 Nick Clifton <nickc@redhat.com>
388 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
391 2017-04-13 Alan Modra <amodra@gmail.com>
393 * epiphany-desc.c: Regenerate.
394 * fr30-desc.c: Regenerate.
395 * frv-desc.c: Regenerate.
396 * ip2k-desc.c: Regenerate.
397 * iq2000-desc.c: Regenerate.
398 * lm32-desc.c: Regenerate.
399 * m32c-desc.c: Regenerate.
400 * m32r-desc.c: Regenerate.
401 * mep-desc.c: Regenerate.
402 * mt-desc.c: Regenerate.
403 * or1k-desc.c: Regenerate.
404 * xc16x-desc.c: Regenerate.
405 * xstormy16-desc.c: Regenerate.
407 2017-04-11 Alan Modra <amodra@gmail.com>
409 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
410 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
411 PPC_OPCODE_TMR for e6500.
412 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
413 (PPCVEC3): Define as PPC_OPCODE_POWER9.
414 (PPCVSX2): Define as PPC_OPCODE_POWER8.
415 (PPCVSX3): Define as PPC_OPCODE_POWER9.
416 (PPCHTM): Define as PPC_OPCODE_POWER8.
417 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
419 2017-04-10 Alan Modra <amodra@gmail.com>
421 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
422 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
423 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
424 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
426 2017-04-09 Pip Cet <pipcet@gmail.com>
428 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
429 appropriate floating-point precision directly.
431 2017-04-07 Alan Modra <amodra@gmail.com>
433 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
434 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
435 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
436 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
437 vector instructions with E6500 not PPCVEC2.
439 2017-04-06 Pip Cet <pipcet@gmail.com>
441 * Makefile.am: Add wasm32-dis.c.
442 * configure.ac: Add wasm32-dis.c to wasm32 target.
443 * disassemble.c: Add wasm32 disassembler code.
444 * wasm32-dis.c: New file.
445 * Makefile.in: Regenerate.
446 * configure: Regenerate.
447 * po/POTFILES.in: Regenerate.
448 * po/opcodes.pot: Regenerate.
450 2017-04-05 Pedro Alves <palves@redhat.com>
452 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
453 * arm-dis.c (parse_arm_disassembler_options): Constify.
454 * ppc-dis.c (powerpc_init_dialect): Constify local.
455 * vax-dis.c (parse_disassembler_options): Constify.
457 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
459 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
462 2017-03-30 Pip Cet <pipcet@gmail.com>
464 * configure.ac: Add (empty) bfd_wasm32_arch target.
465 * configure: Regenerate
466 * po/opcodes.pot: Regenerate.
468 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
470 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
472 * opcodes/sparc-opc.c (asi_table): New ASIs.
474 2017-03-29 Alan Modra <amodra@gmail.com>
476 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
478 (lookup_powerpc): Don't special case -1 dialect. Handle
480 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
481 lookup_powerpc call, pass it on second.
483 2017-03-27 Alan Modra <amodra@gmail.com>
486 * ppc-dis.c (struct ppc_mopt): Comment.
487 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
489 2017-03-27 Rinat Zelig <rinat@mellanox.com>
491 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
492 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
493 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
494 (insert_nps_misc_imm_offset): New function.
495 (extract_nps_misc imm_offset): New function.
496 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
497 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
499 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
501 * s390-mkopc.c (main): Remove vx2 check.
502 * s390-opc.txt: Remove vx2 instruction flags.
504 2017-03-21 Rinat Zelig <rinat@mellanox.com>
506 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
507 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
508 (insert_nps_imm_offset): New function.
509 (extract_nps_imm_offset): New function.
510 (insert_nps_imm_entry): New function.
511 (extract_nps_imm_entry): New function.
513 2017-03-17 Alan Modra <amodra@gmail.com>
516 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
517 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
518 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
520 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
522 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
526 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
528 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
530 2017-03-13 Andrew Waterman <andrew@sifive.com>
532 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
537 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
539 * i386-gen.c (opcode_modifiers): Replace S with Load.
540 * i386-opc.h (S): Removed.
542 (i386_opcode_modifier): Replace s with load.
543 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
544 and {evex}. Replace S with Load.
545 * i386-tbl.h: Regenerated.
547 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
549 * i386-opc.tbl: Use CpuCET on rdsspq.
550 * i386-tbl.h: Regenerated.
552 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
554 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
555 <vsx>: Do not use PPC_OPCODE_VSX3;
557 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
559 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
561 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
563 * i386-dis.c (REG_0F1E_MOD_3): New enum.
564 (MOD_0F1E_PREFIX_1): Likewise.
565 (MOD_0F38F5_PREFIX_2): Likewise.
566 (MOD_0F38F6_PREFIX_0): Likewise.
567 (RM_0F1E_MOD_3_REG_7): Likewise.
568 (PREFIX_MOD_0_0F01_REG_5): Likewise.
569 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
570 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
571 (PREFIX_0F1E): Likewise.
572 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
573 (PREFIX_0F38F5): Likewise.
574 (dis386_twobyte): Use PREFIX_0F1E.
575 (reg_table): Add REG_0F1E_MOD_3.
576 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
577 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
578 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
579 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
580 (three_byte_table): Use PREFIX_0F38F5.
581 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
582 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
583 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
584 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
585 PREFIX_MOD_3_0F01_REG_5_RM_2.
586 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
587 (cpu_flags): Add CpuCET.
588 * i386-opc.h (CpuCET): New enum.
589 (CpuUnused): Commented out.
590 (i386_cpu_flags): Add cpucet.
591 * i386-opc.tbl: Add Intel CET instructions.
592 * i386-init.h: Regenerated.
593 * i386-tbl.h: Likewise.
595 2017-03-06 Alan Modra <amodra@gmail.com>
598 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
599 (extract_raq, extract_ras, extract_rbx): New functions.
600 (powerpc_operands): Use opposite corresponding insert function.
602 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
603 register restriction.
605 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
607 * disassemble.c Include "safe-ctype.h".
608 (disassemble_init_for_target): Handle s390 init.
609 (remove_whitespace_and_extra_commas): New function.
610 (disassembler_options_cmp): Likewise.
611 * arm-dis.c: Include "libiberty.h".
613 (regnames): Use long disassembler style names.
614 Add force-thumb and no-force-thumb options.
615 (NUM_ARM_REGNAMES): Rename from this...
616 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
617 (get_arm_regname_num_options): Delete.
618 (set_arm_regname_option): Likewise.
619 (get_arm_regnames): Likewise.
620 (parse_disassembler_options): Likewise.
621 (parse_arm_disassembler_option): Rename from this...
622 (parse_arm_disassembler_options): ...to this. Make static.
623 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
624 (print_insn): Use parse_arm_disassembler_options.
625 (disassembler_options_arm): New function.
626 (print_arm_disassembler_options): Handle updated regnames.
627 * ppc-dis.c: Include "libiberty.h".
628 (ppc_opts): Add "32" and "64" entries.
629 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
630 (powerpc_init_dialect): Add break to switch statement.
631 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
632 (disassembler_options_powerpc): New function.
633 (print_ppc_disassembler_options): Use ARRAY_SIZE.
634 Remove printing of "32" and "64".
635 * s390-dis.c: Include "libiberty.h".
636 (init_flag): Remove unneeded variable.
637 (struct s390_options_t): New structure type.
638 (options): New structure.
639 (init_disasm): Rename from this...
640 (disassemble_init_s390): ...to this. Add initializations for
641 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
642 (print_insn_s390): Delete call to init_disasm.
643 (disassembler_options_s390): New function.
644 (print_s390_disassembler_options): Print using information from
646 * po/opcodes.pot: Regenerate.
648 2017-02-28 Jan Beulich <jbeulich@suse.com>
650 * i386-dis.c (PCMPESTR_Fixup): New.
651 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
652 (prefix_table): Use PCMPESTR_Fixup.
653 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
655 (vex_w_table): Delete VPCMPESTR{I,M} entries.
656 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
657 Split 64-bit and non-64-bit variants.
658 * opcodes/i386-tbl.h: Re-generate.
660 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
662 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
663 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
664 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
665 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
666 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
667 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
668 (OP_SVE_V_HSD): New macros.
669 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
670 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
671 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
672 (aarch64_opcode_table): Add new SVE instructions.
673 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
674 for rotation operands. Add new SVE operands.
675 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
676 (ins_sve_quad_index): Likewise.
677 (ins_imm_rotate): Split into...
678 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
679 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
680 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
682 (aarch64_ins_sve_addr_ri_s4): New function.
683 (aarch64_ins_sve_quad_index): Likewise.
684 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
685 * aarch64-asm-2.c: Regenerate.
686 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
687 (ext_sve_quad_index): Likewise.
688 (ext_imm_rotate): Split into...
689 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
690 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
691 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
693 (aarch64_ext_sve_addr_ri_s4): New function.
694 (aarch64_ext_sve_quad_index): Likewise.
695 (aarch64_ext_sve_index): Allow quad indices.
696 (do_misc_decoding): Likewise.
697 * aarch64-dis-2.c: Regenerate.
698 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
700 (OPD_F_OD_MASK): Widen by one bit.
701 (OPD_F_NO_ZR): Bump accordingly.
702 (get_operand_field_width): New function.
703 * aarch64-opc.c (fields): Add new SVE fields.
704 (operand_general_constraint_met_p): Handle new SVE operands.
705 (aarch64_print_operand): Likewise.
706 * aarch64-opc-2.c: Regenerate.
708 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
710 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
711 (aarch64_feature_compnum): ...this.
712 (SIMD_V8_3): Replace with...
714 (CNUM_INSN): New macro.
715 (aarch64_opcode_table): Use it for the complex number instructions.
717 2017-02-24 Jan Beulich <jbeulich@suse.com>
719 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
721 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
723 Add support for associating SPARC ASIs with an architecture level.
724 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
725 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
726 decoding of SPARC ASIs.
728 2017-02-23 Jan Beulich <jbeulich@suse.com>
730 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
731 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
733 2017-02-21 Jan Beulich <jbeulich@suse.com>
735 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
736 1 (instead of to itself). Correct typo.
738 2017-02-14 Andrew Waterman <andrew@sifive.com>
740 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
743 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
745 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
746 (aarch64_sys_reg_supported_p): Handle them.
748 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
750 * arc-opc.c (UIMM6_20R): Define.
751 (SIMM12_20): Use above.
752 (SIMM12_20R): Define.
753 (SIMM3_5_S): Use above.
754 (UIMM7_A32_11R_S): Define.
755 (UIMM7_9_S): Use above.
756 (UIMM3_13R_S): Define.
757 (SIMM11_A32_7_S): Use above.
759 (UIMM10_A32_8_S): Use above.
760 (UIMM8_8R_S): Define.
762 (arc_relax_opcodes): Use all above defines.
764 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
766 * arc-regs.h: Distinguish some of the registers different on
767 ARC700 and HS38 cpus.
769 2017-02-14 Alan Modra <amodra@gmail.com>
772 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
773 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
775 2017-02-11 Stafford Horne <shorne@gmail.com>
776 Alan Modra <amodra@gmail.com>
778 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
779 Use insn_bytes_value and insn_int_value directly instead. Don't
780 free allocated memory until function exit.
782 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
784 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
786 2017-02-03 Nick Clifton <nickc@redhat.com>
789 * aarch64-opc.c (print_register_list): Ensure that the register
790 list index will fir into the tb buffer.
791 (print_register_offset_address): Likewise.
792 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
794 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
797 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
798 instructions when the previous fetch packet ends with a 32-bit
801 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
803 * pru-opc.c: Remove vague reference to a future GDB port.
805 2017-01-20 Nick Clifton <nickc@redhat.com>
807 * po/ga.po: Updated Irish translation.
809 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
811 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
813 2017-01-13 Yao Qi <yao.qi@linaro.org>
815 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
816 if FETCH_DATA returns 0.
817 (m68k_scan_mask): Likewise.
818 (print_insn_m68k): Update code to handle -1 return value.
820 2017-01-13 Yao Qi <yao.qi@linaro.org>
822 * m68k-dis.c (enum print_insn_arg_error): New.
823 (NEXTBYTE): Replace -3 with
824 PRINT_INSN_ARG_MEMORY_ERROR.
825 (NEXTULONG): Likewise.
826 (NEXTSINGLE): Likewise.
827 (NEXTDOUBLE): Likewise.
828 (NEXTDOUBLE): Likewise.
829 (NEXTPACKED): Likewise.
830 (FETCH_ARG): Likewise.
831 (FETCH_DATA): Update comments.
832 (print_insn_arg): Update comments. Replace magic numbers with
834 (match_insn_m68k): Likewise.
836 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
838 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
839 * i386-dis-evex.h (evex_table): Updated.
840 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
841 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
842 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
843 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
844 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
845 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
846 * i386-init.h: Regenerate.
849 2017-01-12 Yao Qi <yao.qi@linaro.org>
851 * msp430-dis.c (msp430_singleoperand): Return -1 if
852 msp430dis_opcode_signed returns false.
853 (msp430_doubleoperand): Likewise.
854 (msp430_branchinstr): Return -1 if
855 msp430dis_opcode_unsigned returns false.
856 (msp430x_calla_instr): Likewise.
857 (print_insn_msp430): Likewise.
859 2017-01-05 Nick Clifton <nickc@redhat.com>
862 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
863 could not be matched.
864 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
867 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
869 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
870 (aarch64_opcode_table): Use RCPC_INSN.
872 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
874 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
876 * riscv-opcodes/all-opcodes: Likewise.
878 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
880 * riscv-dis.c (print_insn_args): Add fall through comment.
882 2017-01-03 Nick Clifton <nickc@redhat.com>
884 * po/sr.po: New Serbian translation.
885 * configure.ac (ALL_LINGUAS): Add sr.
886 * configure: Regenerate.
888 2017-01-02 Alan Modra <amodra@gmail.com>
890 * epiphany-desc.h: Regenerate.
891 * epiphany-opc.h: Regenerate.
892 * fr30-desc.h: Regenerate.
893 * fr30-opc.h: Regenerate.
894 * frv-desc.h: Regenerate.
895 * frv-opc.h: Regenerate.
896 * ip2k-desc.h: Regenerate.
897 * ip2k-opc.h: Regenerate.
898 * iq2000-desc.h: Regenerate.
899 * iq2000-opc.h: Regenerate.
900 * lm32-desc.h: Regenerate.
901 * lm32-opc.h: Regenerate.
902 * m32c-desc.h: Regenerate.
903 * m32c-opc.h: Regenerate.
904 * m32r-desc.h: Regenerate.
905 * m32r-opc.h: Regenerate.
906 * mep-desc.h: Regenerate.
907 * mep-opc.h: Regenerate.
908 * mt-desc.h: Regenerate.
909 * mt-opc.h: Regenerate.
910 * or1k-desc.h: Regenerate.
911 * or1k-opc.h: Regenerate.
912 * xc16x-desc.h: Regenerate.
913 * xc16x-opc.h: Regenerate.
914 * xstormy16-desc.h: Regenerate.
915 * xstormy16-opc.h: Regenerate.
917 2017-01-02 Alan Modra <amodra@gmail.com>
919 Update year range in copyright notice of all files.
921 For older changes see ChangeLog-2016
923 Copyright (C) 2017 Free Software Foundation, Inc.
925 Copying and distribution of this file, with or without modification,
926 are permitted in any medium without royalty provided the copyright
927 notice and this notice are preserved.
933 version-control: never