1 2004-11-19 Alan Modra <amodra@bigpond.net.au>
3 * maxq-dis.c: Formatting.
4 (print_insn): Warning fix.
6 2004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
8 * arm-dis.c (WORD_ADDRESS): Define.
9 (print_insn): Use it. Correct big-endian end-of-section handling.
11 2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
12 Vineet Sharma <vineets@noida.hcltech.com>
14 * maxq-dis.c: New file.
15 * disassemble.c (ARCH_maxq): Define.
16 (disassembler): Add 'print_insn_maxq_little' for handling maxq
18 * configure.in: Add case for bfd_maxq_arch.
19 * configure: Regenerate.
20 * Makefile.am: Add support for maxq-dis.c
21 * Makefile.in: Regenerate.
22 * aclocal.m4: Regenerate.
24 2004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
26 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
28 * crx-dis.c: Likewise.
30 2004-11-04 Hans-Peter Nilsson <hp@axis.com>
32 Generally, handle CRISv32.
33 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
34 (struct cris_disasm_data): New type.
35 (format_reg, format_hex, cris_constraint, print_flags)
36 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
38 (format_sup_reg, print_insn_crisv32_with_register_prefix)
39 (print_insn_crisv32_without_register_prefix)
40 (print_insn_crisv10_v32_with_register_prefix)
41 (print_insn_crisv10_v32_without_register_prefix)
42 (cris_parse_disassembler_options): New functions.
43 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
44 parameter. All callers changed.
45 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
47 (cris_constraint) <case 'Y', 'U'>: New cases.
48 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
50 (print_with_operands) <case 'Y'>: New case.
51 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
52 <case 'N', 'Y', 'Q'>: New cases.
53 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
54 (print_insn_cris_with_register_prefix)
55 (print_insn_cris_without_register_prefix): Call
56 cris_parse_disassembler_options.
57 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
58 for CRISv32 and the size of immediate operands. New v32-only
59 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
60 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
61 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
62 Change brp to be v3..v10.
63 (cris_support_regs): New vector.
64 (cris_opcodes): Update head comment. New format characters '[',
65 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
66 Add new opcodes for v32 and adjust existing opcodes to accommodate
67 differences to earlier variants.
68 (cris_cond15s): New vector.
70 2004-11-04 Jan Beulich <jbeulich@novell.com>
72 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
74 (Mp): Use f_mode rather than none at all.
75 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
76 replaces what previously was x_mode; x_mode now means 128-bit SSE
78 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
79 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
80 pinsrw's second operand is Edqw.
81 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
82 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
83 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
84 mode when an operand size override is present or always suffixing.
85 More instructions will need to be added to this group.
86 (putop): Handle new macro chars 'C' (short/long suffix selector),
87 'I' (Intel mode override for following macro char), and 'J' (for
88 adding the 'l' prefix to far branches in AT&T mode). When an
89 alternative was specified in the template, honor macro character when
90 specified for Intel mode.
91 (OP_E): Handle new *_mode values. Correct pointer specifications for
92 memory operands. Consolidate output of index register.
93 (OP_G): Handle new *_mode values.
94 (OP_I): Handle const_1_mode.
95 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
96 respective opcode prefix bits have been consumed.
97 (OP_EM, OP_EX): Provide some default handling for generating pointer
100 2004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
102 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
105 2004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
107 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
108 (getregliststring): Support HI/LO and user registers.
109 * crx-opc.c (crx_instruction): Update data structure according to the
110 rearrangement done in CRX opcode header file.
111 (crx_regtab): Likewise.
112 (crx_optab): Likewise.
113 (crx_instruction): Reorder load/stor instructions, remove unsupported
115 support new Co-Processor instruction 'cpi'.
117 2004-10-27 Nick Clifton <nickc@redhat.com>
119 * opcodes/iq2000-asm.c: Regenerate.
120 * opcodes/iq2000-desc.c: Regenerate.
121 * opcodes/iq2000-desc.h: Regenerate.
122 * opcodes/iq2000-dis.c: Regenerate.
123 * opcodes/iq2000-ibld.c: Regenerate.
124 * opcodes/iq2000-opc.c: Regenerate.
125 * opcodes/iq2000-opc.h: Regenerate.
127 2004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
129 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
130 us4, us5 (respectively).
131 Remove unsupported 'popa' instruction.
132 Reverse operands order in store co-processor instructions.
134 2004-10-15 Alan Modra <amodra@bigpond.net.au>
136 * Makefile.am: Run "make dep-am"
137 * Makefile.in: Regenerate.
139 2004-10-12 Bob Wilson <bob.wilson@acm.org>
141 * xtensa-dis.c: Use ISO C90 formatting.
143 2004-10-09 Alan Modra <amodra@bigpond.net.au>
145 * ppc-opc.c: Revert 2004-09-09 change.
147 2004-10-07 Bob Wilson <bob.wilson@acm.org>
149 * xtensa-dis.c (state_names): Delete.
150 (fetch_data): Use xtensa_isa_maxlength.
151 (print_xtensa_operand): Replace operand parameter with opcode/operand
152 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
153 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
154 instruction bundles. Use xmalloc instead of malloc.
156 2004-10-07 David Gibson <david@gibson.dropbear.id.au>
158 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
161 2004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
163 * crx-opc.c (crx_instruction): Support Co-processor insns.
164 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
165 (getregliststring): Change function to use the above enum.
166 (print_arg): Handle CO-Processor insns.
167 (crx_cinvs): Add 'b' option to invalidate the branch-target
170 2004-10-06 Aldy Hernandez <aldyh@redhat.com>
172 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
173 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
174 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
175 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
176 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
178 2004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
180 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
183 2004-09-30 Paul Brook <paul@codesourcery.com>
185 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
186 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
188 2004-09-17 H.J. Lu <hongjiu.lu@intel.com>
190 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
191 (CONFIG_STATUS_DEPENDENCIES): New.
193 (config.status): Likewise.
194 * Makefile.in: Regenerated.
196 2004-09-17 Alan Modra <amodra@bigpond.net.au>
198 * Makefile.am: Run "make dep-am".
199 * Makefile.in: Regenerate.
200 * aclocal.m4: Regenerate.
201 * configure: Regenerate.
202 * po/POTFILES.in: Regenerate.
203 * po/opcodes.pot: Regenerate.
205 2004-09-11 Andreas Schwab <schwab@suse.de>
207 * configure: Rebuild.
209 2004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
211 * ppc-opc.c (L): Make this field not optional.
213 2004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
215 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
216 Fix parameter to 'm[t|f]csr' insns.
218 2004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
220 * configure.in: Autoupdate to autoconf 2.59.
221 * aclocal.m4: Rebuild with aclocal 1.4p6.
222 * configure: Rebuild with autoconf 2.59.
223 * Makefile.in: Rebuild with automake 1.4p6 (picking up
224 bfd changes for autoconf 2.59 on the way).
225 * config.in: Rebuild with autoheader 2.59.
227 2004-08-27 Richard Sandiford <rsandifo@redhat.com>
229 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
231 2004-07-30 Michal Ludvig <mludvig@suse.cz>
233 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
234 (GRPPADLCK2): New define.
235 (twobyte_has_modrm): True for 0xA6.
236 (grps): GRPPADLCK2 for opcode 0xA6.
238 2004-07-29 Alexandre Oliva <aoliva@redhat.com>
240 Introduce SH2a support.
241 * sh-opc.h (arch_sh2a_base): Renumber.
242 (arch_sh2a_nofpu_base): Remove.
243 (arch_sh_base_mask): Adjust.
244 (arch_opann_mask): New.
245 (arch_sh2a, arch_sh2a_nofpu): Adjust.
246 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
247 (sh_table): Adjust whitespace.
248 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
249 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
250 instruction list throughout.
251 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
252 of arch_sh2a in instruction list throughout.
253 (arch_sh2e_up): Accomodate above changes.
254 (arch_sh2_up): Ditto.
255 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
256 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
257 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
258 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
259 * sh-opc.h (arch_sh2a_nofpu): New.
260 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
261 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
263 2004-01-20 DJ Delorie <dj@redhat.com>
264 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
265 2003-12-29 DJ Delorie <dj@redhat.com>
266 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
267 sh_opcode_info, sh_table): Add sh2a support.
268 (arch_op32): New, to tag 32-bit opcodes.
269 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
270 2003-12-02 Michael Snyder <msnyder@redhat.com>
271 * sh-opc.h (arch_sh2a): Add.
272 * sh-dis.c (arch_sh2a): Handle.
273 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
275 2004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
277 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
279 2004-07-22 Nick Clifton <nickc@redhat.com>
282 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
283 insns - this is done by objdump itself.
284 * h8500-dis.c (print_insn_h8500): Likewise.
286 2004-07-21 Jan Beulich <jbeulich@novell.com>
288 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
289 regardless of address size prefix in effect.
290 (ptr_reg): Size or address registers does not depend on rex64, but
291 on the presence of an address size override.
292 (OP_MMX): Use rex.x only for xmm registers.
293 (OP_EM): Use rex.z only for xmm registers.
295 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
297 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
298 move/branch operations to the bottom so that VR5400 multimedia
299 instructions take precedence in disassembly.
301 2004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
303 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
304 ISA-specific "break" encoding.
306 2004-07-13 Elvis Chiang <elvisfb@gmail.com>
308 * arm-opc.h: Fix typo in comment.
310 2004-07-11 Andreas Schwab <schwab@suse.de>
312 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
314 2004-07-09 Andreas Schwab <schwab@suse.de>
316 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
318 2004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
320 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
321 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
322 (crx-dis.lo): New target.
323 (crx-opc.lo): Likewise.
324 * Makefile.in: Regenerate.
325 * configure.in: Handle bfd_crx_arch.
326 * configure: Regenerate.
327 * crx-dis.c: New file.
328 * crx-opc.c: New file.
329 * disassemble.c (ARCH_crx): Define.
330 (disassembler): Handle ARCH_crx.
332 2004-06-29 James E Wilson <wilson@specifixinc.com>
334 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
335 * ia64-asmtab.c: Regnerate.
337 2004-06-28 Alan Modra <amodra@bigpond.net.au>
339 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
340 (extract_fxm): Don't test dialect.
341 (XFXFXM_MASK): Include the power4 bit.
342 (XFXM): Add p4 param.
343 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
345 2004-06-27 Alexandre Oliva <aoliva@redhat.com>
347 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
348 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
350 2004-06-26 Alan Modra <amodra@bigpond.net.au>
352 * ppc-opc.c (BH, XLBH_MASK): Define.
353 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
355 2004-06-24 Alan Modra <amodra@bigpond.net.au>
357 * i386-dis.c (x_mode): Comment.
358 (two_source_ops): File scope.
359 (float_mem): Correct fisttpll and fistpll.
360 (float_mem_mode): New table.
362 (OP_E): Correct intel mode PTR output.
363 (ptr_reg): Use open_char and close_char.
364 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
365 operands. Set two_source_ops.
367 2004-06-15 Alan Modra <amodra@bigpond.net.au>
369 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
370 instead of _raw_size.
372 2004-06-08 Jakub Jelinek <jakub@redhat.com>
374 * ia64-gen.c (in_iclass): Handle more postinc st
376 * ia64-asmtab.c: Rebuilt.
378 2004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
380 * s390-opc.txt: Correct architecture mask for some opcodes.
381 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
382 in the esa mode as well.
384 2004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
386 * sh-dis.c (target_arch): Make unsigned.
387 (print_insn_sh): Replace (most of) switch with a call to
388 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
389 * sh-opc.h: Redefine architecture flags values.
390 Add sh3-nommu architecture.
391 Reorganise <arch>_up macros so they make more visual sense.
392 (SH_MERGE_ARCH_SET): Define new macro.
393 (SH_VALID_BASE_ARCH_SET): Likewise.
394 (SH_VALID_MMU_ARCH_SET): Likewise.
395 (SH_VALID_CO_ARCH_SET): Likewise.
396 (SH_VALID_ARCH_SET): Likewise.
397 (SH_MERGE_ARCH_SET_VALID): Likewise.
398 (SH_ARCH_SET_HAS_FPU): Likewise.
399 (SH_ARCH_SET_HAS_DSP): Likewise.
400 (SH_ARCH_UNKNOWN_ARCH): Likewise.
401 (sh_get_arch_from_bfd_mach): Add prototype.
402 (sh_get_arch_up_from_bfd_mach): Likewise.
403 (sh_get_bfd_mach_from_arch_set): Likewise.
404 (sh_merge_bfd_arc): Likewise.
406 2004-05-24 Peter Barada <peter@the-baradas.com>
408 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
409 into new match_insn_m68k function. Loop over canidate
410 matches and select first that completely matches.
411 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
412 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
413 to verify addressing for MAC/EMAC.
414 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
415 reigster halves since 'fpu' and 'spl' look misleading.
416 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
417 * m68k-opc.c: Rearragne mac/emac cases to use longest for
418 first, tighten up match masks.
419 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
420 'size' from special case code in print_insn_m68k to
421 determine decode size of insns.
423 2004-05-19 Alan Modra <amodra@bigpond.net.au>
425 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
426 well as when -mpower4.
428 2004-05-13 Nick Clifton <nickc@redhat.com>
430 * po/fr.po: Updated French translation.
432 2004-05-05 Peter Barada <peter@the-baradas.com>
434 * m68k-dis.c(print_insn_m68k): Add new chips, use core
435 variants in arch_mask. Only set m68881/68851 for 68k chips.
436 * m68k-op.c: Switch from ColdFire chips to core variants.
438 2004-05-05 Alan Modra <amodra@bigpond.net.au>
441 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
443 2004-04-29 Ben Elliston <bje@au.ibm.com>
445 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
446 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
448 2004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
450 * sh-dis.c (print_insn_sh): Print the value in constant pool
451 as a symbol if it looks like a symbol.
453 2004-04-22 Peter Barada <peter@the-baradas.com>
455 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
456 appropriate ColdFire architectures.
457 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
459 Add EMAC instructions, fix MAC instructions. Remove
460 macmw/macml/msacmw/msacml instructions since mask addressing now
463 2004-04-20 Jakub Jelinek <jakub@redhat.com>
465 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
466 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
467 suffix. Use fmov*x macros, create all 3 fpsize variants in one
468 macro. Adjust all users.
470 2004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
472 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
475 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
477 * m32r-asm.c: Regenerate.
479 2004-03-29 Stan Shebs <shebs@apple.com>
481 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
484 2004-03-19 Alan Modra <amodra@bigpond.net.au>
486 * aclocal.m4: Regenerate.
487 * config.in: Regenerate.
488 * configure: Regenerate.
489 * po/POTFILES.in: Regenerate.
490 * po/opcodes.pot: Regenerate.
492 2004-03-16 Alan Modra <amodra@bigpond.net.au>
494 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
496 * ppc-opc.c (RA0): Define.
497 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
498 (RAOPT): Rename from RAO. Update all uses.
499 (powerpc_opcodes): Use RA0 as appropriate.
501 2004-03-15 Aldy Hernandez <aldyh@redhat.com>
503 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
505 2004-03-15 Alan Modra <amodra@bigpond.net.au>
507 * sparc-dis.c (print_insn_sparc): Update getword prototype.
509 2004-03-12 Michal Ludvig <mludvig@suse.cz>
511 * i386-dis.c (GRPPLOCK): Delete.
512 (grps): Delete GRPPLOCK entry.
514 2004-03-12 Alan Modra <amodra@bigpond.net.au>
516 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
518 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
520 (dis386): Use NOP_Fixup on "nop".
521 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
522 (twobyte_has_modrm): Set for 0xa7.
523 (padlock_table): Delete. Move to..
524 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
526 (print_insn): Revert PADLOCK_SPECIAL code.
527 (OP_E): Delete sfence, lfence, mfence checks.
529 2004-03-12 Jakub Jelinek <jakub@redhat.com>
531 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
532 (INVLPG_Fixup): New function.
533 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
535 2004-03-12 Michal Ludvig <mludvig@suse.cz>
537 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
538 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
539 (padlock_table): New struct with PadLock instructions.
540 (print_insn): Handle PADLOCK_SPECIAL.
542 2004-03-12 Alan Modra <amodra@bigpond.net.au>
544 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
545 (OP_E): Twiddle clflush to sfence here.
547 2004-03-08 Nick Clifton <nickc@redhat.com>
549 * po/de.po: Updated German translation.
551 2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
553 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
554 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
555 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
558 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
560 * frv-asm.c: Regenerate.
561 * frv-desc.c: Regenerate.
562 * frv-desc.h: Regenerate.
563 * frv-dis.c: Regenerate.
564 * frv-ibld.c: Regenerate.
565 * frv-opc.c: Regenerate.
566 * frv-opc.h: Regenerate.
568 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
570 * frv-desc.c, frv-opc.c: Regenerate.
572 2004-03-01 Richard Sandiford <rsandifo@redhat.com>
574 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
576 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
578 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
579 Also correct mistake in the comment.
581 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
583 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
584 ensure that double registers have even numbers.
585 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
586 that reserved instruction 0xfffd does not decode the same
588 * sh-opc.h: Add REG_N_D nibble type and use it whereever
589 REG_N refers to a double register.
590 Add REG_N_B01 nibble type and use it instead of REG_NM
592 Adjust the bit patterns in a few comments.
594 2004-02-25 Aldy Hernandez <aldyh@redhat.com>
596 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
598 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
600 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
602 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
604 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
606 2004-02-20 Aldy Hernandez <aldyh@redhat.com>
608 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
609 mtivor32, mtivor33, mtivor34.
611 2004-02-19 Aldy Hernandez <aldyh@redhat.com>
613 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
615 2004-02-10 Petko Manolov <petkan@nucleusys.com>
617 * arm-opc.h Maverick accumulator register opcode fixes.
619 2004-02-13 Ben Elliston <bje@wasabisystems.com>
621 * m32r-dis.c: Regenerate.
623 2004-01-27 Michael Snyder <msnyder@redhat.com>
625 * sh-opc.h (sh_table): "fsrra", not "fssra".
627 2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
629 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
632 2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
634 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
636 2004-01-19 Alan Modra <amodra@bigpond.net.au>
638 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
639 1. Don't print scale factor on AT&T mode when index missing.
641 2004-01-16 Alexandre Oliva <aoliva@redhat.com>
643 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
644 when loaded into XR registers.
646 2004-01-14 Richard Sandiford <rsandifo@redhat.com>
648 * frv-desc.h: Regenerate.
649 * frv-desc.c: Regenerate.
650 * frv-opc.c: Regenerate.
652 2004-01-13 Michael Snyder <msnyder@redhat.com>
654 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
656 2004-01-09 Paul Brook <paul@codesourcery.com>
658 * arm-opc.h (arm_opcodes): Move generic mcrr after known
661 2004-01-07 Daniel Jacobowitz <drow@mvista.com>
663 * Makefile.am (libopcodes_la_DEPENDENCIES)
664 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
665 comment about the problem.
666 * Makefile.in: Regenerate.
668 2004-01-06 Alexandre Oliva <aoliva@redhat.com>
670 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
671 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
672 cut&paste errors in shifting/truncating numerical operands.
673 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
674 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
675 (parse_uslo16): Likewise.
676 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
677 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
678 (parse_s12): Likewise.
679 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
680 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
681 (parse_uslo16): Likewise.
682 (parse_uhi16): Parse gothi and gotfuncdeschi.
683 (parse_d12): Parse got12 and gotfuncdesc12.
684 (parse_s12): Likewise.
686 2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
688 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
689 instruction which looks similar to an 'rla' instruction.
691 For older changes see ChangeLog-0203
697 version-control: never