1 2019-09-03 Nick Clifton <nickc@redhat.com>
4 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
5 (MAX_SPEC_REG_NAME_LEN): Define.
6 (struct mmix_dis_info): Use defined constants for array lengths.
7 (get_reg_name): New function.
8 (get_sprec_reg_name): New function.
9 (print_insn_mmix): Use new functions.
11 2019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
13 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
14 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
15 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
17 2019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
19 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
20 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
21 (aarch64_sys_reg_supported_p): Update checks for the above.
23 2019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
25 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
26 cases MVE_SQRSHRL and MVE_UQRSHLL.
27 (print_insn_mve): Add case for specifier 'k' to check
28 specific bit of the instruction.
30 2019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
33 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
34 encountering an unknown machine type.
35 (print_insn_arc): Handle arc_insn_length returning 0. In error
36 cases return -1 rather than calling abort.
38 2019-08-07 Jan Beulich <jbeulich@suse.com>
40 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
41 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
43 * i386-tbl.h: Re-generate.
45 2019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
47 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
50 2019-07-30 Mel Chen <mel.chen@sifive.com>
52 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
53 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
55 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
58 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
60 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
61 and MPY class instructions.
62 (parse_option): Add nps400 option.
63 (print_arc_disassembler_options): Add nps400 info.
65 2019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
67 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
70 * arc-opc.c (RAD_CHK): Add.
71 * arc-tbl.h: Regenerate.
73 2019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
75 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
76 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
78 2019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
80 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
81 instructions as UNPREDICTABLE.
83 2019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
85 * bpf-desc.c: Regenerated.
87 2019-07-17 Jan Beulich <jbeulich@suse.com>
89 * i386-gen.c (static_assert): Define.
91 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
92 (Opcode_Modifier_Num): ... this.
95 2019-07-16 Jan Beulich <jbeulich@suse.com>
97 * i386-gen.c (operand_types): Move RegMem ...
98 (opcode_modifiers): ... here.
99 * i386-opc.h (RegMem): Move to opcode modifer enum.
100 (union i386_operand_type): Move regmem field ...
101 (struct i386_opcode_modifier): ... here.
102 * i386-opc.tbl (RegMem): Define.
103 (mov, movq): Move RegMem on segment, control, debug, and test
105 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
106 to non-SSE2AVX flavor.
107 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
108 Move RegMem on register only flavors. Drop IgnoreSize from
109 legacy encoding flavors.
110 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
112 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
113 register only flavors.
114 (vmovd): Move RegMem and drop IgnoreSize on register only
115 flavor. Change opcode and operand order to store form.
116 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
118 2019-07-16 Jan Beulich <jbeulich@suse.com>
120 * i386-gen.c (operand_type_init, operand_types): Replace SReg
122 * i386-opc.h (SReg2, SReg3): Replace by ...
124 (union i386_operand_type): Replace sreg fields.
125 * i386-opc.tbl (mov, ): Use SReg.
126 (push, pop): Likewies. Drop i386 and x86-64 specific segment
128 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
129 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
131 2019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
133 * bpf-desc.c: Regenerate.
134 * bpf-opc.c: Likewise.
135 * bpf-opc.h: Likewise.
137 2019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
139 * bpf-desc.c: Regenerate.
140 * bpf-opc.c: Likewise.
142 2019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
144 * arm-dis.c (print_insn_coprocessor): Rename index to
147 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
149 * riscv-opc.c (riscv_insn_types): Add r4 type.
151 * riscv-opc.c (riscv_insn_types): Add b and j type.
153 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
154 format for sb type and correct s type.
156 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
158 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
159 SVE FMOV alias of FCPY.
161 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
163 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
164 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
166 2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
168 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
169 registers in an instruction prefixed by MOVPRFX.
171 2019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
173 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
174 sve_size_13 icode to account for variant behaviour of
176 * aarch64-dis-2.c: Regenerate.
177 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
178 sve_size_13 icode to account for variant behaviour of
180 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
181 (OP_SVE_VVV_Q_D): Add new qualifier.
182 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
183 (struct aarch64_opcode): Split pmull{t,b} into those requiring
186 2019-07-01 Jan Beulich <jbeulich@suse.com>
188 * opcodes/i386-gen.c (operand_type_init): Remove
189 OPERAND_TYPE_VEC_IMM4 entry.
190 (operand_types): Remove Vec_Imm4.
191 * opcodes/i386-opc.h (Vec_Imm4): Delete.
192 (union i386_operand_type): Remove vec_imm4.
193 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
194 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
196 2019-07-01 Jan Beulich <jbeulich@suse.com>
198 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
199 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
200 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
201 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
202 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
203 monitorx, mwaitx): Drop ImmExt from operand-less forms.
204 * i386-tbl.h: Re-generate.
206 2019-07-01 Jan Beulich <jbeulich@suse.com>
208 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
210 * i386-tbl.h: Re-generate.
212 2019-07-01 Jan Beulich <jbeulich@suse.com>
214 * i386-opc.tbl (C): New.
215 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
216 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
217 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
218 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
219 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
220 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
221 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
222 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
223 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
224 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
225 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
226 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
227 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
228 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
229 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
230 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
231 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
232 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
233 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
234 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
235 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
236 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
237 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
238 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
239 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
240 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
242 * i386-tbl.h: Re-generate.
244 2019-07-01 Jan Beulich <jbeulich@suse.com>
246 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
248 * i386-tbl.h: Re-generate.
250 2019-07-01 Jan Beulich <jbeulich@suse.com>
252 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
253 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
254 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
255 * i386-tbl.h: Re-generate.
257 2019-07-01 Jan Beulich <jbeulich@suse.com>
259 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
260 Disp8MemShift from register only templates.
261 * i386-tbl.h: Re-generate.
263 2019-07-01 Jan Beulich <jbeulich@suse.com>
265 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
266 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
267 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
268 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
269 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
270 EVEX_W_0F11_P_3_M_1): Delete.
271 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
272 EVEX_W_0F11_P_3): New.
273 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
274 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
275 MOD_EVEX_0F11_PREFIX_3 table entries.
276 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
277 PREFIX_EVEX_0F11 table entries.
278 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
279 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
280 EVEX_W_0F11_P_3_M_{0,1} table entries.
282 2019-07-01 Jan Beulich <jbeulich@suse.com>
284 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
287 2019-06-27 H.J. Lu <hongjiu.lu@intel.com>
290 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
291 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
292 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
293 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
294 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
295 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
296 EVEX_LEN_0F38C7_R_6_P_2_W_1.
297 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
298 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
299 PREFIX_EVEX_0F38C6_REG_6 entries.
300 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
301 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
302 EVEX_W_0F38C7_R_6_P_2 entries.
303 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
304 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
305 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
306 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
307 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
308 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
309 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
311 2019-06-27 Jan Beulich <jbeulich@suse.com>
313 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
314 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
315 VEX_LEN_0F2D_P_3): Delete.
316 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
317 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
318 (prefix_table): ... here.
320 2019-06-27 Jan Beulich <jbeulich@suse.com>
322 * i386-dis.c (Iq): Delete.
324 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
326 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
327 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
328 (OP_E_memory): Also honor needindex when deciding whether an
329 address size prefix needs printing.
330 (OP_I): Remove handling of q_mode. Add handling of d_mode.
332 2019-06-26 Jim Wilson <jimw@sifive.com>
335 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
336 Set info->display_endian to info->endian_code.
338 2019-06-25 Jan Beulich <jbeulich@suse.com>
340 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
341 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
342 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
343 OPERAND_TYPE_ACC64 entries.
344 * i386-init.h: Re-generate.
346 2019-06-25 Jan Beulich <jbeulich@suse.com>
348 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
350 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
352 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
354 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
355 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
357 2019-06-25 Jan Beulich <jbeulich@suse.com>
359 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
362 2019-06-25 Jan Beulich <jbeulich@suse.com>
364 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
365 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
367 * i386-opc.tbl (movnti): Add IgnoreSize.
368 * i386-tbl.h: Re-generate.
370 2019-06-25 Jan Beulich <jbeulich@suse.com>
372 * i386-opc.tbl (and): Mark Imm8S form for optimization.
373 * i386-tbl.h: Re-generate.
375 2019-06-21 H.J. Lu <hongjiu.lu@intel.com>
377 * i386-dis-evex.h: Break into ...
378 * i386-dis-evex-len.h: New file.
379 * i386-dis-evex-mod.h: Likewise.
380 * i386-dis-evex-prefix.h: Likewise.
381 * i386-dis-evex-reg.h: Likewise.
382 * i386-dis-evex-w.h: Likewise.
383 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
384 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
387 2019-06-19 H.J. Lu <hongjiu.lu@intel.com>
390 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
391 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
393 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
394 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
395 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
396 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
397 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
398 EVEX_LEN_0F385B_P_2_W_1.
399 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
400 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
401 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
402 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
403 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
404 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
405 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
406 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
407 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
408 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
410 2019-06-17 H.J. Lu <hongjiu.lu@intel.com>
413 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
414 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
415 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
416 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
417 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
418 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
419 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
420 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
421 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
422 EVEX_LEN_0F3A43_P_2_W_1.
423 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
424 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
425 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
426 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
427 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
428 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
429 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
430 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
431 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
432 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
433 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
434 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
436 2019-06-14 Nick Clifton <nickc@redhat.com>
438 * po/fr.po; Updated French translation.
440 2019-06-13 Stafford Horne <shorne@gmail.com>
442 * or1k-asm.c: Regenerated.
443 * or1k-desc.c: Regenerated.
444 * or1k-desc.h: Regenerated.
445 * or1k-dis.c: Regenerated.
446 * or1k-ibld.c: Regenerated.
447 * or1k-opc.c: Regenerated.
448 * or1k-opc.h: Regenerated.
449 * or1k-opinst.c: Regenerated.
451 2019-06-12 Peter Bergner <bergner@linux.ibm.com>
453 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
455 2019-06-05 H.J. Lu <hongjiu.lu@intel.com>
458 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
459 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
460 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
461 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
462 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
463 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
464 EVEX_LEN_0F3A1B_P_2_W_1.
465 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
466 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
467 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
468 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
469 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
470 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
471 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
472 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
474 2019-06-04 H.J. Lu <hongjiu.lu@intel.com>
477 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
478 EVEX.vvvv when disassembling VEX and EVEX instructions.
479 (OP_VEX): Set vex.register_specifier to 0 after readding
480 vex.register_specifier.
481 (OP_Vex_2src_1): Likewise.
482 (OP_Vex_2src_2): Likewise.
483 (OP_LWP_E): Likewise.
484 (OP_EX_Vex): Don't check vex.register_specifier.
485 (OP_XMM_Vex): Likewise.
487 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
488 Lili Cui <lili.cui@intel.com>
490 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
491 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
493 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
494 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
495 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
496 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
497 (i386_cpu_flags): Add cpuavx512_vp2intersect.
498 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
499 * i386-init.h: Regenerated.
500 * i386-tbl.h: Likewise.
502 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
503 Lili Cui <lili.cui@intel.com>
505 * doc/c-i386.texi: Document enqcmd.
506 * testsuite/gas/i386/enqcmd-intel.d: New file.
507 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
508 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
509 * testsuite/gas/i386/enqcmd.d: Likewise.
510 * testsuite/gas/i386/enqcmd.s: Likewise.
511 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
512 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
513 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
514 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
515 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
516 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
517 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
520 2019-06-04 Alan Hayward <alan.hayward@arm.com>
522 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
524 2019-06-03 Alan Modra <amodra@gmail.com>
526 * ppc-dis.c (prefix_opcd_indices): Correct size.
528 2019-05-28 H.J. Lu <hongjiu.lu@intel.com>
531 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
533 * i386-tbl.h: Regenerated.
535 2019-05-24 Alan Modra <amodra@gmail.com>
537 * po/POTFILES.in: Regenerate.
539 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
540 Alan Modra <amodra@gmail.com>
542 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
543 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
544 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
545 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
546 XTOP>): Define and add entries.
547 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
548 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
549 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
550 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
552 2019-05-24 Peter Bergner <bergner@linux.ibm.com>
553 Alan Modra <amodra@gmail.com>
555 * ppc-dis.c (ppc_opts): Add "future" entry.
556 (PREFIX_OPCD_SEGS): Define.
557 (prefix_opcd_indices): New array.
558 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
559 (lookup_prefix): New function.
560 (print_insn_powerpc): Handle 64-bit prefix instructions.
561 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
562 (PMRR, POWERXX): Define.
563 (prefix_opcodes): New instruction table.
564 (prefix_num_opcodes): New constant.
566 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
568 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
569 * configure: Regenerated.
570 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
572 (HFILES): Add bpf-desc.h and bpf-opc.h.
573 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
574 bpf-ibld.c and bpf-opc.c.
576 * Makefile.in: Regenerated.
577 * disassemble.c (ARCH_bpf): Define.
578 (disassembler): Add case for bfd_arch_bpf.
579 (disassemble_init_for_target): Likewise.
580 (enum epbf_isa_attr): Define.
581 * disassemble.h: extern print_insn_bpf.
582 * bpf-asm.c: Generated.
583 * bpf-opc.h: Likewise.
584 * bpf-opc.c: Likewise.
585 * bpf-ibld.c: Likewise.
586 * bpf-dis.c: Likewise.
587 * bpf-desc.h: Likewise.
588 * bpf-desc.c: Likewise.
590 2019-05-21 Sudakshina Das <sudi.das@arm.com>
592 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
593 and VMSR with the new operands.
595 2019-05-21 Sudakshina Das <sudi.das@arm.com>
597 * arm-dis.c (enum mve_instructions): New enum
598 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
600 (mve_opcodes): New instructions as above.
601 (is_mve_encoding_conflict): Add cases for csinc, csinv,
603 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
605 2019-05-21 Sudakshina Das <sudi.das@arm.com>
607 * arm-dis.c (emun mve_instructions): Updated for new instructions.
608 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
609 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
610 uqshl, urshrl and urshr.
611 (is_mve_okay_in_it): Add new instructions to TRUE list.
612 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
613 (print_insn_mve): Updated to accept new %j,
614 %<bitfield>m and %<bitfield>n patterns.
616 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
618 * mips-opc.c (mips_builtin_opcodes): Change source register
621 2019-05-20 Nick Clifton <nickc@redhat.com>
623 * po/fr.po: Updated French translation.
625 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
626 Michael Collison <michael.collison@arm.com>
628 * arm-dis.c (thumb32_opcodes): Add new instructions.
629 (enum mve_instructions): Likewise.
630 (enum mve_undefined): Add new reasons.
631 (is_mve_encoding_conflict): Handle new instructions.
632 (is_mve_undefined): Likewise.
633 (is_mve_unpredictable): Likewise.
634 (print_mve_undefined): Likewise.
635 (print_mve_size): Likewise.
637 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
638 Michael Collison <michael.collison@arm.com>
640 * arm-dis.c (thumb32_opcodes): Add new instructions.
641 (enum mve_instructions): Likewise.
642 (is_mve_encoding_conflict): Handle new instructions.
643 (is_mve_undefined): Likewise.
644 (is_mve_unpredictable): Likewise.
645 (print_mve_size): Likewise.
647 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
648 Michael Collison <michael.collison@arm.com>
650 * arm-dis.c (thumb32_opcodes): Add new instructions.
651 (enum mve_instructions): Likewise.
652 (is_mve_encoding_conflict): Likewise.
653 (is_mve_unpredictable): Likewise.
654 (print_mve_size): Likewise.
656 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
657 Michael Collison <michael.collison@arm.com>
659 * arm-dis.c (thumb32_opcodes): Add new instructions.
660 (enum mve_instructions): Likewise.
661 (is_mve_encoding_conflict): Handle new instructions.
662 (is_mve_undefined): Likewise.
663 (is_mve_unpredictable): Likewise.
664 (print_mve_size): Likewise.
666 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
667 Michael Collison <michael.collison@arm.com>
669 * arm-dis.c (thumb32_opcodes): Add new instructions.
670 (enum mve_instructions): Likewise.
671 (is_mve_encoding_conflict): Handle new instructions.
672 (is_mve_undefined): Likewise.
673 (is_mve_unpredictable): Likewise.
674 (print_mve_size): Likewise.
675 (print_insn_mve): Likewise.
677 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
678 Michael Collison <michael.collison@arm.com>
680 * arm-dis.c (thumb32_opcodes): Add new instructions.
681 (print_insn_thumb32): Handle new instructions.
683 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
684 Michael Collison <michael.collison@arm.com>
686 * arm-dis.c (enum mve_instructions): Add new instructions.
687 (enum mve_undefined): Add new reasons.
688 (is_mve_encoding_conflict): Handle new instructions.
689 (is_mve_undefined): Likewise.
690 (is_mve_unpredictable): Likewise.
691 (print_mve_undefined): Likewise.
692 (print_mve_size): Likewise.
693 (print_mve_shift_n): Likewise.
694 (print_insn_mve): Likewise.
696 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
697 Michael Collison <michael.collison@arm.com>
699 * arm-dis.c (enum mve_instructions): Add new instructions.
700 (is_mve_encoding_conflict): Handle new instructions.
701 (is_mve_unpredictable): Likewise.
702 (print_mve_rotate): Likewise.
703 (print_mve_size): Likewise.
704 (print_insn_mve): Likewise.
706 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
707 Michael Collison <michael.collison@arm.com>
709 * arm-dis.c (enum mve_instructions): Add new instructions.
710 (is_mve_encoding_conflict): Handle new instructions.
711 (is_mve_unpredictable): Likewise.
712 (print_mve_size): Likewise.
713 (print_insn_mve): Likewise.
715 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
716 Michael Collison <michael.collison@arm.com>
718 * arm-dis.c (enum mve_instructions): Add new instructions.
719 (enum mve_undefined): Add new reasons.
720 (is_mve_encoding_conflict): Handle new instructions.
721 (is_mve_undefined): Likewise.
722 (is_mve_unpredictable): Likewise.
723 (print_mve_undefined): Likewise.
724 (print_mve_size): Likewise.
725 (print_insn_mve): Likewise.
727 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
728 Michael Collison <michael.collison@arm.com>
730 * arm-dis.c (enum mve_instructions): Add new instructions.
731 (is_mve_encoding_conflict): Handle new instructions.
732 (is_mve_undefined): Likewise.
733 (is_mve_unpredictable): Likewise.
734 (print_mve_size): Likewise.
735 (print_insn_mve): Likewise.
737 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
738 Michael Collison <michael.collison@arm.com>
740 * arm-dis.c (enum mve_instructions): Add new instructions.
741 (enum mve_unpredictable): Add new reasons.
742 (enum mve_undefined): Likewise.
743 (is_mve_okay_in_it): Handle new isntructions.
744 (is_mve_encoding_conflict): Likewise.
745 (is_mve_undefined): Likewise.
746 (is_mve_unpredictable): Likewise.
747 (print_mve_vmov_index): Likewise.
748 (print_simd_imm8): Likewise.
749 (print_mve_undefined): Likewise.
750 (print_mve_unpredictable): Likewise.
751 (print_mve_size): Likewise.
752 (print_insn_mve): Likewise.
754 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
755 Michael Collison <michael.collison@arm.com>
757 * arm-dis.c (enum mve_instructions): Add new instructions.
758 (enum mve_unpredictable): Add new reasons.
759 (enum mve_undefined): Likewise.
760 (is_mve_encoding_conflict): Handle new instructions.
761 (is_mve_undefined): Likewise.
762 (is_mve_unpredictable): Likewise.
763 (print_mve_undefined): Likewise.
764 (print_mve_unpredictable): Likewise.
765 (print_mve_rounding_mode): Likewise.
766 (print_mve_vcvt_size): Likewise.
767 (print_mve_size): Likewise.
768 (print_insn_mve): Likewise.
770 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
771 Michael Collison <michael.collison@arm.com>
773 * arm-dis.c (enum mve_instructions): Add new instructions.
774 (enum mve_unpredictable): Add new reasons.
775 (enum mve_undefined): Likewise.
776 (is_mve_undefined): Handle new instructions.
777 (is_mve_unpredictable): Likewise.
778 (print_mve_undefined): Likewise.
779 (print_mve_unpredictable): Likewise.
780 (print_mve_size): Likewise.
781 (print_insn_mve): Likewise.
783 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
784 Michael Collison <michael.collison@arm.com>
786 * arm-dis.c (enum mve_instructions): Add new instructions.
787 (enum mve_undefined): Add new reasons.
788 (insns): Add new instructions.
789 (is_mve_encoding_conflict):
790 (print_mve_vld_str_addr): New print function.
791 (is_mve_undefined): Handle new instructions.
792 (is_mve_unpredictable): Likewise.
793 (print_mve_undefined): Likewise.
794 (print_mve_size): Likewise.
795 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
796 (print_insn_mve): Handle new operands.
798 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
799 Michael Collison <michael.collison@arm.com>
801 * arm-dis.c (enum mve_instructions): Add new instructions.
802 (enum mve_unpredictable): Add new reasons.
803 (is_mve_encoding_conflict): Handle new instructions.
804 (is_mve_unpredictable): Likewise.
805 (mve_opcodes): Add new instructions.
806 (print_mve_unpredictable): Handle new reasons.
807 (print_mve_register_blocks): New print function.
808 (print_mve_size): Handle new instructions.
809 (print_insn_mve): Likewise.
811 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
812 Michael Collison <michael.collison@arm.com>
814 * arm-dis.c (enum mve_instructions): Add new instructions.
815 (enum mve_unpredictable): Add new reasons.
816 (enum mve_undefined): Likewise.
817 (is_mve_encoding_conflict): Handle new instructions.
818 (is_mve_undefined): Likewise.
819 (is_mve_unpredictable): Likewise.
820 (coprocessor_opcodes): Move NEON VDUP from here...
821 (neon_opcodes): ... to here.
822 (mve_opcodes): Add new instructions.
823 (print_mve_undefined): Handle new reasons.
824 (print_mve_unpredictable): Likewise.
825 (print_mve_size): Handle new instructions.
826 (print_insn_neon): Handle vdup.
827 (print_insn_mve): Handle new operands.
829 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
830 Michael Collison <michael.collison@arm.com>
832 * arm-dis.c (enum mve_instructions): Add new instructions.
833 (enum mve_unpredictable): Add new values.
834 (mve_opcodes): Add new instructions.
835 (vec_condnames): New array with vector conditions.
836 (mve_predicatenames): New array with predicate suffixes.
837 (mve_vec_sizename): New array with vector sizes.
838 (enum vpt_pred_state): New enum with vector predication states.
839 (struct vpt_block): New struct type for vpt blocks.
840 (vpt_block_state): Global struct to keep track of state.
841 (mve_extract_pred_mask): New helper function.
842 (num_instructions_vpt_block): Likewise.
843 (mark_outside_vpt_block): Likewise.
844 (mark_inside_vpt_block): Likewise.
845 (invert_next_predicate_state): Likewise.
846 (update_next_predicate_state): Likewise.
847 (update_vpt_block_state): Likewise.
848 (is_vpt_instruction): Likewise.
849 (is_mve_encoding_conflict): Add entries for new instructions.
850 (is_mve_unpredictable): Likewise.
851 (print_mve_unpredictable): Handle new cases.
852 (print_instruction_predicate): Likewise.
853 (print_mve_size): New function.
854 (print_vec_condition): New function.
855 (print_insn_mve): Handle vpt blocks and new print operands.
857 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
859 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
860 8, 14 and 15 for Armv8.1-M Mainline.
862 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
863 Michael Collison <michael.collison@arm.com>
865 * arm-dis.c (enum mve_instructions): New enum.
866 (enum mve_unpredictable): Likewise.
867 (enum mve_undefined): Likewise.
868 (struct mopcode32): New struct.
869 (is_mve_okay_in_it): New function.
870 (is_mve_architecture): Likewise.
871 (arm_decode_field): Likewise.
872 (arm_decode_field_multiple): Likewise.
873 (is_mve_encoding_conflict): Likewise.
874 (is_mve_undefined): Likewise.
875 (is_mve_unpredictable): Likewise.
876 (print_mve_undefined): Likewise.
877 (print_mve_unpredictable): Likewise.
878 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
879 (print_insn_mve): New function.
880 (print_insn_thumb32): Handle MVE architecture.
881 (select_arm_features): Force thumb for Armv8.1-m Mainline.
883 2019-05-10 Nick Clifton <nickc@redhat.com>
886 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
887 end of the table prematurely.
889 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
891 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
894 2019-05-11 Alan Modra <amodra@gmail.com>
896 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
897 when -Mraw is in effect.
899 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
901 * aarch64-dis-2.c: Regenerate.
902 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
903 (OP_SVE_BBB): New variant set.
904 (OP_SVE_DDDD): New variant set.
905 (OP_SVE_HHH): New variant set.
906 (OP_SVE_HHHU): New variant set.
907 (OP_SVE_SSS): New variant set.
908 (OP_SVE_SSSU): New variant set.
909 (OP_SVE_SHH): New variant set.
910 (OP_SVE_SBBU): New variant set.
911 (OP_SVE_DSS): New variant set.
912 (OP_SVE_DHHU): New variant set.
913 (OP_SVE_VMV_HSD_BHS): New variant set.
914 (OP_SVE_VVU_HSD_BHS): New variant set.
915 (OP_SVE_VVVU_SD_BH): New variant set.
916 (OP_SVE_VVVU_BHSD): New variant set.
917 (OP_SVE_VVV_QHD_DBS): New variant set.
918 (OP_SVE_VVV_HSD_BHS): New variant set.
919 (OP_SVE_VVV_HSD_BHS2): New variant set.
920 (OP_SVE_VVV_BHS_HSD): New variant set.
921 (OP_SVE_VV_BHS_HSD): New variant set.
922 (OP_SVE_VVV_SD): New variant set.
923 (OP_SVE_VVU_BHS_HSD): New variant set.
924 (OP_SVE_VZVV_SD): New variant set.
925 (OP_SVE_VZVV_BH): New variant set.
926 (OP_SVE_VZV_SD): New variant set.
927 (aarch64_opcode_table): Add sve2 instructions.
929 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
931 * aarch64-asm-2.c: Regenerated.
932 * aarch64-dis-2.c: Regenerated.
933 * aarch64-opc-2.c: Regenerated.
934 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
935 for SVE_SHLIMM_UNPRED_22.
936 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
937 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
940 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
942 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
943 sve_size_tsz_bhs iclass encode.
944 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
945 sve_size_tsz_bhs iclass decode.
947 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
949 * aarch64-asm-2.c: Regenerated.
950 * aarch64-dis-2.c: Regenerated.
951 * aarch64-opc-2.c: Regenerated.
952 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
953 for SVE_Zm4_11_INDEX.
954 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
955 (fields): Handle SVE_i2h field.
956 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
957 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
959 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
961 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
962 sve_shift_tsz_bhsd iclass encode.
963 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
964 sve_shift_tsz_bhsd iclass decode.
966 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
968 * aarch64-asm-2.c: Regenerated.
969 * aarch64-dis-2.c: Regenerated.
970 * aarch64-opc-2.c: Regenerated.
971 * aarch64-asm.c (aarch64_ins_sve_shrimm):
972 (aarch64_encode_variant_using_iclass): Handle
973 sve_shift_tsz_hsd iclass encode.
974 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
975 sve_shift_tsz_hsd iclass decode.
976 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
977 for SVE_SHRIMM_UNPRED_22.
978 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
979 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
982 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
984 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
985 sve_size_013 iclass encode.
986 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
987 sve_size_013 iclass decode.
989 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
991 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
992 sve_size_bh iclass encode.
993 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
994 sve_size_bh iclass decode.
996 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
998 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
999 sve_size_sd2 iclass encode.
1000 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1001 sve_size_sd2 iclass decode.
1002 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1003 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1005 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1007 * aarch64-asm-2.c: Regenerated.
1008 * aarch64-dis-2.c: Regenerated.
1009 * aarch64-opc-2.c: Regenerated.
1010 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1012 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1013 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1015 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1017 * aarch64-asm-2.c: Regenerated.
1018 * aarch64-dis-2.c: Regenerated.
1019 * aarch64-opc-2.c: Regenerated.
1020 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1021 for SVE_Zm3_11_INDEX.
1022 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1023 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1024 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1026 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1028 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1030 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1031 sve_size_hsd2 iclass encode.
1032 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1033 sve_size_hsd2 iclass decode.
1034 * aarch64-opc.c (fields): Handle SVE_size field.
1035 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1037 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1039 * aarch64-asm-2.c: Regenerated.
1040 * aarch64-dis-2.c: Regenerated.
1041 * aarch64-opc-2.c: Regenerated.
1042 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1044 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1045 (fields): Handle SVE_rot3 field.
1046 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1047 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1049 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1051 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1054 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1057 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1058 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1059 aarch64_feature_sve2bitperm): New feature sets.
1060 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1061 for feature set addresses.
1062 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1063 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1065 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1066 Faraz Shahbazker <fshahbazker@wavecomp.com>
1068 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1069 argument and set ASE_EVA_R6 appropriately.
1070 (set_default_mips_dis_options): Pass ISA to above.
1071 (parse_mips_dis_option): Likewise.
1072 * mips-opc.c (EVAR6): New macro.
1073 (mips_builtin_opcodes): Add llwpe, scwpe.
1075 2019-05-01 Sudakshina Das <sudi.das@arm.com>
1077 * aarch64-asm-2.c: Regenerated.
1078 * aarch64-dis-2.c: Regenerated.
1079 * aarch64-opc-2.c: Regenerated.
1080 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1081 AARCH64_OPND_TME_UIMM16.
1082 (aarch64_print_operand): Likewise.
1083 * aarch64-tbl.h (QL_IMM_NIL): New.
1086 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1088 2019-04-29 John Darrington <john@darrington.wattle.id.au>
1090 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1092 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1093 Faraz Shahbazker <fshahbazker@wavecomp.com>
1095 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1097 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1099 * s12z-opc.h: Add extern "C" bracketing to help
1100 users who wish to use this interface in c++ code.
1102 2019-04-24 John Darrington <john@darrington.wattle.id.au>
1104 * s12z-opc.c (bm_decode): Handle bit map operations with the
1107 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1109 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1110 specifier. Add entries for VLDR and VSTR of system registers.
1111 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1112 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1113 of %J and %K format specifier.
1115 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1117 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1118 Add new entries for VSCCLRM instruction.
1119 (print_insn_coprocessor): Handle new %C format control code.
1121 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1123 * arm-dis.c (enum isa): New enum.
1124 (struct sopcode32): New structure.
1125 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1126 set isa field of all current entries to ANY.
1127 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1128 Only match an entry if its isa field allows the current mode.
1130 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1132 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1134 (print_insn_thumb32): Add logic to print %n CLRM register list.
1136 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1138 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1141 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1143 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1144 (print_insn_thumb32): Edit the switch case for %Z.
1146 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1148 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1150 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1152 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1154 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1156 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1158 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1160 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1161 Arm register with r13 and r15 unpredictable.
1162 (thumb32_opcodes): New instructions for bfx and bflx.
1164 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1166 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1168 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1170 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1172 2019-04-15 Sudakshina Das <sudi.das@arm.com>
1174 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1176 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1178 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1180 2019-04-12 John Darrington <john@darrington.wattle.id.au>
1182 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1183 "optr". ("operator" is a reserved word in c++).
1185 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1187 * aarch64-opc.c (aarch64_print_operand): Add case for
1189 (verify_constraints): Likewise.
1190 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1191 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1192 to accept Rt|SP as first operand.
1193 (AARCH64_OPERANDS): Add new Rt_SP.
1194 * aarch64-asm-2.c: Regenerated.
1195 * aarch64-dis-2.c: Regenerated.
1196 * aarch64-opc-2.c: Regenerated.
1198 2019-04-11 Sudakshina Das <sudi.das@arm.com>
1200 * aarch64-asm-2.c: Regenerated.
1201 * aarch64-dis-2.c: Likewise.
1202 * aarch64-opc-2.c: Likewise.
1203 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1205 2019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1207 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1209 2019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1211 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1212 * i386-init.h: Regenerated.
1214 2019-04-07 Alan Modra <amodra@gmail.com>
1216 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1217 op_separator to control printing of spaces, comma and parens
1218 rather than need_comma, need_paren and spaces vars.
1220 2019-04-07 Alan Modra <amodra@gmail.com>
1223 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1224 (print_insn_neon, print_insn_arm): Likewise.
1226 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1228 * i386-dis-evex.h (evex_table): Updated to support BF16
1230 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1231 and EVEX_W_0F3872_P_3.
1232 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1233 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1234 * i386-opc.h (enum): Add CpuAVX512_BF16.
1235 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1236 * i386-opc.tbl: Add AVX512 BF16 instructions.
1237 * i386-init.h: Regenerated.
1238 * i386-tbl.h: Likewise.
1240 2019-04-05 Alan Modra <amodra@gmail.com>
1242 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1243 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1244 to favour printing of "-" branch hint when using the "y" bit.
1245 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1247 2019-04-05 Alan Modra <amodra@gmail.com>
1249 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1250 opcode until first operand is output.
1252 2019-04-04 Peter Bergner <bergner@linux.ibm.com>
1255 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1256 (valid_bo_post_v2): Add support for 'at' branch hints.
1257 (insert_bo): Only error on branch on ctr.
1258 (get_bo_hint_mask): New function.
1259 (insert_boe): Add new 'branch_taken' formal argument. Add support
1260 for inserting 'at' branch hints.
1261 (extract_boe): Add new 'branch_taken' formal argument. Add support
1262 for extracting 'at' branch hints.
1263 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1264 (BOE): Delete operand.
1265 (BOM, BOP): New operands.
1267 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1268 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1269 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1270 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1271 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1272 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1273 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1274 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1275 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1276 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1277 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1278 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1279 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1280 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1281 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1282 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1283 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1284 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1285 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1286 bttarl+>: New extended mnemonics.
1288 2019-03-28 Alan Modra <amodra@gmail.com>
1291 * ppc-opc.c (BTF): Define.
1292 (powerpc_opcodes): Use for mtfsb*.
1293 * ppc-dis.c (print_insn_powerpc): Print fields with both
1294 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1296 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1298 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1299 (mapping_symbol_for_insn): Implement new algorithm.
1300 (print_insn): Remove duplicate code.
1302 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1304 * aarch64-dis.c (print_insn_aarch64):
1307 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1309 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1312 2019-03-25 Tamar Christina <tamar.christina@arm.com>
1314 * aarch64-dis.c (last_stop_offset): New.
1315 (print_insn_aarch64): Use stop_offset.
1317 2019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1320 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1322 * i386-init.h: Regenerated.
1324 2019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1327 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1328 vmovdqu16, vmovdqu32 and vmovdqu64.
1329 * i386-tbl.h: Regenerated.
1331 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1333 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1334 from vstrszb, vstrszh, and vstrszf.
1336 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1338 * s390-opc.txt: Add instruction descriptions.
1340 2019-02-08 Jim Wilson <jimw@sifive.com>
1342 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1345 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1347 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1349 2019-02-07 Tamar Christina <tamar.christina@arm.com>
1352 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1353 * aarch64-opc.c (verify_elem_sd): New.
1354 (fields): Add FLD_sz entr.
1355 * aarch64-tbl.h (_SIMD_INSN): New.
1356 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1357 fmulx scalar and vector by element isns.
1359 2019-02-07 Nick Clifton <nickc@redhat.com>
1361 * po/sv.po: Updated Swedish translation.
1363 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1365 * s390-mkopc.c (main): Accept arch13 as cpu string.
1366 * s390-opc.c: Add new instruction formats and instruction opcode
1368 * s390-opc.txt: Add new arch13 instructions.
1370 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1372 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1373 (aarch64_opcode): Change encoding for stg, stzg
1375 * aarch64-asm-2.c: Regenerated.
1376 * aarch64-dis-2.c: Regenerated.
1377 * aarch64-opc-2.c: Regenerated.
1379 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1381 * aarch64-asm-2.c: Regenerated.
1382 * aarch64-dis-2.c: Likewise.
1383 * aarch64-opc-2.c: Likewise.
1384 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1386 2019-01-25 Sudakshina Das <sudi.das@arm.com>
1387 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1389 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1390 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1391 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1392 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1393 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1394 case for ldstgv_indexed.
1395 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1396 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1397 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1398 * aarch64-asm-2.c: Regenerated.
1399 * aarch64-dis-2.c: Regenerated.
1400 * aarch64-opc-2.c: Regenerated.
1402 2019-01-23 Nick Clifton <nickc@redhat.com>
1404 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1406 2019-01-21 Nick Clifton <nickc@redhat.com>
1408 * po/de.po: Updated German translation.
1409 * po/uk.po: Updated Ukranian translation.
1411 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1412 * mips-dis.c (mips_arch_choices): Fix typo in
1413 gs464, gs464e and gs264e descriptors.
1415 2019-01-19 Nick Clifton <nickc@redhat.com>
1417 * configure: Regenerate.
1418 * po/opcodes.pot: Regenerate.
1420 2018-06-24 Nick Clifton <nickc@redhat.com>
1422 2.32 branch created.
1424 2019-01-09 John Darrington <john@darrington.wattle.id.au>
1426 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1428 -dis.c (opr_emit_disassembly): Do not omit an index if it is
1431 2019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1433 * configure: Regenerate.
1435 2019-01-07 Alan Modra <amodra@gmail.com>
1437 * configure: Regenerate.
1438 * po/POTFILES.in: Regenerate.
1440 2019-01-03 John Darrington <john@darrington.wattle.id.au>
1442 * s12z-opc.c: New file.
1443 * s12z-opc.h: New file.
1444 * s12z-dis.c: Removed all code not directly related to display
1445 of instructions. Used the interface provided by the new files
1447 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
1448 * Makefile.in: Regenerate.
1449 * configure.ac (bfd_s12z_arch): Correct the dependencies.
1450 * configure: Regenerate.
1452 2019-01-01 Alan Modra <amodra@gmail.com>
1454 Update year range in copyright notice of all files.
1456 For older changes see ChangeLog-2018
1458 Copyright (C) 2019 Free Software Foundation, Inc.
1460 Copying and distribution of this file, with or without modification,
1461 are permitted in any medium without royalty provided the copyright
1462 notice and this notice are preserved.
1468 version-control: never