1 2014-11-30 Alan Modra <amodra@gmail.com>
3 * ppc-opc.c (powerpc_opcodes): Make mftb* generate mfspr for
6 2014-11-28 Alan Modra <amodra@gmail.com>
8 * ppc-opc.c (powerpc_opcodes <mftb>): Don't deprecate for power7.
10 (insert_tbr, extract_tbr): Validate tbr number.
12 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
14 * i386-dis-evex.c (evex_table): Add vpermi2b, vpermt2b, vpermb,
16 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F3883, EVEX_W_0F3883_P_2.
17 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VBMI_FLAGS.
18 (cpu_flags): Add CpuAVX512VBMI.
19 * i386-opc.h (enum): Add CpuAVX512VBMI.
20 (i386_cpu_flags): Add cpuavx512vbmi.
21 * i386-opc.tbl: Add vpmadd52luq, vpmultishiftqb, vpermb, vpermi2b,
23 * i386-init.h: Regenerated.
24 * i386-tbl.h: Likewise.
26 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
28 * i386-dis-evex.c (evex_table): Add vpmadd52luq, vpmadd52huq.
29 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F38B4,
31 * i386-gen.c (cpu_flag_init): Add CPU_AVX512IFMA_FLAGS.
32 (cpu_flags): Add CpuAVX512IFMA.
33 * i386-opc.h (enum): Add CpuAVX512IFMA.
34 (i386_cpu_flags): Add cpuavx512ifma.
35 * i386-opc.tbl: Add vpmadd52huq, vpmadd52luq.
36 * i386-init.h: Regenerated.
37 * i386-tbl.h: Likewise.
39 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
41 * i386-dis.c (PREFIX enum): Add PREFIX_RM_0_0FAE_REG_7.
42 (prefix_table): Add pcommit.
43 * i386-gen.c (cpu_flag_init): Add CPU_PCOMMIT_FLAGS.
44 (cpu_flags): Add CpuPCOMMIT.
45 * i386-opc.h (enum): Add CpuPCOMMIT.
46 (i386_cpu_flags): Add cpupcommit.
47 * i386-opc.tbl: Add pcommit.
48 * i386-init.h: Regenerated.
49 * i386-tbl.h: Likewise.
51 2014-11-17 Ilya Tocar <ilya.tocar@intel.com>
53 * i386-dis.c (PREFIX enum): Add PREFIX_0FAE_REG_6.
54 (prefix_table): Add clwb.
55 * i386-gen.c (cpu_flag_init): Add CPU_CLWB_FLAGS.
56 (cpu_flags): Add CpuCLWB.
57 * i386-opc.h (enum): Add CpuCLWB.
58 (i386_cpu_flags): Add cpuclwb.
59 * i386-opc.tbl: Add clwb.
60 * i386-init.h: Regenerated.
61 * i386-tbl.h: Likewise.
63 2014-11-03 Nick Clifton <nickc@redhat.com>
65 * po/fi.po: Updated Finnish translation.
67 2014-10-29 Nick Clifton <nickc@redhat.com>
69 * po/de.po: Updated German translation.
71 2014-10-28 Alan Modra <amodra@gmail.com>
74 2014-10-21 Jan Beulich <jbeulich@suse.com>
75 * ppc-opc.c (powerpc_opcodes): Enable msgclr and msgsnd on Power8.
77 2014-10-15 Tristan Gingold <gingold@adacore.com>
79 * configure: Regenerate.
81 2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
83 * sparc-opc.c (sparc-opcodes): Remove instructions `chkpt',
84 `commit', `random', `wr r,r,%cps', `wr r,i,%cps' and `rd %cps,r'.
85 Annotate table with HWCAP2 bits.
86 Add instructions xmontmul, xmontsqr, xmpmul.
87 (sparc-opcodes): Add the `mwait', `wr r,r,%mwait', `wr
88 r,i,%mwait' and `rd %mwait,r' instructions.
89 Add rd/wr instructions for accessing the %mcdper ancillary state
91 (sparc-opcodes): Add sparc5/vis4.0 instructions:
92 subxc, subxccc, fpadd8, fpadds8, fpaddus8, fpaddus16, fpcmple8,
93 fpcmpgt8, fpcmpule16, fpcmpugt16, fpcmpule32, fpcmpugt32, fpmax8,
94 fpmax16, fpmax32, fpmaxu8, fpmaxu16, fpmaxu32, fpmin8, fpmin16,
95 fpmin32, fpminu8, fpminu16, fpminu32, fpsub8, fpsubs8, fpsubus8,
96 fpsubus16, and faligndatai.
97 * sparc-dis.c (v9a_asr_reg_names): Add the %mwait (%asr28)
98 ancillary state register to the table.
99 (print_insn_sparc): Handle the %mcdper ancillary state register.
100 (print_insn_sparc): Handle new operand type '}'.
102 2014-09-22 H.J. Lu <hongjiu.lu@intel.com>
104 * i386-dis.c (MOD_0F20): Removed.
105 (MOD_0F21): Likewise.
106 (MOD_0F22): Likewise.
107 (MOD_0F23): Likewise.
108 (dis386_twobyte): Replace MOD_0F20, MOD_0F21, MOD_0F22 and
109 MOD_0F23 with "movZ".
110 (mod_table): Remove MOD_0F20, MOD_0F21, MOD_0F22 and MOD_0F23.
111 (OP_R): Check mod/rm byte and call OP_E_register.
113 2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
115 * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i,
116 keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2,
117 keyword_aridxi): Add audio ISA extension.
118 (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr,
119 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st,
120 keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope
121 for nds32-dis.c using.
122 (build_opcode_syntax): Remove dead code.
123 (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end,
124 parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr,
125 parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA
127 * nds32-asm.h: Declare.
128 * nds32-dis.c: Use array nds32_opcodes to disassemble instead of
131 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
132 Matthew Fortune <matthew.fortune@imgtec.com>
134 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
136 (parse_mips_dis_option): Allow MSA and virtualization support for
138 (mips_print_arg_state): Add fields dest_regno and seen_dest.
139 (mips_seen_register): New function.
140 (print_insn_arg): Refactored code to use mips_seen_register
141 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
142 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
143 the register rather than aborting.
144 (print_insn_args): Add length argument. Add code to correctly
145 calculate the instruction address for pc relative instructions.
146 (validate_insn_args): New static function.
147 (print_insn_mips): Prevent jalx disassembling for r6. Use
149 (print_insn_micromips): Use validate_insn_args.
150 all the arguments are valid.
151 * mips-formats.h (PREV_CHECK): New define.
152 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
153 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
158 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
159 MIPS R6 instructions from MIPS R2 instructions.
161 2014-09-10 H.J. Lu <hongjiu.lu@intel.com>
163 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
164 (putop): Handle "%LP".
166 2014-09-03 Jiong Wang <jiong.wang@arm.com>
168 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
169 * aarch64-dis-2.c: Update auto-generated file.
171 2014-09-03 Jiong Wang <jiong.wang@arm.com>
173 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
174 (aarch64_feature_lse): New feature added.
176 (aarch64_opcode_table): New LSE instructions added. Improve
177 descriptions for ldarb/ldarh/ldar.
178 (aarch64_opcode_table): Describe PAIRREG.
179 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
180 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
181 (aarch64_print_operand): Recognize PAIRREG.
182 (operand_general_constraint_met_p): Check reg pair constraints for CASP
184 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
185 (do_special_decoding): Recognize F_LSE_SZ.
186 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
188 2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
190 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
191 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
192 "sdbbp", "syscall" and "wait".
194 2014-08-21 Nathan Sidwell <nathan@codesourcery.com>
195 Maciej W. Rozycki <macro@codesourcery.com>
197 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
198 returned if the U bit is set.
200 2014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
202 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
203 48-bit "li" encoding.
205 2014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
207 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
208 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
209 static functions, code was moved from...
210 (print_insn_s390): ...here.
211 (s390_extract_operand): Adjust comment. Change type of first
212 parameter from 'unsigned char *' to 'const bfd_byte *'.
213 (union operand_value): New.
214 (s390_extract_operand): Change return type to union operand_value.
215 Also avoid integer overflow in sign-extension.
216 (s390_print_insn_with_opcode): Adjust to changed return value from
217 s390_extract_operand(). Change "%i" printf format to "%u" for
219 (init_disasm): Simplify initialization of opc_index[]. This also
220 fixes an access after the last element of s390_opcodes[].
221 (print_insn_s390): Simplify the opcode search loop.
222 Check architecture mask against all searched opcodes, not just the
224 (s390_print_insn_with_opcode): Drop function pointer dereferences
226 (print_insn_s390): Likewise.
227 (s390_insn_length): Simplify formula for return value.
228 (s390_print_insn_with_opcode): Avoid special handling for the
229 separator before the first operand. Use new local variable
230 'flags' in place of 'operand->flags'.
232 2014-08-14 Mike Frysinger <vapier@gentoo.org>
234 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
235 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
236 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
237 Change assignment of 1 to priv->comment to TRUE.
238 (print_insn_bfin): Change legal to a bfd_boolean. Change
239 assignment of 0/1 with priv comment and parallel and legal
242 2014-08-14 Mike Frysinger <vapier@gentoo.org>
244 * bfin-dis.c (OUT): Define.
245 (decode_CC2stat_0): Declare new op_names array.
246 Replace multiple if statements with a single one.
248 2014-08-14 Mike Frysinger <vapier@gentoo.org>
250 * bfin-dis.c (struct private): Add iw0.
251 (_print_insn_bfin): Assign iw0 to priv.iw0.
252 (print_insn_bfin): Drop ifetch and use priv.iw0.
254 2014-08-13 Mike Frysinger <vapier@gentoo.org>
256 * bfin-dis.c (comment, parallel): Move from global scope ...
257 (struct private): ... to this new struct.
258 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
259 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
260 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
261 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
262 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
263 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
264 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
265 print_insn_bfin): Declare private struct. Use priv's comment and
268 2014-08-13 Mike Frysinger <vapier@gentoo.org>
270 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
271 (_print_insn_bfin): Add check for unaligned pc.
273 2014-08-13 Mike Frysinger <vapier@gentoo.org>
275 * bfin-dis.c (ifetch): New function.
276 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
279 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
281 * micromips-opc.c (COD): Rename throughout to...
282 (CM): New define, update to use INSN_COPROC_MOVE.
283 (LCD): Rename throughout to...
284 (LC): New define, update to use INSN_LOAD_COPROC.
285 * mips-opc.c: Likewise.
287 2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
289 * micromips-opc.c (COD, LCD) New macros.
290 (cfc1, ctc1): Remove FP_S attribute.
291 (dmfc1, mfc1, mfhc1): Add LCD attribute.
292 (dmtc1, mtc1, mthc1): Add COD attribute.
293 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
295 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
296 Alexander Ivchenko <alexander.ivchenko@intel.com>
297 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
298 Sergey Lega <sergey.s.lega@intel.com>
299 Anna Tikhonova <anna.tikhonova@intel.com>
300 Ilya Tocar <ilya.tocar@intel.com>
301 Andrey Turetskiy <andrey.turetskiy@intel.com>
302 Ilya Verbin <ilya.verbin@intel.com>
303 Kirill Yukhin <kirill.yukhin@intel.com>
304 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
306 * i386-dis-evex.h: Updated.
307 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
308 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
309 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
310 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
312 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
313 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
314 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
315 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
316 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
317 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
318 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
319 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
320 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
321 (prefix_table): Add entries for new instructions.
322 (vex_len_table): Ditto.
323 (vex_w_table): Ditto.
324 (OP_E_memory): Update xmmq_mode handling.
325 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
326 (cpu_flags): Add CpuAVX512DQ.
327 * i386-init.h: Regenerared.
328 * i386-opc.h (CpuAVX512DQ): New.
329 (i386_cpu_flags): Add cpuavx512dq.
330 * i386-opc.tbl: Add AVX512DQ instructions.
331 * i386-tbl.h: Regenerate.
333 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
334 Alexander Ivchenko <alexander.ivchenko@intel.com>
335 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
336 Sergey Lega <sergey.s.lega@intel.com>
337 Anna Tikhonova <anna.tikhonova@intel.com>
338 Ilya Tocar <ilya.tocar@intel.com>
339 Andrey Turetskiy <andrey.turetskiy@intel.com>
340 Ilya Verbin <ilya.verbin@intel.com>
341 Kirill Yukhin <kirill.yukhin@intel.com>
342 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
344 * i386-dis-evex.h: Add new instructions (prefixes bellow).
345 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
346 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
347 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
348 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
349 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
350 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
351 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
352 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
353 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
354 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
355 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
356 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
357 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
358 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
359 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
360 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
361 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
362 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
363 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
364 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
365 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
366 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
367 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
368 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
369 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
370 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
371 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
372 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
373 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
374 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
375 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
376 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
377 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
378 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
379 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
380 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
381 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
382 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
383 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
384 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
385 (prefix_table): Add entries for new instructions.
387 (vex_len_table): Ditto.
388 (vex_w_table): Ditto.
389 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
390 mask_bd_mode handling.
391 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
393 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
395 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
396 (OP_EX): Add dqw_swap_mode handling.
397 (OP_VEX): Add mask_bd_mode handling.
398 (OP_Mask): Add mask_bd_mode handling.
399 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
400 (cpu_flags): Add CpuAVX512BW.
401 * i386-init.h: Regenerated.
402 * i386-opc.h (CpuAVX512BW): New.
403 (i386_cpu_flags): Add cpuavx512bw.
404 * i386-opc.tbl: Add AVX512BW instructions.
405 * i386-tbl.h: Regenerate.
407 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
408 Alexander Ivchenko <alexander.ivchenko@intel.com>
409 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
410 Sergey Lega <sergey.s.lega@intel.com>
411 Anna Tikhonova <anna.tikhonova@intel.com>
412 Ilya Tocar <ilya.tocar@intel.com>
413 Andrey Turetskiy <andrey.turetskiy@intel.com>
414 Ilya Verbin <ilya.verbin@intel.com>
415 Kirill Yukhin <kirill.yukhin@intel.com>
416 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
418 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
419 * i386-tbl.h: Regenerate.
421 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
422 Alexander Ivchenko <alexander.ivchenko@intel.com>
423 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
424 Sergey Lega <sergey.s.lega@intel.com>
425 Anna Tikhonova <anna.tikhonova@intel.com>
426 Ilya Tocar <ilya.tocar@intel.com>
427 Andrey Turetskiy <andrey.turetskiy@intel.com>
428 Ilya Verbin <ilya.verbin@intel.com>
429 Kirill Yukhin <kirill.yukhin@intel.com>
430 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
432 * i386-dis.c (intel_operand_size): Support 128/256 length in
433 vex_vsib_q_w_dq_mode.
434 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
435 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
436 (cpu_flags): Add CpuAVX512VL.
437 * i386-init.h: Regenerated.
438 * i386-opc.h (CpuAVX512VL): New.
439 (i386_cpu_flags): Add cpuavx512vl.
440 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
441 * i386-opc.tbl: Add AVX512VL instructions.
442 * i386-tbl.h: Regenerate.
444 2014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
446 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
447 * or1k-opinst.c: Regenerate.
449 2014-07-08 Ilya Tocar <ilya.tocar@intel.com>
451 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
452 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
454 2014-07-04 Alan Modra <amodra@gmail.com>
456 * configure.ac: Rename from configure.in.
457 * Makefile.in: Regenerate.
458 * config.in: Regenerate.
460 2014-07-04 Alan Modra <amodra@gmail.com>
462 * configure.in: Include bfd/version.m4.
463 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
464 (BFD_VERSION): Delete.
465 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
466 * configure: Regenerate.
467 * Makefile.in: Regenerate.
469 2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
470 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
471 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
472 Soundararajan <Sounderarajan.D@atmel.com>
474 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
475 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
476 machine is not avrtiny.
478 2014-06-26 Philippe De Muyter <phdm@macqel.be>
480 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
483 2014-06-12 Alan Modra <amodra@gmail.com>
485 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
486 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
488 2014-06-10 H.J. Lu <hongjiu.lu@intel.com>
490 * i386-dis.c (fwait_prefix): New.
491 (ckprefix): Set fwait_prefix.
492 (print_insn): Properly print prefixes before fwait.
494 2014-06-07 Alan Modra <amodra@gmail.com>
496 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
498 2014-06-05 Joel Brobecker <brobecker@adacore.com>
500 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
501 bfd's development.sh.
502 * Makefile.in, configure: Regenerate.
504 2014-06-03 Nick Clifton <nickc@redhat.com>
506 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
507 decide when extended addressing is being used.
509 2014-06-02 Eric Botcazou <ebotcazou@adacore.com>
511 * sparc-opc.c (cas): Disable for LEON.
514 2014-05-20 Alan Modra <amodra@gmail.com>
516 * m68k-dis.c: Don't include setjmp.h.
518 2014-05-09 H.J. Lu <hongjiu.lu@intel.com>
520 * i386-dis.c (ADDR16_PREFIX): Removed.
521 (ADDR32_PREFIX): Likewise.
522 (DATA16_PREFIX): Likewise.
523 (DATA32_PREFIX): Likewise.
524 (prefix_name): Updated.
525 (print_insn): Simplify data and address size prefixes processing.
527 2014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
529 * or1k-desc.c: Regenerated.
530 * or1k-desc.h: Likewise.
531 * or1k-opc.c: Likewise.
532 * or1k-opc.h: Likewise.
533 * or1k-opinst.c: Likewise.
535 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
537 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
542 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
544 (parse_mips_dis_option): Update MSA and virtualization support to
545 allow mips64r3 and mips64r5.
547 2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
549 * mips-opc.c (G3): Remove I4.
551 2014-05-05 H.J. Lu <hongjiu.lu@intel.com>
554 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
555 (end_codep): Likewise.
556 (mandatory_prefix): Likewise.
557 (active_seg_prefix): Likewise.
558 (ckprefix): Set active_seg_prefix to the active segment register
560 (seg_prefix): Removed.
561 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
562 for prefix index. Ignore the index if it is invalid and the
563 mandatory prefix isn't required.
564 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
565 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
566 in used_prefixes here. Don't print unused prefixes. Check
567 active_seg_prefix for the active segment register prefix.
568 Restore the DFLAG bit in sizeflag if the data size prefix is
569 unused. Check the unused mandatory PREFIX_XXX prefixes
570 (append_seg): Only print the segment register which gets used.
571 (OP_E_memory): Check active_seg_prefix for the segment register
574 (OP_OFF64): Likewise.
575 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
577 2014-05-02 H.J. Lu <hongjiu.lu@intel.com>
580 * config.in: Regenerated.
581 * configure: Likewise.
582 * configure.in: Check if sigsetjmp is available.
583 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
584 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
585 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
586 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
587 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
588 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
589 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
590 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
591 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
592 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
593 (OPCODES_SIGSETJMP): Likewise.
594 (OPCODES_SIGLONGJMP): Likewise.
595 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
596 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
597 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
598 * xtensa-dis.c (dis_private): Replace jmp_buf with
600 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
601 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
602 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
603 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
604 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
606 2014-05-01 H.J. Lu <hongjiu.lu@intel.com>
609 * i386-dis.c (print_insn): Handle prefixes before fwait.
611 2014-04-26 Alan Modra <amodra@gmail.com>
613 * po/POTFILES.in: Regenerate.
615 2014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
617 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
618 to allow the MIPS XPA ASE.
619 (parse_mips_dis_option): Process the -Mxpa option.
620 * mips-opc.c (XPA): New define.
621 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
622 locations of the ctc0 and cfc0 instructions.
624 2014-04-22 Christian Svensson <blue@cmd.nu>
626 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
627 * configure.in: Likewise.
628 * disassemble.c: Likewise.
629 * or1k-asm.c: New file.
630 * or1k-desc.c: New file.
631 * or1k-desc.h: New file.
632 * or1k-dis.c: New file.
633 * or1k-ibld.c: New file.
634 * or1k-opc.c: New file.
635 * or1k-opc.h: New file.
636 * or1k-opinst.c: New file.
637 * Makefile.in: Regenerate.
638 * configure: Regenerate.
639 * openrisc-asm.c: Delete.
640 * openrisc-desc.c: Delete.
641 * openrisc-desc.h: Delete.
642 * openrisc-dis.c: Delete.
643 * openrisc-ibld.c: Delete.
644 * openrisc-opc.c: Delete.
645 * openrisc-opc.h: Delete.
646 * or32-dis.c: Delete.
647 * or32-opc.c: Delete.
649 2014-04-04 Ilya Tocar <ilya.tocar@intel.com>
651 * i386-dis.c (rm_table): Add encls, enclu.
652 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
653 (cpu_flags): Add CpuSE1.
654 * i386-opc.h (enum): Add CpuSE1.
655 (i386_cpu_flags): Add cpuse1.
656 * i386-opc.tbl: Add encls, enclu.
657 * i386-init.h: Regenerated.
658 * i386-tbl.h: Likewise.
660 2014-04-02 Anthony Green <green@moxielogic.com>
662 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
663 instructions, sex.b and sex.s.
665 2014-03-26 Jiong Wang <jiong.wang@arm.com>
667 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
670 2014-03-20 Ilya Tocar <ilya.tocar@intel.com>
672 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
673 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
675 * i386-tbl.h: Regenerate.
677 2014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
679 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
680 %hstick_enable added.
682 2014-03-19 Nick Clifton <nickc@redhat.com>
684 * rx-decode.opc (bwl): Allow for bogus instructions with a size
686 (sbwl, ubwl, SCALE): Likewise.
687 * rx-decode.c: Regenerate.
689 2014-03-12 Alan Modra <amodra@gmail.com>
691 * Makefile.in: Regenerate.
693 2014-03-05 Alan Modra <amodra@gmail.com>
695 Update copyright years.
697 2014-03-04 Heiher <r@hev.cc>
699 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
701 2014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
703 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
704 so that they come after the Loongson extensions.
706 2014-03-03 Alan Modra <amodra@gmail.com>
708 * i386-gen.c (process_copyright): Emit copyright notice on one line.
710 2014-02-28 Alan Modra <amodra@gmail.com>
712 * msp430-decode.c: Regenerate.
714 2014-02-27 Jiong Wang <jiong.wang@arm.com>
716 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
717 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
719 2014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
721 * aarch64-opc.c (print_register_offset_address): Call
722 get_int_reg_name to prepare the register name.
724 2014-02-25 Ilya Tocar <ilya.tocar@intel.com>
726 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
727 * i386-tbl.h: Regenerate.
729 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
731 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
732 (cpu_flags): Add CpuPREFETCHWT1.
733 * i386-init.h: Regenerate.
734 * i386-opc.h (CpuPREFETCHWT1): New.
735 (i386_cpu_flags): Add cpuprefetchwt1.
736 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
737 * i386-tbl.h: Regenerate.
739 2014-02-20 Ilya Tocar <ilya.tocar@intel.com>
741 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
743 * i386-tbl.h: Regenerate.
745 2014-02-19 H.J. Lu <hongjiu.lu@intel.com>
747 * i386-gen.c (output_cpu_flags): Don't output trailing space.
748 (output_opcode_modifier): Likewise.
749 (output_operand_type): Likewise.
750 * i386-init.h: Regenerated.
751 * i386-tbl.h: Likewise.
753 2014-02-12 Ilya Tocar <ilya.tocar@intel.com>
755 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
757 (PREFIX enum): Add PREFIX_0FAE_REG_7.
758 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
759 (prefix_table): Add clflusopt.
760 (mod_table): Add xrstors, xsavec, xsaves.
761 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
762 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
763 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
764 * i386-init.h: Regenerate.
765 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
766 xsaves64, xsavec, xsavec64.
767 * i386-tbl.h: Regenerate.
769 2014-02-10 Alan Modra <amodra@gmail.com>
771 * po/POTFILES.in: Regenerate.
772 * po/opcodes.pot: Regenerate.
774 2014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
775 Jan Beulich <jbeulich@suse.com>
778 * i386-dis.c (OP_E_memory): Fix shift computation for
779 vex_vsib_q_w_dq_mode.
781 2014-01-09 Bradley Nelson <bradnelson@google.com>
782 Roland McGrath <mcgrathr@google.com>
784 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
785 last_rex_prefix is -1.
787 2014-01-08 H.J. Lu <hongjiu.lu@intel.com>
789 * i386-gen.c (process_copyright): Update copyright year to 2014.
791 2014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
793 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
795 For older changes see ChangeLog-2013
797 Copyright (C) 2014 Free Software Foundation, Inc.
799 Copying and distribution of this file, with or without modification,
800 are permitted in any medium without royalty provided the copyright
801 notice and this notice are preserved.
807 version-control: never