1 2010-12-09 Mike Frysinger <vapier@gentoo.org>
3 * .gitignore: New file.
5 2010-11-25 Alan Modra <amodra@gmail.com>
10 * po/zh_CN.po: Update.
12 2010-11-11 Mingming Sun <mingm.sun@gmail.com>
14 * mips-dis.c (mips_arch_choices): Add loongson3a.
15 * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A.
16 (mips_builtin_opcodes): Modify some instructions' membership from
19 2010-11-10 Nick Clifton <nickc@redhat.com>
21 * po/fi.po: Updated Finnish translation.
23 2010-11-05 Tristan Gingold <gingold@adacore.com>
25 * po/opcodes.pot: Regenerate
27 2010-10-28 Maciej W. Rozycki <macro@codesourcery.com>
29 * mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".
31 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
33 * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.
35 2010-10-25 Chao-ying Fu <fu@mips.com>
37 * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.
39 2010-10-25 Nathan Sidwell <nathan@codesourcery.com>
41 * tic6x-dis.c: Add attribution.
43 2010-10-22 Alan Modra <amodra@gmail.com>
45 * Makefile.am (CLEANFILES): Add stamp-lm32. Sort.
46 * Makefile.in: Regenerate.
48 2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
50 * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
51 macros before their corresponding MIPS III hardware instructions.
53 2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
55 * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
57 * i386-init.h: Regenerated.
59 2010-10-15 Mike Frysinger <vapier@gentoo.org>
61 * bfin-dis.c (decode_dsp32alu_0): Call imm5d() for BYTEOP2M.
63 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
65 * i386-opc.tbl: Remove CheckRegSize from movq.
66 * i386-tbl.h: Regenerated.
68 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
70 * i386-opc.tbl: Remove CheckRegSize from instructions with
71 0, 1 or fixed operands.
72 * i386-tbl.h: Regenerated.
74 2010-10-14 H.J. Lu <hongjiu.lu@intel.com>
76 * i386-gen.c (opcode_modifiers): Add CheckRegSize.
78 * i386-opc.h (CheckRegSize): New.
79 (i386_opcode_modifier): Add checkregsize.
81 * i386-opc.tbl: Add CheckRegSize to instructions which
82 require register size check.
83 * i386-tbl.h: Regenerated.
85 2010-10-12 Andreas Schwab <schwab@linux-m68k.org>
87 * m68k-opc.c (m68k_opcodes): Move fnop before fbf.
89 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
91 * s390-opc.c: Make the instruction masks for the load/store on
92 condition instructions to cover the condition code mask as well.
93 * s390-opc.txt: lgoc -> locg and stgoc -> stocg.
95 2010-10-11 Jan Kratochvil <jan.kratochvil@redhat.com>
96 Jiang Jilin <freephp@gmail.com>
98 * Makefile.am (libopcodes_a_SOURCES): New as empty.
99 * Makefile.in: Regenerate.
101 2010-10-09 Matt Rice <ratmice@gmail.com>
103 * fr30-desc.h: Regenerate.
104 * frv-desc.h: Regenerate.
105 * ip2k-desc.h: Regenerate.
106 * iq2000-desc.h: Regenerate.
107 * lm32-desc.h: Regenerate.
108 * m32c-desc.h: Regenerate.
109 * m32r-desc.h: Regenerate.
110 * mep-desc.h: Regenerate.
111 * mep-opc.c: Regenerate.
112 * mt-desc.h: Regenerate.
113 * openrisc-desc.h: Regenerate.
114 * xc16x-desc.h: Regenerate.
115 * xstormy16-desc.h: Regenerate.
117 2010-10-08 Pierre Muller <muller@ics.u-strasbg.fr>
119 Fix build with -DDEBUG=7
120 * frv-opc.c: Regenerate.
121 * or32-dis.c (DEBUG): Don't redefine.
122 (find_bytes_big, or32_extract, or32_opcode_match, or32_print_register):
123 Adapt DEBUG code to some type changes throughout.
124 * or32-opc.c (or32_extract): Likewise.
126 2010-10-07 Bernd Schmidt <bernds@codesourcery.com>
128 * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field
129 in SPKERNEL instructions.
131 2010-10-02 H.J. Lu <hongjiu.lu@intel.com>
134 * i386-dis.c (RMAL): Remove duplicate.
136 2010-09-30 Pierre Muller <muller@ics.u-strasbg.fr>
138 * s390-mkopc.c (main): Exit with error 1 if sscanf fails
139 to parse all 6 parameters.
141 2010-09-28 Pierre Muller <muller@ics.u-strasbg.fr>
143 * s390-mkopc.c (main): Change description array size to 80.
144 Add maximum length of 79 to description parsing.
146 2010-09-27 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
148 * configure: Regenerate.
150 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
152 * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196.
153 (main): Recognize the new CPU string.
154 * s390-opc.c: Add new instruction formats and masks.
155 * s390-opc.txt: Add new z196 instructions.
157 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
159 * s390-dis.c (print_insn_s390): Pick instruction with most
161 * s390-opc.c: Add unused bits to the insn mask.
162 * s390-opc.txt: Reorder some instructions to prefer more recent
165 2010-09-27 Tejas Belagod <tejas.belagod@arm.com>
167 * arm_dis.c (print_insn_coprocessor): Apply off-by-alignment
168 correction to unaligned PCs while printing comment.
170 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
172 * arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support.
173 (thumb32_opcodes): Likewise.
174 (banked_regname): New function.
175 (print_insn_arm): Add Virtualization Extensions support.
176 (print_insn_thumb32): Likewise.
178 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
180 * arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in
183 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
185 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
186 (thumb32_opcodes): Likewise.
188 2010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
190 * arm-dis.c (arm_opcodes): Add support for pldw.
191 (thumb32_opcodes): Likewise.
193 2010-09-22 Robin Getz <robin.getz@analog.com>
195 * bfin-dis.c (fmtconst): Cast address to 32bits.
197 2010-09-22 Mike Frysinger <vapier@gentoo.org>
199 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
201 2010-09-22 Robin Getz <robin.getz@analog.com>
203 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
204 Reject P6/P7 to TESTSET.
205 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
207 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
208 P/D fields match all the time.
209 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
210 are 0 for accumulator compares.
211 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
212 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
213 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
214 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
215 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
216 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
218 (decode_dagMODim_0): Verify br field for IREG ops.
219 (decode_LDST_0): Reject preg load into same preg.
220 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
221 (print_insn_bfin): Likewise.
223 2010-09-22 Mike Frysinger <vapier@gentoo.org>
225 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
227 2010-09-22 Robin Getz <robin.getz@analog.com>
229 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
231 2010-09-22 Mike Frysinger <vapier@gentoo.org>
233 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
235 2010-09-22 Robin Getz <robin.getz@analog.com>
237 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
238 register values greater than 8.
239 (IS_RESERVEDREG, allreg, mostreg): New helpers.
240 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
241 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
242 (decode_CC2dreg_0): Check valid CC register number.
244 2010-09-22 Robin Getz <robin.getz@analog.com>
246 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
248 2010-09-22 Robin Getz <robin.getz@analog.com>
250 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
251 (reg_names): Likewise.
252 (decode_statbits): Likewise; while reformatting to make manageable.
254 2010-09-22 Mike Frysinger <vapier@gentoo.org>
256 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
257 (decode_pseudoOChar_0): New function.
258 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
260 2010-09-22 Robin Getz <robin.getz@analog.com>
262 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
263 LSHIFT instead of SHIFT.
265 2010-09-22 Mike Frysinger <vapier@gentoo.org>
267 * bfin-dis.c (constant_formats): Constify the whole structure.
268 (fmtconst): Add const to return value.
269 (reg_names): Mark const.
270 (decode_multfunc): Mark s0/s1 as const.
271 (decode_macfunc): Mark a/sop as const.
273 2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
275 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
277 2010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
279 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
280 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
282 2010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
284 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
287 2010-08-31 H.J. Lu <hongjiu.lu@intel.com>
290 * i386-dis.c (sIv): New.
291 (dis386): Replace Iq with sIv on "pushT".
292 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
293 (x86_64_table): Replace {T|}/{P|} with P.
294 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
295 (OP_sI): Update v_mode. Remove w_mode.
297 2010-08-27 Nathan Froyd <froydnj@codesourcery.com>
299 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
302 2010-08-17 H.J. Lu <hongjiu.lu@intel.com>
304 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
307 2010-08-06 Quentin Neill <quentin.neill@amd.com>
309 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
310 to processor flags for PENTIUMPRO processors and later.
311 * i386-opc.h (enum): Add CpuNop.
312 (i386_cpu_flags): Add cpunop bit.
313 * i386-opc.tbl: Change nop cpu_flags.
314 * i386-init.h: Regenerated.
315 * i386-tbl.h: Likewise.
317 2010-08-06 Quentin Neill <quentin.neill@amd.com>
319 * i386-opc.h (enum): Fix typos in comments.
321 2010-08-06 Alan Modra <amodra@gmail.com>
323 * disassemble.c: Formatting.
324 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
326 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
328 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
329 * i386-tbl.h: Regenerated.
331 2010-08-05 H.J. Lu <hongjiu.lu@intel.com>
333 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
335 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
336 * i386-tbl.h: Regenerated.
338 2010-07-29 DJ Delorie <dj@redhat.com>
340 * rx-decode.opc (SRR): New.
341 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
342 r0,r0) and NOP3 (max r0,r0) special cases.
343 * rx-decode.c: Regenerate.
345 2010-07-28 H.J. Lu <hongjiu.lu@intel.com>
347 * i386-dis.c: Add 0F to VEX opcode enums.
349 2010-07-27 DJ Delorie <dj@redhat.com>
351 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
352 (rx_decode_opcode): Likewise.
353 * rx-decode.c: Regenerate.
355 2010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
356 Ina Pandit <ina.pandit@kpitcummins.com>
358 * v850-dis.c (v850_sreg_names): Updated structure for system
360 (float_cc_names): new structure for condition codes.
361 (print_value): Update the function that prints value.
362 (get_operand_value): New function to get the operand value.
363 (disassemble): Updated to handle the disassembly of instructions.
364 (print_insn_v850): Updated function to print instruction for different
366 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
367 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
368 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
369 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
370 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
371 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
372 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
373 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
374 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
375 (v850_operands): Update with the relocation name. Also update
376 the instructions with specific set of processors.
378 2010-07-08 Tejas Belagod <tejas.belagod@arm.com>
380 * arm-dis.c (print_insn_arm): Add cases for printing more
382 (print_insn_thumb32): Likewise.
384 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
386 * mips-dis.c (print_insn_mips): Correct branch instruction type
389 2010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
391 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
392 type and delay slot determination.
393 (print_insn_mips16): Extend branch instruction type and delay
394 slot determination to cover all instructions.
395 * mips16-opc.c (BR): Remove macro.
396 (UBR, CBR): New macros.
397 (mips16_opcodes): Update branch annotation for "b", "beqz",
398 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
401 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
403 AVX Programming Reference (June, 2010)
404 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
405 * i386-opc.tbl: Likewise.
406 * i386-tbl.h: Regenerated.
408 2010-07-05 H.J. Lu <hongjiu.lu@intel.com>
410 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
412 2010-07-03 Andreas Schwab <schwab@linux-m68k.org>
414 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
415 ppc_cpu_t before inverting.
416 (ppc_parse_cpu): Likewise.
417 (print_insn_powerpc): Likewise.
419 2010-07-03 Alan Modra <amodra@gmail.com>
421 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
422 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
423 (PPC64, MFDEC2): Update.
424 (NON32, NO371): Define.
425 (powerpc_opcode): Update to not use old opcode flags, and avoid
428 2010-07-03 DJ Delorie <dj@delorie.com>
430 * m32c-ibld.c: Regenerate.
432 2010-07-03 Alan Modra <amodra@gmail.com>
434 * ppc-opc.c (PWR2COM): Define.
435 (PPCPWR2): Add PPC_OPCODE_COMMON.
436 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
437 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
440 2010-07-01 H.J. Lu <hongjiu.lu@intel.com>
442 AVX Programming Reference (June, 2010)
443 * i386-dis.c (PREFIX_0FAE_REG_0): New.
444 (PREFIX_0FAE_REG_1): Likewise.
445 (PREFIX_0FAE_REG_2): Likewise.
446 (PREFIX_0FAE_REG_3): Likewise.
447 (PREFIX_VEX_3813): Likewise.
448 (PREFIX_VEX_3A1D): Likewise.
449 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
450 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
452 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
453 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
454 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
456 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
457 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
458 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
460 * i386-opc.h (CpuXsaveopt): New.
461 (CpuFSGSBase): Likewise.
462 (CpuRdRnd): Likewise.
464 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
467 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
468 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
469 * i386-init.h: Regenerated.
470 * i386-tbl.h: Likewise.
472 2010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
474 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
477 2010-06-29 Alan Modra <amodra@gmail.com>
479 * maxq-dis.c: Delete file.
480 * Makefile.am: Remove references to maxq.
481 * configure.in: Likewise.
482 * disassemble.c: Likewise.
483 * Makefile.in: Regenerate.
484 * configure: Regenerate.
485 * po/POTFILES.in: Regenerate.
487 2010-06-29 Alan Modra <amodra@gmail.com>
489 * mep-dis.c: Regenerate.
491 2010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
493 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
495 2010-06-27 Alan Modra <amodra@gmail.com>
497 * arc-dis.c (arc_sprintf): Delete set but unused variables.
498 (decodeInstr): Likewise.
499 * dlx-dis.c (print_insn_dlx): Likewise.
500 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
501 * maxq-dis.c (check_move, print_insn): Likewise.
502 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
503 * msp430-dis.c (msp430_branchinstr): Likewise.
504 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
505 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
506 * sparc-dis.c (print_insn_sparc): Likewise.
507 * fr30-asm.c: Regenerate.
508 * frv-asm.c: Regenerate.
509 * ip2k-asm.c: Regenerate.
510 * iq2000-asm.c: Regenerate.
511 * lm32-asm.c: Regenerate.
512 * m32c-asm.c: Regenerate.
513 * m32r-asm.c: Regenerate.
514 * mep-asm.c: Regenerate.
515 * mt-asm.c: Regenerate.
516 * openrisc-asm.c: Regenerate.
517 * xc16x-asm.c: Regenerate.
518 * xstormy16-asm.c: Regenerate.
520 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
523 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
525 2010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
528 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
530 2010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
532 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
533 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
534 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
535 touch floating point regs and are enabled by COM, PPC or PPCCOM.
536 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
537 Treat lwsync as msync on e500.
539 2010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
541 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
543 2010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
545 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
546 constants is the same on 32-bit and 64-bit hosts.
548 2010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
550 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
551 .short directives so that they can be reassembled.
553 2010-05-26 Catherine Moore <clm@codesourcery.com>
554 David Ung <davidu@mips.com>
556 * mips-opc.c: Change membership to I1 for instructions ssnop and
559 2010-05-26 H.J. Lu <hongjiu.lu@intel.com>
561 * i386-dis.c (sib): New.
563 (print_insn): Call get_sib.
564 OP_E_memory): Use sib.
566 2010-05-26 Catherine Moore <clm@codesoourcery.com>
568 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
569 * mips-opc.c (I16): Remove.
570 (mips_builtin_op): Reclassify jalx.
572 2010-05-19 Alan Modra <amodra@gmail.com>
574 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
575 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
577 2010-05-13 Alan Modra <amodra@gmail.com>
579 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
581 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
583 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
585 (print_insn_thumb16): Add support for new %W format.
587 2010-05-07 Tristan Gingold <gingold@adacore.com>
589 * Makefile.in: Regenerate with automake 1.11.1.
592 2010-05-05 Nick Clifton <nickc@redhat.com>
594 * po/es.po: Updated Spanish translation.
596 2010-04-22 Nick Clifton <nickc@redhat.com>
598 * po/opcodes.pot: Updated by the Translation project.
599 * po/vi.po: Updated Vietnamese translation.
601 2010-04-16 H.J. Lu <hongjiu.lu@intel.com>
603 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
606 2010-04-09 Nick Clifton <nickc@redhat.com>
608 * i386-dis.c (print_insn): Remove unused variable op.
609 (OP_sI): Remove unused variable mask.
611 2010-04-07 Alan Modra <amodra@gmail.com>
613 * configure: Regenerate.
615 2010-04-06 Peter Bergner <bergner@vnet.ibm.com>
617 * ppc-opc.c (RBOPT): New define.
618 ("dccci"): Enable for PPCA2. Make operands optional.
619 ("iccci"): Likewise. Do not deprecate for PPC476.
621 2010-04-02 Masaki Muranaka <monaka@monami-software.com>
623 * cr16-opc.c (cr16_instruction): Fix typo in comment.
625 2010-03-25 Joseph Myers <joseph@codesourcery.com>
627 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
628 * Makefile.in: Regenerate.
629 * configure.in (bfd_tic6x_arch): New.
630 * configure: Regenerate.
631 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
632 (disassembler): Handle TI C6X.
635 2010-03-24 Mike Frysinger <vapier@gentoo.org>
637 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
639 2010-03-23 Joseph Myers <joseph@codesourcery.com>
641 * dis-buf.c (buffer_read_memory): Give error for reading just
642 before the start of memory.
644 2010-03-22 Sebastian Pop <sebastian.pop@amd.com>
645 Quentin Neill <quentin.neill@amd.com>
647 * i386-dis.c (OP_LWP_I): Removed.
648 (reg_table): Do not use OP_LWP_I, use Iq.
649 (OP_LWPCB_E): Remove use of names16.
651 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
652 should not set the Vex.length bit.
653 * i386-tbl.h: Regenerated.
655 2010-02-25 Edmar Wienskoski <edmar@freescale.com>
657 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
659 2010-02-24 Nick Clifton <nickc@redhat.com>
662 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
663 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
664 (thumb32_opcodes): Likewise.
666 2010-02-15 Nick Clifton <nickc@redhat.com>
668 * po/vi.po: Updated Vietnamese translation.
670 2010-02-12 Doug Evans <dje@sebabeach.org>
672 * lm32-opinst.c: Regenerate.
674 2010-02-11 Doug Evans <dje@sebabeach.org>
676 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
677 (print_address): Delete CGEN_PRINT_ADDRESS.
678 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
679 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
680 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
681 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
683 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
684 * frv-desc.c, * frv-desc.h, * frv-opc.c,
685 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
686 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
687 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
688 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
689 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
690 * mep-desc.c, * mep-desc.h, * mep-opc.c,
691 * mt-desc.c, * mt-desc.h, * mt-opc.c,
692 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
693 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
694 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
696 2010-02-11 H.J. Lu <hongjiu.lu@intel.com>
698 * i386-dis.c: Update copyright.
699 * i386-gen.c: Likewise.
700 * i386-opc.h: Likewise.
701 * i386-opc.tbl: Likewise.
703 2010-02-10 Quentin Neill <quentin.neill@amd.com>
704 Sebastian Pop <sebastian.pop@amd.com>
706 * i386-dis.c (OP_EX_VexImmW): Reintroduced
707 function to handle 5th imm8 operand.
708 (PREFIX_VEX_3A48): Added.
709 (PREFIX_VEX_3A49): Added.
710 (VEX_W_3A48_P_2): Added.
711 (VEX_W_3A49_P_2): Added.
712 (prefix table): Added entries for PREFIX_VEX_3A48
714 (vex table): Added entries for VEX_W_3A48_P_2 and
716 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
717 for Vec_Imm4 operands.
718 * i386-opc.h (enum): Added Vec_Imm4.
719 (i386_operand_type): Added vec_imm4.
720 * i386-opc.tbl: Add entries for vpermilp[ds].
721 * i386-init.h: Regenerated.
722 * i386-tbl.h: Regenerated.
724 2010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
726 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
727 and "pwr7". Move "a2" into alphabetical order.
729 2010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
731 * ppc-dis.c (ppc_opts): Add titan entry.
732 * ppc-opc.c (TITAN, MULHW): Define.
733 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
735 2010-02-03 Quentin Neill <quentin.neill@amd.com>
737 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
739 * i386-init.h: Regenerated.
741 2010-02-03 Anthony Green <green@moxielogic.com>
743 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
744 0x0f, and make 0x00 an illegal instruction.
746 2010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
748 * opcodes/arm-dis.c (struct arm_private_data): New.
749 (print_insn_coprocessor, print_insn_arm): Update to use struct
751 (is_mapping_symbol, get_map_sym_type): New functions.
752 (get_sym_code_type): Check the symbol's section. Do not check
754 (print_insn): Default to disassembling ARM mode code. Check
755 for mapping symbols separately from other symbols. Use
756 struct arm_private_data.
758 2010-01-28 H.J. Lu <hongjiu.lu@intel.com>
760 * i386-dis.c (EXVexWdqScalar): New.
761 (vex_scalar_w_dq_mode): Likewise.
762 (prefix_table): Update entries for PREFIX_VEX_3899,
763 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
764 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
765 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
766 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
767 (intel_operand_size): Handle vex_scalar_w_dq_mode.
770 2010-01-27 H.J. Lu <hongjiu.lu@intel.com>
772 * i386-dis.c (XMScalar): New.
773 (EXdScalar): Likewise.
774 (EXqScalar): Likewise.
775 (EXqScalarS): Likewise.
776 (VexScalar): Likewise.
777 (EXdVexScalarS): Likewise.
778 (EXqVexScalarS): Likewise.
779 (XMVexScalar): Likewise.
780 (scalar_mode): Likewise.
781 (d_scalar_mode): Likewise.
782 (d_scalar_swap_mode): Likewise.
783 (q_scalar_mode): Likewise.
784 (q_scalar_swap_mode): Likewise.
785 (vex_scalar_mode): Likewise.
786 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
787 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
788 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
789 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
790 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
791 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
792 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
793 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
794 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
795 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
796 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
797 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
798 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
799 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
800 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
801 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
802 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
803 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
804 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
805 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
806 q_scalar_mode, q_scalar_swap_mode.
807 (OP_XMM): Handle scalar_mode.
808 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
809 and q_scalar_swap_mode.
810 (OP_VEX): Handle vex_scalar_mode.
812 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
814 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
816 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
818 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
820 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
822 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
824 2010-01-24 H.J. Lu <hongjiu.lu@intel.com>
826 * i386-dis.c (Bad_Opcode): New.
827 (bad_opcode): Likewise.
828 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
829 (dis386_twobyte): Likewise.
830 (reg_table): Likewise.
831 (prefix_table): Likewise.
832 (x86_64_table): Likewise.
833 (vex_len_table): Likewise.
834 (vex_w_table): Likewise.
835 (mod_table): Likewise.
836 (rm_table): Likewise.
837 (float_reg): Likewise.
838 (reg_table): Remove trailing "(bad)" entries.
839 (prefix_table): Likewise.
840 (x86_64_table): Likewise.
841 (vex_len_table): Likewise.
842 (vex_w_table): Likewise.
843 (mod_table): Likewise.
844 (rm_table): Likewise.
845 (get_valid_dis386): Handle bytemode 0.
847 2010-01-23 H.J. Lu <hongjiu.lu@intel.com>
849 * i386-opc.h (VEXScalar): New.
851 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
853 * i386-tbl.h: Regenerated.
855 2010-01-21 H.J. Lu <hongjiu.lu@intel.com>
857 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
859 * i386-opc.tbl: Add xsave64 and xrstor64.
860 * i386-tbl.h: Regenerated.
862 2010-01-20 Nick Clifton <nickc@redhat.com>
865 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
866 based post-indexed addressing.
868 2010-01-15 Sebastian Pop <sebastian.pop@amd.com>
870 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
871 * i386-tbl.h: Regenerated.
873 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
875 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
878 2010-01-14 H.J. Lu <hongjiu.lu@intel.com>
880 * i386-dis.c (names_mm): New.
881 (intel_names_mm): Likewise.
882 (att_names_mm): Likewise.
883 (names_xmm): Likewise.
884 (intel_names_xmm): Likewise.
885 (att_names_xmm): Likewise.
886 (names_ymm): Likewise.
887 (intel_names_ymm): Likewise.
888 (att_names_ymm): Likewise.
889 (print_insn): Set names_mm, names_xmm and names_ymm.
890 (OP_MMX): Use names_mm, names_xmm and names_ymm.
896 (XMM_Fixup): Likewise.
898 (OP_EX_VexReg): Likewise.
899 (OP_Vex_2src): Likewise.
900 (OP_Vex_2src_1): Likewise.
901 (OP_Vex_2src_2): Likewise.
902 (OP_REG_VexI4): Likewise.
904 2010-01-13 H.J. Lu <hongjiu.lu@intel.com>
906 * i386-dis.c (print_insn): Update comments.
908 2010-01-12 H.J. Lu <hongjiu.lu@intel.com>
910 * i386-dis.c (rex_original): Removed.
911 (ckprefix): Remove rex_original.
912 (print_insn): Update comments.
914 2010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
916 * Makefile.in: Regenerate.
917 * configure: Regenerate.
919 2010-01-07 Doug Evans <dje@sebabeach.org>
921 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
922 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
923 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
924 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
925 * xstormy16-ibld.c: Regenerate.
927 2010-01-06 Quentin Neill <quentin.neill@amd.com>
929 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
930 * i386-init.h: Regenerated.
932 2010-01-06 Daniel Gutson <dgutson@codesourcery.com>
934 * arm-dis.c (print_insn): Fixed search for next symbol and data
935 dumping condition, and the initial mapping symbol state.
937 2010-01-05 Doug Evans <dje@sebabeach.org>
939 * cgen-ibld.in: #include "cgen/basic-modes.h".
940 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
941 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
942 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
943 * xstormy16-ibld.c: Regenerate.
945 2010-01-04 Nick Clifton <nickc@redhat.com>
948 * arm-dis.c (print_insn_coprocessor): Initialise value.
950 2010-01-04 Edmar Wienskoski <edmar@freescale.com>
952 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
954 2010-01-02 Doug Evans <dje@sebabeach.org>
956 * cgen-asm.in: Update copyright year.
957 * cgen-dis.in: Update copyright year.
958 * cgen-ibld.in: Update copyright year.
959 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
960 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
961 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
962 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
963 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
964 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
965 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
966 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
967 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
968 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
969 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
970 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
971 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
972 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
973 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
974 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
975 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
976 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
977 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
978 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
979 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
981 For older changes see ChangeLog-2009
987 version-control: never