1 2013-06-21 DJ Delorie <dj@redhat.com>
3 * msp430-decode.opc: New.
4 * msp430-decode.c: New/generated.
5 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
6 (MAINTAINER_CLEANFILES): Likewise.
7 Add rule to build msp430-decode.c frommsp430decode.opc
8 using the opc2c program.
9 * Makefile.in: Regenerate.
10 * configure.in: Add msp430-decode.lo to msp430 architecture files.
11 * configure: Regenerate.
13 2013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
15 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
16 (SYMTAB_AVAILABLE): Removed.
17 (#include "elf/aarch64.h): Ditto.
19 2013-06-17 Catherine Moore <clm@codesourcery.com>
20 Maciej W. Rozycki <macro@codesourcery.com>
21 Chao-Ying Fu <fu@mips.com>
23 * micromips-opc.c (EVA): Define.
25 (micromips_opcodes): Add EVA opcodes.
26 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
27 (print_insn_args): Handle EVA offsets.
28 (print_insn_micromips): Likewise.
29 * mips-opc.c (EVA): Define.
31 (mips_builtin_opcodes): Add EVA opcodes.
33 2013-06-17 Alan Modra <amodra@gmail.com>
35 * Makefile.am (mips-opc.lo): Add rules to create automatic
36 dependency files. Pass archdefs.
37 (micromips-opc.lo, mips16-opc.lo): Likewise.
38 * Makefile.in: Regenerate.
40 2013-06-14 DJ Delorie <dj@redhat.com>
42 * rx-decode.opc (rx_decode_opcode): Bit operations on
43 registers are 32-bit operations, not 8-bit operations.
44 * rx-decode.c: Regenerate.
46 2013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
48 * micromips-opc.c (IVIRT): New define.
49 (IVIRT64): New define.
50 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
51 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
53 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
54 dmtgc0 to print cp0 names.
56 2013-06-09 Sandra Loosemore <sandra@codesourcery.com>
58 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
61 2013-06-08 Catherine Moore <clm@codesourcery.com>
62 Richard Sandiford <rdsandiford@googlemail.com>
64 * micromips-opc.c (D32, D33, MC): Update definitions.
65 (micromips_opcodes): Initialize ase field.
66 * mips-dis.c (mips_arch_choice): Add ase field.
67 (mips_arch_choices): Initialize ase field.
68 (set_default_mips_dis_options): Declare and setup mips_ase.
69 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
70 MT32, MC): Update definitions.
71 (mips_builtin_opcodes): Initialize ase field.
73 2013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
75 * s390-opc.txt (flogr): Require a register pair destination.
77 2013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
79 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
82 2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
84 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
86 2013-05-20 Peter Bergner <bergner@vnet.ibm.com>
88 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
89 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
90 XLS_MASK, PPCVSX2): New defines.
91 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
92 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
93 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
94 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
95 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
96 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
97 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
98 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
99 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
100 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
101 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
102 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
103 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
104 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
105 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
106 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
107 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
108 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
109 <lxvx, stxvx>: New extended mnemonics.
111 2013-05-17 Alan Modra <amodra@gmail.com>
113 * ia64-raw.tbl: Replace non-ASCII char.
114 * ia64-waw.tbl: Likewise.
115 * ia64-asmtab.c: Regenerate.
117 2013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
119 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
120 * i386-init.h: Regenerated.
122 2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
124 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
125 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
126 check from [0, 255] to [-128, 255].
128 2013-05-09 Andrew Pinski <apinski@cavium.com>
130 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
131 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
132 (parse_mips_dis_option): Handle the virt option.
133 (print_insn_args): Handle "+J".
134 (print_mips_disassembler_options): Print out message about virt64.
135 * mips-opc.c (IVIRT): New define.
136 (IVIRT64): New define.
137 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
138 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
139 Move rfe to the bottom as it conflicts with tlbgp.
141 2013-05-09 Alan Modra <amodra@gmail.com>
143 * ppc-opc.c (extract_vlesi): Properly sign extend.
144 (extract_vlensi): Likewise. Comment reason for setting invalid.
146 2013-05-02 Nick Clifton <nickc@redhat.com>
148 * msp430-dis.c: Add support for MSP430X instructions.
150 2013-04-24 Sandra Loosemore <sandra@codesourcery.com>
152 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
155 2013-04-17 Wei-chen Wang <cole945@gmail.com>
158 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
160 (hash_insns_list): Likewise.
162 2013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
164 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
167 2013-04-08 Jan Beulich <jbeulich@suse.com>
169 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
170 * i386-tbl.h: Re-generate.
172 2013-04-06 David S. Miller <davem@davemloft.net>
174 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
175 of an opcode, prefer the one with F_PREFERRED set.
176 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
177 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
178 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
179 mark existing mnenomics as aliases. Add "cc" suffix to edge
180 instructions generating condition codes, mark existing mnenomics
181 as aliases. Add "fp" prefix to VIS compare instructions, mark
182 existing mnenomics as aliases.
184 2013-04-03 Nick Clifton <nickc@redhat.com>
186 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
187 destination address by subtracting the operand from the current
189 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
190 a positive value in the insn.
191 (extract_u16_loop): Do not negate the returned value.
192 (D16_LOOP): Add V850_INVERSE_PCREL flag.
194 (ceilf.sw): Remove duplicate entry.
195 (cvtf.hs): New entry.
201 (maddf.s): Restrict to E3V5 architectures.
203 (nmaddf.s): Likewise.
204 (nmsubf.s): Likewise.
206 2013-03-27 H.J. Lu <hongjiu.lu@intel.com>
208 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
210 (print_insn): Pass sizeflag to get_sib.
212 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
215 * tic6x-dis.c: Add support for displaying 16-bit insns.
217 2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
220 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
221 individual msb and lsb halves in src1 & src2 fields. Discard the
222 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
223 follow what Ti SDK does in that case as any value in the src1
224 field yields the same output with SDK disassembler.
226 2013-03-12 Michael Eager <eager@eagercon.com>
228 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
230 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
232 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
234 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
236 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
238 2013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
240 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
242 2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
244 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
245 (thumb32_opcodes): Likewise.
246 (print_insn_thumb32): Handle 'S' control char.
248 2013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
250 * lm32-desc.c: Regenerate.
252 2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
254 * i386-reg.tbl (riz): Add RegRex64.
255 * i386-tbl.h: Regenerated.
257 2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
259 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
260 (aarch64_feature_crc): New static.
262 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
263 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
264 * aarch64-asm-2.c: Re-generate.
265 * aarch64-dis-2.c: Ditto.
266 * aarch64-opc-2.c: Ditto.
268 2013-02-27 Alan Modra <amodra@gmail.com>
270 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
271 * rl78-decode.c: Regenerate.
273 2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
275 * rl78-decode.opc: Fix encoding of DIVWU insn.
276 * rl78-decode.c: Regenerate.
278 2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
281 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
283 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
284 (cpu_flags): Add CpuSMAP.
286 * i386-opc.h (CpuSMAP): New.
287 (i386_cpu_flags): Add cpusmap.
289 * i386-opc.tbl: Add clac and stac.
291 * i386-init.h: Regenerated.
292 * i386-tbl.h: Likewise.
294 2013-02-15 Markos Chandras <markos.chandras@imgtec.com>
296 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
297 which also makes the disassembler output be in little
298 endian like it should be.
300 2013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
302 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
304 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
306 2013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
308 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
309 section disassembled.
311 2013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
313 * arm-dis.c: Update strht pattern.
315 2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
317 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
318 single-float. Disable ll, lld, sc and scd for EE. Disable the
319 trunc.w.s macro for EE.
321 2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
322 Andrew Jenner <andrew@codesourcery.com>
324 Based on patches from Altera Corporation.
326 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
328 * Makefile.in: Regenerated.
329 * configure.in: Add case for bfd_nios2_arch.
330 * configure: Regenerated.
331 * disassemble.c (ARCH_nios2): Define.
332 (disassembler): Add case for bfd_arch_nios2.
333 * nios2-dis.c: New file.
334 * nios2-opc.c: New file.
336 2013-02-04 Alan Modra <amodra@gmail.com>
338 * po/POTFILES.in: Regenerate.
339 * rl78-decode.c: Regenerate.
340 * rx-decode.c: Regenerate.
342 2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
344 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
345 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
346 * aarch64-asm.c (convert_xtl_to_shll): New function.
347 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
348 calling convert_xtl_to_shll.
349 * aarch64-dis.c (convert_shll_to_xtl): New function.
350 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
351 calling convert_shll_to_xtl.
352 * aarch64-gen.c: Update copyright year.
353 * aarch64-asm-2.c: Re-generate.
354 * aarch64-dis-2.c: Re-generate.
355 * aarch64-opc-2.c: Re-generate.
357 2013-01-24 Nick Clifton <nickc@redhat.com>
359 * v850-dis.c: Add support for e3v5 architecture.
360 * v850-opc.c: Likewise.
362 2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
364 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
365 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
366 * aarch64-opc.c (operand_general_constraint_met_p): For
367 AARCH64_MOD_LSL, move the range check on the shift amount before the
368 alignment check; change to call set_sft_amount_out_of_range_error
369 instead of set_imm_out_of_range_error.
370 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
371 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
372 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
375 2013-01-16 H.J. Lu <hongjiu.lu@intel.com>
377 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
379 * i386-init.h: Regenerated.
380 * i386-tbl.h: Likewise.
382 2013-01-15 Nick Clifton <nickc@redhat.com>
384 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
386 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
388 2013-01-14 Will Newton <will.newton@imgtec.com>
390 * metag-dis.c (REG_WIDTH): Increase to 64.
392 2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
394 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
395 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
396 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
398 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
399 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
400 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
401 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
403 2013-01-10 Will Newton <will.newton@imgtec.com>
405 * Makefile.am: Add Meta.
406 * configure.in: Add Meta.
407 * disassemble.c: Add Meta support.
408 * metag-dis.c: New file.
409 * Makefile.in: Regenerate.
410 * configure: Regenerate.
412 2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
414 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
415 (match_opcode): Rename to cr16_match_opcode.
417 2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
419 * mips-dis.c: Add names for CP0 registers of r5900.
420 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
421 instructions sq and lq.
422 Add support for MIPS r5900 CPU.
423 Add support for 128 bit MMI (Multimedia Instructions).
424 Add support for EE instructions (Emotion Engine).
425 Disable unsupported floating point instructions (64 bit and
426 undefined compare operations).
427 Enable instructions of MIPS ISA IV which are supported by r5900.
428 Disable 64 bit co processor instructions.
429 Disable 64 bit multiplication and division instructions.
430 Disable instructions for co-processor 2 and 3, because these are
431 not supported (preparation for later VU0 support (Vector Unit)).
432 Disable cvt.w.s because this behaves like trunc.w.s and the
433 correct execution can't be ensured on r5900.
434 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
435 will confuse less developers and compilers.
437 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
439 * aarch64-opc.c (aarch64_print_operand): Change to print
440 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
442 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
443 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
446 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
448 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
449 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
451 2013-01-02 H.J. Lu <hongjiu.lu@intel.com>
453 * i386-gen.c (process_copyright): Update copyright year to 2013.
455 2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
457 * cr16-dis.c (match_opcode,make_instruction): Remove static
459 (dwordU,wordU): Moved typedefs to opcode/cr16.h
460 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
462 For older changes see ChangeLog-2012
464 Copyright (C) 2013 Free Software Foundation, Inc.
466 Copying and distribution of this file, with or without modification,
467 are permitted in any medium without royalty provided the copyright
468 notice and this notice are preserved.
474 version-control: never