1 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
4 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
6 * i386-dis.c (print_insn): Parenthesize expression to prevent
10 2016-01-25 Tristan Gingold <gingold@adacore.com>
12 * configure: Regenerate.
14 2016-01-25 Tristan Gingold <gingold@adacore.com>
16 * configure: Regenerate.
18 2016-01-12 Peter Bergner <bergner@vnet.ibm.com>
21 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
22 * ppc-opc.c <xscmpnedp>: Delete.
23 <xvcmpnedp>: Likewise.
24 <xvcmpnedp.>: Likewise.
25 <xvcmpnesp>: Likewise.
26 <xvcmpnesp.>: Likewise.
28 2015-12-22 Thomas Preud'homme <thomas.preudhomme@arm.com>
31 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
32 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
35 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
37 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
39 (aarch64_pstatefield_supported_p): Move feature checks for AT
41 (aarch64_sys_ins_reg_supported_p): .. to here.
43 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Regenerate.
47 * aarch64-opc-2.c: Regenerate.
48 * aarch64-tbl.h (QL_SSHIFT_H): New.
49 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
50 and fcvtzu to the Adv.SIMD scalar shift by immediate group.
52 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
54 * aarch64-asm-2.c: Regenerate.
55 * aarch64-dis-2.c: Regenerate.
56 * aarch64-opc-2.c: Regenerate.
57 * aarch64-tbl.h (QL_VSHIFT_H): New.
58 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
59 and fcvtzu to the Adv.SIMD shift by immediate group.
61 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
63 * aarch64-asm-2.c: Regenerate.
64 * aarch64-dis-2.c: Regenerate.
65 * aarch64-opc-2.c: Regenerate.
66 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
67 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
68 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
70 2015-12-15 Matthew Wahab <matthew.wahab@arm.coM>
72 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
73 and adjust calculation to ignore qualifier for type 2H.
74 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
76 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
78 * aarch64-asm-2.c: Regenerate.
79 * aarch64-dis-2.c: Regenerate.
80 * aarch64-opc-2.c: Regenerate.
81 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
82 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
83 modified immediate group.
85 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
87 * aarch64-asm-2.c: Regenerate.
88 * aarch64-dis-2.c: Regenerate.
89 * aarch64-opc-2.c: Regenerate.
90 * aarch64-tbl.h (QL_XLANES_FP_H): New.
91 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
92 fminnmv, fminv to the Adv.SIMD across lanes group.
94 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
96 * aarch64-asm-2.c: Regenerate.
97 * aarch64-dis-2.c: Regenerate.
98 * aarch64-opc-2.c: Regenerate.
99 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
100 fmls, fmul and fmulx to the scalar indexed element group.
102 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
104 * aarch64-asm-2.c: Regenerate.
105 * aarch64-dis-2.c: Regenerate.
106 * aarch64-opc-2.c: Regenerate.
107 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
108 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
109 fmulx to the vector indexed element group.
111 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
113 * aarch64-asm-2.c: Regenerate.
114 * aarch64-dis-2.c: Regenerate.
115 * aarch64-opc-2.c: Regenerate.
116 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
118 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
119 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
120 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
121 fcvtzu and frsqrte to the scalar two register misc. group.
123 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
125 * aarch64-asm-2.c: Regenerate.
126 * aarch64-dis-2.c: Regenerate.
127 * aarch64-opc-2.c: Regenerate.
128 * aarch64-tbl.h (QL_V2SAMEH): New.
129 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
130 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
131 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
132 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
133 and fsqrt to the vector register misc. group.
135 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
137 * aarch64-asm-2.c: Regenerate.
138 * aarch64-dis-2.c: Regenerate.
139 * aarch64-opc-2.c: Regenerate.
140 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
141 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
142 to the scalar three same group.
144 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
146 * aarch64-asm-2.c: Regenerate.
147 * aarch64-dis-2.c: Regenerate.
148 * aarch64-opc-2.c: Regenerate.
149 * aarch64-tbl.h (QL_V3SAMEH): New.
150 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
151 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
152 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
153 fcmgt, facgt and fminp to the vector three same group.
155 2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
157 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
160 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
162 * aarch64-asm.c (aarch64_ins_hint): New.
163 * aarch64-asm.h (aarch64_ins_hint): Declare.
164 * aarch64-dis.c (aarch64_ext_hint): New.
165 * aarch64-dis.h (aarch64_ext_hint): Declare.
166 * aarch64-opc-2.c: Regenerate.
167 * aarch64-opc.c (aarch64_hint_options): New.
168 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
170 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
172 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
174 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
176 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
177 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
178 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
180 (aarch64_sys_reg_supported_p): Add architecture feature tests for
183 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
185 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
186 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
187 feature test for "s1e1rp" and "s1e1wp".
189 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
191 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
192 (aarch64_sys_ins_reg_supported_p): New.
194 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
196 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
197 with aarch64_sys_ins_reg_has_xt.
198 (aarch64_ext_sysins_op): Likewise.
199 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
201 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
202 (aarch64_sys_regs_dc): Likewise.
203 (aarch64_sys_regs_at): Likewise.
204 (aarch64_sys_regs_tlbi): Likewise.
205 (aarch64_sys_ins_reg_has_xt): New.
207 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
209 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
210 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
211 (aarch64_pstatefields): Add "uao".
212 (aarch64_pstatefield_supported_p): Add checks for "uao".
214 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
216 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
217 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
218 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
219 (aarch64_sys_reg_supported_p): Add architecture feature tests for
222 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Regenerate.
226 * aarch64-tbl.h (aarch64_feature_ras): New.
228 (aarch64_opcode_table): Add "esb".
230 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
232 * aarch64-asm-2.c: Regenerate.
233 * aarch64-dis-2.c: Regenerate.
234 * aarch64-opc-2.c: Regenerate.
235 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
236 (QL_INT2FP_H, QL_FP2INT_H): New.
237 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
240 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
241 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
242 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
243 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
244 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
245 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
248 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
250 * aarch64-opc.c (half_conv_t): New.
251 (expand_fp_imm): Replace is_dp flag with the parameter size to
252 specify the number of bytes for the required expansion. Treat
253 a 16-bit expansion like a 32-bit expansion. Add check for an
254 unsupported size request. Update comment.
255 (aarch64_print_operand): Update to support 16-bit floating point
256 values. Update for changes to expand_fp_imm.
258 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
260 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
263 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
265 * aarch64-asm-2.c: Regenerate.
266 * aarch64-dis-2.c: Regenerate.
267 * aarch64-opc-2.c: Regenerate.
268 * aarch64-tbl.h (aarch64_opcode_table): Update "rev", add
271 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
273 * aarch64-asm-2.c: Regenerate.
274 * aarch64-asm.c (convert_bfc_to_bfm): New.
275 (convert_to_real): Add case for OP_BFC.
276 * aarch64-dis-2.c: Regenerate.
277 * aarch64-dis.c: (convert_bfm_to_bfc): New.
278 (convert_to_alias): Add case for OP_BFC.
279 * aarch64-opc-2.c: Regenerate.
280 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
281 to allow width operand in three-operand instructions.
282 * aarch64-tbl.h (QL_BF1): New.
283 (aarch64_feature_v8_2): New.
285 (aarch64_opcode_table): Add "bfc".
287 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
289 * aarch64-asm-2.c: Regenerate.
290 * aarch64-dis-2.c: Regenerate.
291 * aarch64-dis.c: Weaken assert.
292 * aarch64-gen.c: Include the instruction in the list of its
295 2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
297 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
298 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
301 2015-12-09 H.J. Lu <hongjiu.lu@intel.com>
303 * i386-dis.c (MOD_0F01_REG_5): New.
304 (RM_0F01_REG_5): Likewise.
305 (reg_table): Use MOD_0F01_REG_5.
306 (mod_table): Add MOD_0F01_REG_5.
307 (rm_table): Add RM_0F01_REG_5.
308 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
309 (cpu_flags): Add CpuOSPKE.
310 * i386-opc.h (CpuOSPKE): New.
311 (i386_cpu_flags): Add cpuospke.
312 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
313 * i386-init.h: Regenerated.
314 * i386-tbl.h: Likewise.
316 2015-12-08 Matthew Wahab <matthew.wahab@arm.com>
318 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
319 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
320 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
321 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
322 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
323 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
324 cnthv_ctl_el2, cnthv_cval_el2.
325 (aarch64_sys_reg_supported_p): Update for the new system
328 2015-11-20 Nick Clifton <nickc@redhat.com>
330 * po/zh_CN.po: Updated simplified Chinese translation.
332 2015-11-13 Tristan Gingold <gingold@adacore.com>
334 * configure: Regenerate.
336 2015-11-13 Tristan Gingold <gingold@adacore.com>
338 * configure: Regenerate.
340 2015-11-11 Alan Modra <amodra@gmail.com>
341 Peter Bergner <bergner@vnet.ibm.com>
343 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
344 Add PPC_OPCODE_VSX3 to the vsx entry.
345 (powerpc_init_dialect): Set default dialect to power9.
346 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
347 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
348 extract_l1 insert_xtq6, extract_xtq6): New static functions.
349 (insert_esync): Test for illegal L operand value.
350 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
351 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
352 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
353 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
354 PPCVSX3): New defines.
355 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
356 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
357 <mcrxr>: Use XBFRARB_MASK.
358 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
359 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
360 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
361 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
362 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
363 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
364 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
365 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
366 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
367 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
368 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
369 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
370 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
371 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
372 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
373 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
374 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
375 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
376 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
377 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
378 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
379 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
380 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
381 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
382 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
383 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
384 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
385 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
386 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
387 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
388 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
389 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
391 2015-11-02 Nick Clifton <nickc@redhat.com>
393 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
395 * rx-decode.c: Regenerate.
397 2015-11-02 Nick Clifton <nickc@redhat.com>
399 * rx-decode.opc (rx_disp): If the displacement is zero, set the
400 type to RX_Operand_Zero_Indirect.
401 * rx-decode.c: Regenerate.
402 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
404 2015-10-28 Yao Qi <yao.qi@linaro.org>
406 * aarch64-dis.c (aarch64_decode_insn): Add one argument
407 noaliases_p. Update comments. Pass noaliases_p rather than
408 no_aliases to aarch64_opcode_decode.
409 (print_insn_aarch64_word): Pass no_aliases to
412 2015-10-27 Vinay <Vinay.G@kpit.com>
415 * rl78-decode.opc (MOV): Added offset to DE register in index
417 * rl78-decode.c: Regenerate.
419 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
422 * rl78-decode.opc: Add 's' print operator to instructions that
423 access system registers.
424 * rl78-decode.c: Regenerate.
425 * rl78-dis.c (print_insn_rl78_common): Decode all system
428 2015-10-27 Vinay Kumar <vinay.g@kpit.com>
431 * rl78-decode.opc: Add 'a' print operator to mov instructions
432 using stack pointer plus index addressing.
433 * rl78-decode.c: Regenerate.
435 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
437 * s390-opc.c: Fix comment.
438 * s390-opc.txt: Change instruction type for troo, trot, trto, and
439 trtt to RRF_U0RER since the second parameter does not need to be a
442 2015-10-08 Nick Clifton <nickc@redhat.com>
444 * arc-dis.c (print_insn_arc): Initiallise insn array.
446 2015-10-07 Yao Qi <yao.qi@linaro.org>
448 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
449 'name' rather than 'template'.
450 * aarch64-opc.c (aarch64_print_operand): Likewise.
452 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
454 * arc-dis.c: Revamped file for ARC support
455 * arc-dis.h: Likewise.
456 * arc-ext.c: Likewise.
457 * arc-ext.h: Likewise.
458 * arc-opc.c: Likewise.
459 * arc-fxi.h: New file.
460 * arc-regs.h: Likewise.
461 * arc-tbl.h: Likewise.
463 2015-10-02 Yao Qi <yao.qi@linaro.org>
465 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
466 argument insn type to aarch64_insn. Rename to ...
467 (aarch64_decode_insn): ... it.
468 (print_insn_aarch64_word): Caller updated.
470 2015-10-02 Yao Qi <yao.qi@linaro.org>
472 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
473 (print_insn_aarch64_word): Caller updated.
475 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
477 * s390-mkopc.c (main): Parse htm and vx flag.
478 * s390-opc.txt: Mark instructions from the hardware transactional
479 memory and vector facilities with the "htm"/"vx" flag.
481 2015-09-28 Nick Clifton <nickc@redhat.com>
483 * po/de.po: Updated German translation.
485 2015-09-28 Tom Rix <tom@bumblecow.com>
487 * ppc-opc.c (PPC500): Mark some opcodes as invalid
489 2015-09-23 Nick Clifton <nickc@redhat.com>
491 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
493 * tic30-dis.c (print_branch): Likewise.
494 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
495 value before left shifting.
496 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
497 * hppa-dis.c (print_insn_hppa): Likewise.
498 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
500 * msp430-dis.c (msp430_singleoperand): Likewise.
501 (msp430_doubleoperand): Likewise.
502 (print_insn_msp430): Likewise.
503 * nds32-asm.c (parse_operand): Likewise.
504 * sh-opc.h (MASK): Likewise.
505 * v850-dis.c (get_operand_value): Likewise.
507 2015-09-22 Nick Clifton <nickc@redhat.com>
509 * rx-decode.opc (bwl): Use RX_Bad_Size.
511 (ubwl): Likewise. Rename to ubw.
512 (uBWL): Rename to uBW.
513 Replace all references to uBWL with uBW.
514 * rx-decode.c: Regenerate.
515 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
516 (opsize_names): Likewise.
517 (print_insn_rx): Detect and report RX_Bad_Size.
519 2015-09-22 Anton Blanchard <anton@samba.org>
521 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
523 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
525 * sparc-dis.c (print_insn_sparc): Handle the privileged register
528 2015-08-24 Jan Stancek <jstancek@redhat.com>
530 * i386-dis.c (print_insn): Fix decoding of three byte operands.
532 2015-08-21 Alexander Fomin <alexander.fomin@intel.com>
535 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
536 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
537 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
538 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
539 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
540 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
541 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
542 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
543 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
544 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
545 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
546 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
547 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
548 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
549 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
550 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
551 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
552 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
553 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
554 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
555 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
556 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
557 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
558 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
559 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
560 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
561 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
562 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
563 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
564 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
565 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
566 (vex_w_table): Replace terminals with MOD_TABLE entries for
567 most of mask instructions.
569 2015-08-17 Alan Modra <amodra@gmail.com>
571 * cgen.sh: Trim trailing space from cgen output.
572 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
573 (print_dis_table): Likewise.
574 * opc2c.c (dump_lines): Likewise.
575 (orig_filename): Warning fix.
576 * ia64-asmtab.c: Regenerate.
578 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
580 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
581 and higher with ARM instruction set will now mark the 26-bit
582 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
583 (arm_opcodes): Fix for unpredictable nop being recognized as a
586 2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
588 * micromips-opc.c (micromips_opcodes): Re-order table so that move
589 based on 'or' is first.
590 * mips-opc.c (mips_builtin_opcodes): Ditto.
592 2015-08-11 Nick Clifton <nickc@redhat.com>
595 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
598 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
600 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
602 2015-08-07 Amit Pawar <Amit.Pawar@amd.com>
604 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
605 * i386-init.h: Regenerated.
607 2015-07-30 H.J. Lu <hongjiu.lu@intel.com>
610 * i386-dis.c (MOD_0FC3): New.
611 (PREFIX_0FC3): Renamed to ...
612 (PREFIX_MOD_0_0FC3): This.
613 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
614 (prefix_table): Replace Ma with Ev on movntiS.
615 (mod_table): Add MOD_0FC3.
617 2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
619 * configure: Regenerated.
621 2015-07-23 Alan Modra <amodra@gmail.com>
624 * i386-dis.c (get64): Avoid signed integer overflow.
626 2015-07-22 Alexander Fomin <alexander.fomin@intel.com>
629 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
630 "EXEvexHalfBcstXmmq" for the second operand.
631 (EVEX_W_0F79_P_2): Likewise.
632 (EVEX_W_0F7A_P_2): Likewise.
633 (EVEX_W_0F7B_P_2): Likewise.
635 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
637 * arm-dis.c (print_insn_coprocessor): Added support for quarter
638 float bitfield format.
639 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
640 quarter float bitfield format.
642 2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
644 * configure: Regenerated.
646 2015-07-03 Alan Modra <amodra@gmail.com>
648 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
649 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
650 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
652 2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
653 Cesar Philippidis <cesar@codesourcery.com>
655 * nios2-dis.c (nios2_extract_opcode): New.
656 (nios2_disassembler_state): New.
657 (nios2_find_opcode_hash): Use mach parameter to select correct
659 (nios2_print_insn_arg): Extend to support new R2 argument letters
661 (print_insn_nios2): Check for 16-bit instruction at end of memory.
662 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
663 (NIOS2_NUM_OPCODES): Rename to...
664 (NIOS2_NUM_R1_OPCODES): This.
665 (nios2_r2_opcodes): New.
666 (NIOS2_NUM_R2_OPCODES): New.
667 (nios2_num_r2_opcodes): New.
668 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
669 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
670 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
671 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
672 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
674 2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
676 * i386-dis.c (OP_Mwaitx): New.
677 (rm_table): Add monitorx/mwaitx.
678 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
679 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
680 (operand_type_init): Add CpuMWAITX.
681 * i386-opc.h (CpuMWAITX): New.
682 (i386_cpu_flags): Add cpumwaitx.
683 * i386-opc.tbl: Add monitorx and mwaitx.
684 * i386-init.h: Regenerated.
685 * i386-tbl.h: Likewise.
687 2015-06-22 Peter Bergner <bergner@vnet.ibm.com>
689 * ppc-opc.c (insert_ls): Test for invalid LS operands.
690 (insert_esync): New function.
691 (LS, WC): Use insert_ls.
692 (ESYNC): Use insert_esync.
694 2015-06-22 Nick Clifton <nickc@redhat.com>
696 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
697 requested region lies beyond it.
698 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
699 looking for 32-bit insns.
700 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
702 * sh-dis.c (print_insn_sh): Likewise.
703 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
704 blocks of instructions.
705 * vax-dis.c (print_insn_vax): Check that the requested address
706 does not clash with the stop_vma.
708 2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
710 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
711 * ppc-opc.c (FXM4): Add non-zero optional value.
714 (insert_fxm): Handle new default operand value.
715 (extract_fxm): Likewise.
716 (insert_tbr): Likewise.
717 (extract_tbr): Likewise.
719 2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
721 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
723 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
725 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
727 2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
729 * ppc-opc.c: Add comment accidentally removed by old commit.
732 2015-06-04 Peter Bergner <bergner@vnet.ibm.com>
734 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
736 2015-06-04 Nick Clifton <nickc@redhat.com>
739 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
741 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
743 * arm-dis.c (arm_opcodes): Add "setpan".
744 (thumb_opcodes): Add "setpan".
746 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
748 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
751 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
753 * aarch64-tbl.h (aarch64_feature_rdma): New.
755 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
756 * aarch64-asm-2.c: Regenerate.
757 * aarch64-dis-2.c: Regenerate.
758 * aarch64-opc-2.c: Regenerate.
760 2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
762 * aarch64-tbl.h (aarch64_feature_lor): New.
764 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
766 * aarch64-asm-2.c: Regenerate.
767 * aarch64-dis-2.c: Regenerate.
768 * aarch64-opc-2.c: Regenerate.
770 2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
772 * aarch64-opc.c (F_ARCHEXT): New.
773 (aarch64_sys_regs): Add "pan".
774 (aarch64_sys_reg_supported_p): New.
775 (aarch64_pstatefields): Add "pan".
776 (aarch64_pstatefield_supported_p): New.
778 2015-06-01 Jan Beulich <jbeulich@suse.com>
780 * i386-tbl.h: Regenerate.
782 2015-06-01 Jan Beulich <jbeulich@suse.com>
784 * i386-dis.c (print_insn): Swap rounding mode specifier and
785 general purpose register in Intel mode.
787 2015-06-01 Jan Beulich <jbeulich@suse.com>
789 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
790 * i386-tbl.h: Regenerate.
792 2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
794 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
795 * i386-init.h: Regenerated.
797 2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
800 * i386-dis.c: Add comments for '@'.
801 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
802 (enum x86_64_isa): New.
804 (print_i386_disassembler_options): Add amd64 and intel64.
805 (print_insn): Handle amd64 and intel64.
807 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
808 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
809 * i386-opc.h (AMD64): New.
810 (CpuIntel64): Likewise.
811 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
812 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
813 Mark direct call/jmp without Disp16|Disp32 as Intel64.
814 * i386-init.h: Regenerated.
815 * i386-tbl.h: Likewise.
817 2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
819 * ppc-opc.c (IH) New define.
820 (powerpc_opcodes) <wait>: Do not enable for POWER7.
821 <tlbie>: Add RS operand for POWER7.
822 <slbia>: Add IH operand for POWER6.
824 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
826 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
829 * i386-tbl.h: Regenerated.
831 2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
833 * configure.ac: Support bfd_iamcu_arch.
834 * disassemble.c (disassembler): Support bfd_iamcu_arch.
835 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
836 CPU_IAMCU_COMPAT_FLAGS.
837 (cpu_flags): Add CpuIAMCU.
838 * i386-opc.h (CpuIAMCU): New.
839 (i386_cpu_flags): Add cpuiamcu.
840 * configure: Regenerated.
841 * i386-init.h: Likewise.
842 * i386-tbl.h: Likewise.
844 2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
847 * i386-dis.c (X86_64_E8): New.
848 (X86_64_E9): Likewise.
849 Update comments on 'T', 'U', 'V'. Add comments for '^'.
850 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
851 (x86_64_table): Add X86_64_E8 and X86_64_E9.
852 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
854 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
857 2015-04-30 DJ Delorie <dj@redhat.com>
859 * disassemble.c (disassembler): Choose suitable disassembler based
861 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
862 it to decode mul/div insns.
863 * rl78-decode.c: Regenerate.
864 * rl78-dis.c (print_insn_rl78): Rename to...
865 (print_insn_rl78_common): ...this, take ISA parameter.
866 (print_insn_rl78): New.
867 (print_insn_rl78_g10): New.
868 (print_insn_rl78_g13): New.
869 (print_insn_rl78_g14): New.
870 (rl78_get_disassembler): New.
872 2015-04-29 Nick Clifton <nickc@redhat.com>
874 * po/fr.po: Updated French translation.
876 2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
878 * ppc-opc.c (DCBT_EO): New define.
879 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
883 <waitrsv>: Do not enable for POWER7 and later.
884 <waitimpl>: Likewise.
885 <dcbt>: Default to the two operand form of the instruction for all
886 "old" cpus. For "new" cpus, use the operand ordering that matches
887 whether the cpu is server or embedded.
890 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
892 * s390-opc.c: New instruction type VV0UU2.
893 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
896 2015-04-23 Jan Beulich <jbeulich@suse.com>
898 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
899 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
900 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
901 (vfpclasspd, vfpclassps): Add %XZ.
903 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
905 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
906 (PREFIX_UD_REPZ): Likewise.
907 (PREFIX_UD_REPNZ): Likewise.
908 (PREFIX_UD_DATA): Likewise.
909 (PREFIX_UD_ADDR): Likewise.
910 (PREFIX_UD_LOCK): Likewise.
912 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
914 * i386-dis.c (prefix_requirement): Removed.
915 (print_insn): Don't set prefix_requirement. Check
916 dp->prefix_requirement instead of prefix_requirement.
918 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
921 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
922 (PREFIX_MOD_0_0FC7_REG_6): This.
923 (PREFIX_MOD_3_0FC7_REG_6): New.
924 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
925 (prefix_table): Replace PREFIX_0FC7_REG_6 with
926 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
927 PREFIX_MOD_3_0FC7_REG_7.
928 (mod_table): Replace PREFIX_0FC7_REG_6 with
929 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
930 PREFIX_MOD_3_0FC7_REG_7.
932 2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
934 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
935 (PREFIX_MANDATORY_REPNZ): Likewise.
936 (PREFIX_MANDATORY_DATA): Likewise.
937 (PREFIX_MANDATORY_ADDR): Likewise.
938 (PREFIX_MANDATORY_LOCK): Likewise.
939 (PREFIX_MANDATORY): Likewise.
940 (PREFIX_UD_SHIFT): Set to 8
941 (PREFIX_UD_REPZ): Updated.
942 (PREFIX_UD_REPNZ): Likewise.
943 (PREFIX_UD_DATA): Likewise.
944 (PREFIX_UD_ADDR): Likewise.
945 (PREFIX_UD_LOCK): Likewise.
946 (PREFIX_IGNORED_SHIFT): New.
947 (PREFIX_IGNORED_REPZ): Likewise.
948 (PREFIX_IGNORED_REPNZ): Likewise.
949 (PREFIX_IGNORED_DATA): Likewise.
950 (PREFIX_IGNORED_ADDR): Likewise.
951 (PREFIX_IGNORED_LOCK): Likewise.
952 (PREFIX_OPCODE): Likewise.
953 (PREFIX_IGNORED): Likewise.
954 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
955 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
956 (three_byte_table): Likewise.
957 (mod_table): Likewise.
958 (mandatory_prefix): Renamed to ...
959 (prefix_requirement): This.
960 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
961 Update PREFIX_90 entry.
962 (get_valid_dis386): Check prefix_requirement to see if a prefix
964 (print_insn): Replace mandatory_prefix with prefix_requirement.
966 2015-04-15 Renlin Li <renlin.li@arm.com>
968 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
969 use it for ssat and ssat16.
970 (print_insn_thumb32): Add handle case for 'D' control code.
972 2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
973 H.J. Lu <hongjiu.lu@intel.com>
975 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
976 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
977 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
978 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
979 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
980 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
981 Fill prefix_requirement field.
982 (struct dis386): Add prefix_requirement field.
983 (dis386): Fill prefix_requirement field.
984 (dis386_twobyte): Ditto.
985 (twobyte_has_mandatory_prefix_: Remove.
986 (reg_table): Fill prefix_requirement field.
987 (prefix_table): Ditto.
988 (x86_64_table): Ditto.
989 (three_byte_table): Ditto.
992 (vex_len_table): Ditto.
993 (vex_w_table): Ditto.
996 (print_insn): Use prefix_requirement.
997 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
998 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1001 2015-03-30 Mike Frysinger <vapier@gentoo.org>
1003 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1005 2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
1007 * Makefile.in: Regenerated.
1009 2015-03-25 Anton Blanchard <anton@samba.org>
1011 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1012 powerpc_opcd_indices and vle_opcd_indices once.
1014 2015-03-25 Anton Blanchard <anton@samba.org>
1016 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1018 2015-03-24 Terry Guo <terry.guo@arm.com>
1020 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1021 (opcode16): Likewise.
1022 (coprocessor_opcodes): Replace bit with feature struct.
1023 (neon_opcodes): Likewise.
1024 (arm_opcodes): Likewise.
1025 (thumb_opcodes): Likewise.
1026 (thumb32_opcodes): Likewise.
1027 (print_insn_coprocessor): Likewise.
1028 (print_insn_arm): Likewise.
1029 (select_arm_features): Follow new feature struct.
1031 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1033 * i386-dis.c (rm_table): Add clzero.
1034 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1035 Add CPU_CLZERO_FLAGS.
1036 (cpu_flags): Add CpuCLZERO.
1037 * i386-opc.h: Add CpuCLZERO.
1038 * i386-opc.tbl: Add clzero.
1039 * i386-init.h: Re-generated.
1040 * i386-tbl.h: Re-generated.
1042 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1044 * mips-opc.c (decode_mips_operand): Fix constraint issues
1045 with u and y operands.
1047 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1049 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1051 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1053 * s390-opc.c: Add new IBM z13 instructions.
1054 * s390-opc.txt: Likewise.
1056 2015-03-10 Renlin Li <renlin.li@arm.com>
1058 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1059 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1061 * aarch64-asm-2.c: Regenerate.
1062 * aarch64-dis-2.c: Likewise.
1063 * aarch64-opc-2.c: Likewise.
1065 2015-03-03 Jiong Wang <jiong.wang@arm.com>
1067 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1069 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1071 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1073 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1074 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1076 2015-02-23 Vinay <Vinay.G@kpit.com>
1078 * rl78-decode.opc (MOV): Added space between two operands for
1079 'mov' instruction in index addressing mode.
1080 * rl78-decode.c: Regenerate.
1082 2015-02-19 Pedro Alves <palves@redhat.com>
1084 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1086 2015-02-10 Pedro Alves <palves@redhat.com>
1087 Tom Tromey <tromey@redhat.com>
1089 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1090 microblaze_and, microblaze_xor.
1091 * microblaze-opc.h (opcodes): Adjust.
1093 2015-01-28 James Bowman <james.bowman@ftdichip.com>
1095 * Makefile.am: Add FT32 files.
1096 * configure.ac: Handle FT32.
1097 * disassemble.c (disassembler): Call print_insn_ft32.
1098 * ft32-dis.c: New file.
1099 * ft32-opc.c: New file.
1100 * Makefile.in: Regenerate.
1101 * configure: Regenerate.
1102 * po/POTFILES.in: Regenerate.
1104 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1106 * nds32-asm.c (keyword_sr): Add new system registers.
1108 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1110 * s390-dis.c (s390_extract_operand): Support vector register
1112 (s390_print_insn_with_opcode): Support new operands types and add
1113 new handling of optional operands.
1114 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1115 and include opcode/s390.h instead.
1116 (struct op_struct): New field `flags'.
1117 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1118 (dumpTable): Dump flags.
1119 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1121 * s390-opc.c: Add new operands types, instruction formats, and
1123 (s390_opformats): Add new formats for .insn.
1124 * s390-opc.txt: Add new instructions.
1126 2015-01-01 Alan Modra <amodra@gmail.com>
1128 Update year range in copyright notice of all files.
1130 For older changes see ChangeLog-2014
1132 Copyright (C) 2015 Free Software Foundation, Inc.
1134 Copying and distribution of this file, with or without modification,
1135 are permitted in any medium without royalty provided the copyright
1136 notice and this notice are preserved.
1142 version-control: never