1 2017-04-11 Alan Modra <amodra@gmail.com>
3 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
4 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm".
5 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
6 (PPCVEC3): Define as PPC_OPCODE_POWER9.
7 (PPCVSX2): Define as PPC_OPCODE_POWER8.
8 (PPCVSX3): Define as PPC_OPCODE_POWER9.
9 (PPCHTM): Define as PPC_OPCODE_POWER8.
11 2017-04-10 Alan Modra <amodra@gmail.com>
13 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
14 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
15 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
16 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
18 2017-04-09 Pip Cet <pipcet@gmail.com>
20 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
21 appropriate floating-point precision directly.
23 2017-04-07 Alan Modra <amodra@gmail.com>
25 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
26 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
27 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
28 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
29 vector instructions with E6500 not PPCVEC2.
31 2017-04-06 Pip Cet <pipcet@gmail.com>
33 * Makefile.am: Add wasm32-dis.c.
34 * configure.ac: Add wasm32-dis.c to wasm32 target.
35 * disassemble.c: Add wasm32 disassembler code.
36 * wasm32-dis.c: New file.
37 * Makefile.in: Regenerate.
38 * configure: Regenerate.
39 * po/POTFILES.in: Regenerate.
40 * po/opcodes.pot: Regenerate.
42 2017-04-05 Pedro Alves <palves@redhat.com>
44 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
45 * arm-dis.c (parse_arm_disassembler_options): Constify.
46 * ppc-dis.c (powerpc_init_dialect): Constify local.
47 * vax-dis.c (parse_disassembler_options): Constify.
49 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
51 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
54 2017-03-30 Pip Cet <pipcet@gmail.com>
56 * configure.ac: Add (empty) bfd_wasm32_arch target.
57 * configure: Regenerate
58 * po/opcodes.pot: Regenerate.
60 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
62 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
64 * opcodes/sparc-opc.c (asi_table): New ASIs.
66 2017-03-29 Alan Modra <amodra@gmail.com>
68 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
70 (lookup_powerpc): Don't special case -1 dialect. Handle
72 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
73 lookup_powerpc call, pass it on second.
75 2017-03-27 Alan Modra <amodra@gmail.com>
78 * ppc-dis.c (struct ppc_mopt): Comment.
79 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
81 2017-03-27 Rinat Zelig <rinat@mellanox.com>
83 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
84 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
85 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
86 (insert_nps_misc_imm_offset): New function.
87 (extract_nps_misc imm_offset): New function.
88 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
89 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
91 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
93 * s390-mkopc.c (main): Remove vx2 check.
94 * s390-opc.txt: Remove vx2 instruction flags.
96 2017-03-21 Rinat Zelig <rinat@mellanox.com>
98 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
99 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
100 (insert_nps_imm_offset): New function.
101 (extract_nps_imm_offset): New function.
102 (insert_nps_imm_entry): New function.
103 (extract_nps_imm_entry): New function.
105 2017-03-17 Alan Modra <amodra@gmail.com>
108 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
109 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
110 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
112 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
114 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
118 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
120 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
122 2017-03-13 Andrew Waterman <andrew@sifive.com>
124 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
129 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
131 * i386-gen.c (opcode_modifiers): Replace S with Load.
132 * i386-opc.h (S): Removed.
134 (i386_opcode_modifier): Replace s with load.
135 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
136 and {evex}. Replace S with Load.
137 * i386-tbl.h: Regenerated.
139 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
141 * i386-opc.tbl: Use CpuCET on rdsspq.
142 * i386-tbl.h: Regenerated.
144 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
146 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
147 <vsx>: Do not use PPC_OPCODE_VSX3;
149 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
151 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
153 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
155 * i386-dis.c (REG_0F1E_MOD_3): New enum.
156 (MOD_0F1E_PREFIX_1): Likewise.
157 (MOD_0F38F5_PREFIX_2): Likewise.
158 (MOD_0F38F6_PREFIX_0): Likewise.
159 (RM_0F1E_MOD_3_REG_7): Likewise.
160 (PREFIX_MOD_0_0F01_REG_5): Likewise.
161 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
162 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
163 (PREFIX_0F1E): Likewise.
164 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
165 (PREFIX_0F38F5): Likewise.
166 (dis386_twobyte): Use PREFIX_0F1E.
167 (reg_table): Add REG_0F1E_MOD_3.
168 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
169 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
170 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
171 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
172 (three_byte_table): Use PREFIX_0F38F5.
173 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
174 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
175 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
176 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
177 PREFIX_MOD_3_0F01_REG_5_RM_2.
178 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
179 (cpu_flags): Add CpuCET.
180 * i386-opc.h (CpuCET): New enum.
181 (CpuUnused): Commented out.
182 (i386_cpu_flags): Add cpucet.
183 * i386-opc.tbl: Add Intel CET instructions.
184 * i386-init.h: Regenerated.
185 * i386-tbl.h: Likewise.
187 2017-03-06 Alan Modra <amodra@gmail.com>
190 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
191 (extract_raq, extract_ras, extract_rbx): New functions.
192 (powerpc_operands): Use opposite corresponding insert function.
194 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
195 register restriction.
197 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
199 * disassemble.c Include "safe-ctype.h".
200 (disassemble_init_for_target): Handle s390 init.
201 (remove_whitespace_and_extra_commas): New function.
202 (disassembler_options_cmp): Likewise.
203 * arm-dis.c: Include "libiberty.h".
205 (regnames): Use long disassembler style names.
206 Add force-thumb and no-force-thumb options.
207 (NUM_ARM_REGNAMES): Rename from this...
208 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
209 (get_arm_regname_num_options): Delete.
210 (set_arm_regname_option): Likewise.
211 (get_arm_regnames): Likewise.
212 (parse_disassembler_options): Likewise.
213 (parse_arm_disassembler_option): Rename from this...
214 (parse_arm_disassembler_options): ...to this. Make static.
215 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
216 (print_insn): Use parse_arm_disassembler_options.
217 (disassembler_options_arm): New function.
218 (print_arm_disassembler_options): Handle updated regnames.
219 * ppc-dis.c: Include "libiberty.h".
220 (ppc_opts): Add "32" and "64" entries.
221 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
222 (powerpc_init_dialect): Add break to switch statement.
223 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
224 (disassembler_options_powerpc): New function.
225 (print_ppc_disassembler_options): Use ARRAY_SIZE.
226 Remove printing of "32" and "64".
227 * s390-dis.c: Include "libiberty.h".
228 (init_flag): Remove unneeded variable.
229 (struct s390_options_t): New structure type.
230 (options): New structure.
231 (init_disasm): Rename from this...
232 (disassemble_init_s390): ...to this. Add initializations for
233 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
234 (print_insn_s390): Delete call to init_disasm.
235 (disassembler_options_s390): New function.
236 (print_s390_disassembler_options): Print using information from
238 * po/opcodes.pot: Regenerate.
240 2017-02-28 Jan Beulich <jbeulich@suse.com>
242 * i386-dis.c (PCMPESTR_Fixup): New.
243 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
244 (prefix_table): Use PCMPESTR_Fixup.
245 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
247 (vex_w_table): Delete VPCMPESTR{I,M} entries.
248 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
249 Split 64-bit and non-64-bit variants.
250 * opcodes/i386-tbl.h: Re-generate.
252 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
254 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
255 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
256 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
257 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
258 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
259 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
260 (OP_SVE_V_HSD): New macros.
261 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
262 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
263 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
264 (aarch64_opcode_table): Add new SVE instructions.
265 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
266 for rotation operands. Add new SVE operands.
267 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
268 (ins_sve_quad_index): Likewise.
269 (ins_imm_rotate): Split into...
270 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
271 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
272 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
274 (aarch64_ins_sve_addr_ri_s4): New function.
275 (aarch64_ins_sve_quad_index): Likewise.
276 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
277 * aarch64-asm-2.c: Regenerate.
278 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
279 (ext_sve_quad_index): Likewise.
280 (ext_imm_rotate): Split into...
281 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
282 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
283 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
285 (aarch64_ext_sve_addr_ri_s4): New function.
286 (aarch64_ext_sve_quad_index): Likewise.
287 (aarch64_ext_sve_index): Allow quad indices.
288 (do_misc_decoding): Likewise.
289 * aarch64-dis-2.c: Regenerate.
290 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
292 (OPD_F_OD_MASK): Widen by one bit.
293 (OPD_F_NO_ZR): Bump accordingly.
294 (get_operand_field_width): New function.
295 * aarch64-opc.c (fields): Add new SVE fields.
296 (operand_general_constraint_met_p): Handle new SVE operands.
297 (aarch64_print_operand): Likewise.
298 * aarch64-opc-2.c: Regenerate.
300 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
302 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
303 (aarch64_feature_compnum): ...this.
304 (SIMD_V8_3): Replace with...
306 (CNUM_INSN): New macro.
307 (aarch64_opcode_table): Use it for the complex number instructions.
309 2017-02-24 Jan Beulich <jbeulich@suse.com>
311 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
313 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
315 Add support for associating SPARC ASIs with an architecture level.
316 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
317 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
318 decoding of SPARC ASIs.
320 2017-02-23 Jan Beulich <jbeulich@suse.com>
322 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
323 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
325 2017-02-21 Jan Beulich <jbeulich@suse.com>
327 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
328 1 (instead of to itself). Correct typo.
330 2017-02-14 Andrew Waterman <andrew@sifive.com>
332 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
335 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
337 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
338 (aarch64_sys_reg_supported_p): Handle them.
340 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
342 * arc-opc.c (UIMM6_20R): Define.
343 (SIMM12_20): Use above.
344 (SIMM12_20R): Define.
345 (SIMM3_5_S): Use above.
346 (UIMM7_A32_11R_S): Define.
347 (UIMM7_9_S): Use above.
348 (UIMM3_13R_S): Define.
349 (SIMM11_A32_7_S): Use above.
351 (UIMM10_A32_8_S): Use above.
352 (UIMM8_8R_S): Define.
354 (arc_relax_opcodes): Use all above defines.
356 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
358 * arc-regs.h: Distinguish some of the registers different on
359 ARC700 and HS38 cpus.
361 2017-02-14 Alan Modra <amodra@gmail.com>
364 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
365 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
367 2017-02-11 Stafford Horne <shorne@gmail.com>
368 Alan Modra <amodra@gmail.com>
370 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
371 Use insn_bytes_value and insn_int_value directly instead. Don't
372 free allocated memory until function exit.
374 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
376 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
378 2017-02-03 Nick Clifton <nickc@redhat.com>
381 * aarch64-opc.c (print_register_list): Ensure that the register
382 list index will fir into the tb buffer.
383 (print_register_offset_address): Likewise.
384 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
386 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
389 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
390 instructions when the previous fetch packet ends with a 32-bit
393 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
395 * pru-opc.c: Remove vague reference to a future GDB port.
397 2017-01-20 Nick Clifton <nickc@redhat.com>
399 * po/ga.po: Updated Irish translation.
401 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
403 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
405 2017-01-13 Yao Qi <yao.qi@linaro.org>
407 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
408 if FETCH_DATA returns 0.
409 (m68k_scan_mask): Likewise.
410 (print_insn_m68k): Update code to handle -1 return value.
412 2017-01-13 Yao Qi <yao.qi@linaro.org>
414 * m68k-dis.c (enum print_insn_arg_error): New.
415 (NEXTBYTE): Replace -3 with
416 PRINT_INSN_ARG_MEMORY_ERROR.
417 (NEXTULONG): Likewise.
418 (NEXTSINGLE): Likewise.
419 (NEXTDOUBLE): Likewise.
420 (NEXTDOUBLE): Likewise.
421 (NEXTPACKED): Likewise.
422 (FETCH_ARG): Likewise.
423 (FETCH_DATA): Update comments.
424 (print_insn_arg): Update comments. Replace magic numbers with
426 (match_insn_m68k): Likewise.
428 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
430 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
431 * i386-dis-evex.h (evex_table): Updated.
432 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
433 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
434 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
435 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
436 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
437 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
438 * i386-init.h: Regenerate.
441 2017-01-12 Yao Qi <yao.qi@linaro.org>
443 * msp430-dis.c (msp430_singleoperand): Return -1 if
444 msp430dis_opcode_signed returns false.
445 (msp430_doubleoperand): Likewise.
446 (msp430_branchinstr): Return -1 if
447 msp430dis_opcode_unsigned returns false.
448 (msp430x_calla_instr): Likewise.
449 (print_insn_msp430): Likewise.
451 2017-01-05 Nick Clifton <nickc@redhat.com>
454 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
455 could not be matched.
456 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
459 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
461 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
462 (aarch64_opcode_table): Use RCPC_INSN.
464 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
466 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
468 * riscv-opcodes/all-opcodes: Likewise.
470 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
472 * riscv-dis.c (print_insn_args): Add fall through comment.
474 2017-01-03 Nick Clifton <nickc@redhat.com>
476 * po/sr.po: New Serbian translation.
477 * configure.ac (ALL_LINGUAS): Add sr.
478 * configure: Regenerate.
480 2017-01-02 Alan Modra <amodra@gmail.com>
482 * epiphany-desc.h: Regenerate.
483 * epiphany-opc.h: Regenerate.
484 * fr30-desc.h: Regenerate.
485 * fr30-opc.h: Regenerate.
486 * frv-desc.h: Regenerate.
487 * frv-opc.h: Regenerate.
488 * ip2k-desc.h: Regenerate.
489 * ip2k-opc.h: Regenerate.
490 * iq2000-desc.h: Regenerate.
491 * iq2000-opc.h: Regenerate.
492 * lm32-desc.h: Regenerate.
493 * lm32-opc.h: Regenerate.
494 * m32c-desc.h: Regenerate.
495 * m32c-opc.h: Regenerate.
496 * m32r-desc.h: Regenerate.
497 * m32r-opc.h: Regenerate.
498 * mep-desc.h: Regenerate.
499 * mep-opc.h: Regenerate.
500 * mt-desc.h: Regenerate.
501 * mt-opc.h: Regenerate.
502 * or1k-desc.h: Regenerate.
503 * or1k-opc.h: Regenerate.
504 * xc16x-desc.h: Regenerate.
505 * xc16x-opc.h: Regenerate.
506 * xstormy16-desc.h: Regenerate.
507 * xstormy16-opc.h: Regenerate.
509 2017-01-02 Alan Modra <amodra@gmail.com>
511 Update year range in copyright notice of all files.
513 For older changes see ChangeLog-2016
515 Copyright (C) 2017 Free Software Foundation, Inc.
517 Copying and distribution of this file, with or without modification,
518 are permitted in any medium without royalty provided the copyright
519 notice and this notice are preserved.
525 version-control: never