1 2006-10-26 Daniel Jacobowitz <dan@codesourcery.com>
3 * h8300-dis.c (bfd_h8_disassemble): Add missing consts.
5 2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com>
6 Yukishige Shibata <shibata@rd.scei.sony.co.jp>
7 Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp>
8 Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp>
9 Alan Modra <amodra@bigpond.net.au>
11 * spu-dis.c: New file.
12 * spu-opc.c: New file.
13 * configure.in: Add SPU support.
14 * disassemble.c: Likewise.
15 * Makefile.am: Likewise. Run "make dep-am".
16 * Makefile.in: Regenerate.
17 * configure: Regenerate.
18 * po/POTFILES.in: Regenerate.
20 2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com>
22 * ppc-opc.c (CELL): New define.
23 (powerpc_opcodes): Enable hrfid for Cell. Add ldbrx and stdbrx,
24 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
26 * ppc-dis.c (powerpc_dialect): Handle cell.
28 2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
30 * i386-dis.c (dis386): Add support for the change in POPCNT opcode in
31 amdfam10 architecture.
33 (print_insn): Disallow REP prefix for POPCNT.
35 2006-10-20 Andrew Stubbs <andrew.stubbs@st.com>
37 * sh-dis.c (print_insn_sh): Remove 0x from output to prevent GDB
40 2006-10-18 Dave Brolley <brolley@redhat.com>
42 * configure.in (BFD_MACHINES): Add cgen-bitset.lo for bfd_sh_arch.
43 * configure: Regenerated.
45 2006-09-29 Alan Modra <amodra@bigpond.net.au>
47 * po/POTFILES.in: Regenerate.
49 2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
50 Joseph Myers <joseph@codesourcery.com>
51 Ian Lance Taylor <ian@wasabisystems.com>
52 Ben Elliston <bje@wasabisystems.com>
54 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
55 only be used with the default multiply-add operation, so if N is
56 set, don't bother printing X. Add new iwmmxt instructions.
57 (IWMMXT_INSN_COUNT): Update.
58 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
60 (print_insn_coprocessor): Check for iWMMXt2. Handle format
63 2006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
66 * i386-dis.c (prefix_user_table): Fix the second operand of
67 maskmovdqu instruction to allow only %xmm register instead of
68 both %xmm register and memory.
70 2006-09-23 H.J. Lu <hongjiu.lu@intel.com>
73 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
76 2006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
78 * score-dis.c: New file.
79 * score-opc.h: New file.
80 * Makefile.am: Add Score files.
81 * Makefile.in: Regenerate.
82 * configure.in: Add support for Score target.
83 * configure: Regenerate.
84 * disassemble.c: Add support for Score target.
86 2006-09-16 Nick Clifton <nickc@redhat.com>
87 Pedro Alves <pedro_alves@portugalmail.pt>
89 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
90 macros defined in bfd.h.
91 * cris-dis.c: Likewise.
92 * h8300-dis.c: Likewise.
93 * i386-dis.c: Likewise.
94 * ia64-gen.c: Likewise.
97 2006-09-04 Paul Brook <paul@codesourcery.com>
99 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
101 2006-08-23 H.J. Lu <hongjiu.lu@intel.com>
103 * i386-dis.c (three_byte_table): Expand to 256 elements.
105 2006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
108 * i386-dis.c (MXC,EMC): Define.
109 (OP_MXC): New function to handle cvt* (convert instructions) between
110 %xmm and %mm register correctly.
112 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
113 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
116 2006-07-29 Richard Sandiford <richard@codesourcery.com>
118 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
121 2006-07-19 Paul Brook <paul@codesourcery.com>
123 * armd-dis.c (arm_opcodes): Fix rbit opcode.
125 2006-07-18 H.J. Lu <hongjiu.lu@intel.com>
127 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
128 "sldt", "str" and "smsw".
130 2006-07-15 H.J. Lu <hongjiu.lu@intel.com>
133 * i386-dis.c (GRP11_C6): NEW.
134 (GRP11_C7): Likewise.
141 (GRPPADLCK1): Likewise.
142 (GRPPADLCK2): Likewise.
143 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
145 (grps): Add entries for GRP11_C6 and GRP11_C7.
147 2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
148 Michael Meissner <michael.meissner@amd.com>
150 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
151 support for amdfam10 SSE4a/ABM instructions. Modify all
152 initializer macros to have additional arguments. Disallow REP
153 prefix for non-string instructions.
156 2006-07-05 Julian Brown <julian@codesourcery.com>
158 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
160 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
162 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
163 (twobyte_has_modrm): Set 1 for 0x1f.
165 2006-06-12 H.J. Lu <hongjiu.lu@intel.com>
167 * i386-dis.c (NOP_Fixup): Removed.
169 (NOP_Fixup2): Likewise.
170 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
172 2006-06-12 Julian Brown <julian@codesourcery.com>
174 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
177 2006-06-10 H.J. Lu <hongjiu.lu@intel.com>
179 * i386.c (GRP10): Renamed to ...
181 (GRP11): Renamed to ...
183 (GRP12): Renamed to ...
185 (GRP13): Renamed to ...
187 (GRP14): Renamed to ...
189 (dis386_twobyte): Updated.
192 2006-06-09 Nick Clifton <nickc@redhat.com>
194 * po/fi.po: Updated Finnish translation.
196 2006-06-07 Joseph S. Myers <joseph@codesourcery.com>
198 * po/Make-in (pdf, ps): New dummy targets.
200 2006-06-06 Paul Brook <paul@codesourcery.com>
202 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
204 (neon_opcodes): Add conditional execution specifiers.
205 (thumb_opcodes): Ditto.
206 (thumb32_opcodes): Ditto.
207 (arm_conditional): Change 0xe to "al" and add "" to end.
208 (ifthen_state, ifthen_next_state, ifthen_address): New.
209 (IFTHEN_COND): Define.
210 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
211 (print_insn_arm): Change %c to use new values of arm_conditional.
212 (print_insn_thumb16): Print thumb conditions. Add %I.
213 (print_insn_thumb32): Print thumb conditions.
214 (find_ifthen_state): New function.
215 (print_insn): Track IT block state.
217 2006-06-06 Ben Elliston <bje@au.ibm.com>
218 Anton Blanchard <anton@samba.org>
219 Peter Bergner <bergner@vnet.ibm.com>
221 * ppc-dis.c (powerpc_dialect): Handle power6 option.
222 (print_ppc_disassembler_options): Mention power6.
224 2006-06-06 Thiemo Seufer <ths@mips.com>
225 Chao-ying Fu <fu@mips.com>
227 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
228 * mips-opc.c: Add DSP64 instructions.
230 2006-06-06 Alan Modra <amodra@bigpond.net.au>
232 * m68hc11-dis.c (print_insn): Warning fix.
234 2006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
236 * po/Make-in (top_builddir): Define.
238 2006-06-05 Alan Modra <amodra@bigpond.net.au>
240 * Makefile.am: Run "make dep-am".
241 * Makefile.in: Regenerate.
242 * config.in: Regenerate.
244 2006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
246 * Makefile.am (INCLUDES): Use @INCINTL@.
247 * acinclude.m4: Include new gettext macros.
248 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
249 Remove local code for po/Makefile.
250 * Makefile.in, aclocal.m4, configure: Regenerated.
252 2006-05-30 Nick Clifton <nickc@redhat.com>
254 * po/es.po: Updated Spanish translation.
256 2006-05-25 Richard Sandiford <richard@codesourcery.com>
258 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
259 and fmovem entries. Put register list entries before immediate
260 mask entries. Use "l" rather than "L" in the fmovem entries.
261 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
263 (m68k_scan_mask): New function, split out from...
264 (print_insn_m68k): ...here. If no architecture has been set,
265 first try printing an m680x0 instruction, then try a Coldfire one.
267 2006-05-24 Nick Clifton <nickc@redhat.com>
269 * po/ga.po: Updated Irish translation.
271 2006-05-22 Nick Clifton <nickc@redhat.com>
273 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
275 2006-05-22 Nick Clifton <nickc@redhat.com>
277 * po/nl.po: Updated translation.
279 2006-05-18 Alan Modra <amodra@bigpond.net.au>
281 * avr-dis.c: Formatting fix.
283 2006-05-14 Thiemo Seufer <ths@mips.com>
285 * mips16-opc.c (I1, I32, I64): New shortcut defines.
286 (mips16_opcodes): Change membership of instructions to their
289 2006-05-09 H.J. Lu <hongjiu.lu@intel.com>
291 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
293 2006-05-05 Julian Brown <julian@codesourcery.com>
295 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
298 2006-05-05 Thiemo Seufer <ths@mips.com>
299 David Ung <davidu@mips.com>
301 * mips-opc.c: Add macro for cache instruction.
303 2006-05-04 Thiemo Seufer <ths@mips.com>
304 Nigel Stephens <nigel@mips.com>
305 David Ung <davidu@mips.com>
307 * mips-dis.c (mips_arch_choices): Add smartmips instruction
308 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
309 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
311 * mips-opc.c: fix random typos in comments.
312 (INSN_SMARTMIPS): New defines.
313 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
314 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
315 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
316 FP_S and FP_D flags to denote single and double register
317 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
318 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
319 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
320 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
322 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
324 2006-05-03 Thiemo Seufer <ths@mips.com>
326 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
328 2006-05-02 Thiemo Seufer <ths@mips.com>
329 Nigel Stephens <nigel@mips.com>
330 David Ung <davidu@mips.com>
332 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
333 (print_mips16_insn_arg): Force mips16 to odd addresses.
335 2006-04-30 Thiemo Seufer <ths@mips.com>
336 David Ung <davidu@mips.com>
338 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
340 * mips-dis.c (print_insn_args): Adds udi argument handling.
342 2006-04-28 James E Wilson <wilson@specifix.com>
344 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
347 2006-04-28 Thiemo Seufer <ths@mips.com>
348 David Ung <davidu@mips.com>
349 Nigel Stephens <nigel@mips.com>
351 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
354 2006-04-28 Thiemo Seufer <ths@mips.com>
355 Nigel Stephens <nigel@mips.com>
356 David Ung <davidu@mips.com>
358 * mips-dis.c (print_insn_args): Add mips_opcode argument.
359 (print_insn_mips): Adjust print_insn_args call.
361 2006-04-28 Thiemo Seufer <ths@mips.com>
362 Nigel Stephens <nigel@mips.com>
364 * mips-dis.c (print_insn_args): Print $fcc only for FP
365 instructions, use $cc elsewise.
367 2006-04-28 Thiemo Seufer <ths@mips.com>
368 Nigel Stephens <nigel@mips.com>
370 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
371 Map MIPS16 registers to O32 names.
372 (print_mips16_insn_arg): Use mips16_reg_names.
374 2006-04-26 Julian Brown <julian@codesourcery.com>
376 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
379 2006-04-26 Nathan Sidwell <nathan@codesourcery.com>
380 Julian Brown <julian@codesourcery.com>
382 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
383 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
384 Add unified load/store instruction names.
385 (neon_opcode_table): New.
386 (arm_opcodes): Expand meaning of %<bitfield>['`?].
387 (arm_decode_bitfield): New.
388 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
389 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
390 (print_insn_neon): New.
391 (print_insn_arm): Adjust print_insn_coprocessor call. Call
392 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
393 (print_insn_thumb32): Likewise.
395 2006-04-19 Alan Modra <amodra@bigpond.net.au>
397 * Makefile.am: Run "make dep-am".
398 * Makefile.in: Regenerate.
400 2006-04-19 Alan Modra <amodra@bigpond.net.au>
402 * avr-dis.c (avr_operand): Warning fix.
404 * configure: Regenerate.
406 2006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
408 * po/POTFILES.in: Regenerated.
410 2006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
413 * avr-dis.c (avr_operand): Arrange for a comment to appear before
414 the symolic form of an address, so that the output of objdump -d
417 2006-04-10 DJ Delorie <dj@redhat.com>
419 * m32c-asm.c: Regenerate.
421 2006-04-06 Carlos O'Donell <carlos@codesourcery.com>
423 * Makefile.am: Add install-html target.
424 * Makefile.in: Regenerate.
426 2006-04-06 Nick Clifton <nickc@redhat.com>
428 * po/vi/po: Updated Vietnamese translation.
430 2006-03-31 Paul Koning <ni1d@arrl.net>
432 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
434 2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
436 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
437 logic to identify halfword shifts.
439 2006-03-16 Paul Brook <paul@codesourcery.com>
441 * arm-dis.c (arm_opcodes): Rename swi to svc.
442 (thumb_opcodes): Ditto.
444 2006-03-13 DJ Delorie <dj@redhat.com>
446 * m32c-asm.c: Regenerate.
447 * m32c-desc.c: Likewise.
448 * m32c-desc.h: Likewise.
449 * m32c-dis.c: Likewise.
450 * m32c-ibld.c: Likewise.
451 * m32c-opc.c: Likewise.
452 * m32c-opc.h: Likewise.
454 2006-03-10 DJ Delorie <dj@redhat.com>
456 * m32c-desc.c: Regenerate with mul.l, mulu.l.
457 * m32c-opc.c: Likewise.
458 * m32c-opc.h: Likewise.
461 2006-03-09 Nick Clifton <nickc@redhat.com>
463 * po/sv.po: Updated Swedish translation.
465 2006-03-07 H.J. Lu <hongjiu.lu@intel.com>
468 * i386-dis.c (REP_Fixup): New function.
469 (AL): Remove duplicate.
474 (indirDXr): Likewise.
477 (dis386): Updated entries of ins, outs, movs, lods and stos.
479 2006-03-05 Nick Clifton <nickc@redhat.com>
481 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
482 signed 32-bit value into an unsigned 32-bit field when the host is
484 * fr30-ibld.c: Regenerate.
485 * frv-ibld.c: Regenerate.
486 * ip2k-ibld.c: Regenerate.
487 * iq2000-asm.c: Regenerate.
488 * iq2000-ibld.c: Regenerate.
489 * m32c-ibld.c: Regenerate.
490 * m32r-ibld.c: Regenerate.
491 * openrisc-ibld.c: Regenerate.
492 * xc16x-ibld.c: Regenerate.
493 * xstormy16-ibld.c: Regenerate.
495 2006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
497 * xc16x-asm.c: Regenerate.
498 * xc16x-dis.c: Regenerate.
500 2006-02-27 Carlos O'Donell <carlos@codesourcery.com>
502 * po/Make-in: Add html target.
504 2006-02-27 H.J. Lu <hongjiu.lu@intel.com>
506 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
507 Intel Merom New Instructions.
508 (THREE_BYTE_0): Likewise.
509 (THREE_BYTE_1): Likewise.
510 (three_byte_table): Likewise.
511 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
512 THREE_BYTE_1 for entry 0x3a.
513 (twobyte_has_modrm): Updated.
514 (twobyte_uses_SSE_prefix): Likewise.
515 (print_insn): Handle 3-byte opcodes used by Intel Merom New
518 2006-02-24 David S. Miller <davem@sunset.davemloft.net>
520 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
521 (v9_hpriv_reg_names): New table.
522 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
523 New cases '$' and '%' for read/write hyperprivileged register.
524 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
525 window handling and rdhpr/wrhpr instructions.
527 2006-02-24 DJ Delorie <dj@redhat.com>
529 * m32c-desc.c: Regenerate with linker relaxation attributes.
530 * m32c-desc.h: Likewise.
531 * m32c-dis.c: Likewise.
532 * m32c-opc.c: Likewise.
534 2006-02-24 Paul Brook <paul@codesourcery.com>
536 * arm-dis.c (arm_opcodes): Add V7 instructions.
537 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
538 (print_arm_address): New function.
539 (print_insn_arm): Use it. Add 'P' and 'U' cases.
540 (psr_name): New function.
541 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
543 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
545 * ia64-opc-i.c (bXc): New.
547 (OpX2TaTbYaXcC): Likewise.
550 (ia64_opcodes_i): Add instructions for tf.
552 * ia64-opc.h (IMMU5b): New.
554 * ia64-asmtab.c: Regenerated.
556 2006-02-23 H.J. Lu <hongjiu.lu@intel.com>
558 * ia64-gen.c: Update copyright years.
559 * ia64-opc-b.c: Likewise.
561 2006-02-22 H.J. Lu <hongjiu.lu@intel.com>
563 * ia64-gen.c (lookup_regindex): Handle ".vm".
564 (print_dependency_table): Handle '\"'.
566 * ia64-ic.tbl: Updated from SDM 2.2.
567 * ia64-raw.tbl: Likewise.
568 * ia64-waw.tbl: Likewise.
569 * ia64-asmtab.c: Regenerated.
571 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
573 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
574 Anil Paranjape <anilp1@kpitcummins.com>
575 Shilin Shakti <shilins@kpitcummins.com>
577 * xc16x-desc.h: New file
578 * xc16x-desc.c: New file
579 * xc16x-opc.h: New file
580 * xc16x-opc.c: New file
581 * xc16x-ibld.c: New file
582 * xc16x-asm.c: New file
583 * xc16x-dis.c: New file
584 * Makefile.am: Entries for xc16x
585 * Makefile.in: Regenerate
586 * cofigure.in: Add xc16x target information.
587 * configure: Regenerate.
588 * disassemble.c: Add xc16x target information.
590 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
592 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
595 2006-02-11 H.J. Lu <hongjiu.lu@intel.com>
597 * i386-dis.c ('Z'): Add a new macro.
598 (dis386_twobyte): Use "movZ" for control register moves.
600 2006-02-10 Nick Clifton <nickc@redhat.com>
602 * iq2000-asm.c: Regenerate.
604 2006-02-07 Nathan Sidwell <nathan@codesourcery.com>
606 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
608 2006-01-26 David Ung <davidu@mips.com>
610 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
611 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
612 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
613 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
614 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
616 2006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
618 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
619 ld_d_r, pref_xd_cb): Use signed char to hold data to be
621 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
622 buffer overflows when disassembling instructions like
624 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
625 operand, if the offset is negative.
627 2006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
629 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
630 unsigned char to hold data to be disassembled.
632 2006-01-17 Andreas Schwab <schwab@suse.de>
635 * disassemble.c (disassemble_init_for_target): Set
636 disassembler_needs_relocs for bfd_arch_arm.
638 2006-01-16 Paul Brook <paul@codesourcery.com>
640 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
641 f?add?, and f?sub? instructions.
643 2006-01-16 Nick Clifton <nickc@redhat.com>
645 * po/zh_CN.po: New Chinese (simplified) translation.
646 * configure.in (ALL_LINGUAS): Add "zh_CH".
647 * configure: Regenerate.
649 2006-01-05 Paul Brook <paul@codesourcery.com>
651 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
653 2006-01-06 DJ Delorie <dj@redhat.com>
655 * m32c-desc.c: Regenerate.
656 * m32c-opc.c: Regenerate.
657 * m32c-opc.h: Regenerate.
659 2006-01-03 DJ Delorie <dj@redhat.com>
661 * cgen-ibld.in (extract_normal): Avoid memory range errors.
662 * m32c-ibld.c: Regenerated.
664 For older changes see ChangeLog-2005
670 version-control: never