1 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
3 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
4 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
5 * aarch64-asm-2.c: Regenerate.
6 * aarch64-dis-2.c: Regenerate.
7 * aarch64-opc-2.c: Regenerate.
9 2016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
11 * aarch64-tbl.h (QL_X1NIL): New.
12 (arch64_opcode_table): Add ldraa, ldrab.
13 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
14 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
15 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
16 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
17 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
18 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
19 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
20 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
21 (aarch64_print_operand): Likewise.
22 * aarch64-asm-2.c: Regenerate.
23 * aarch64-dis-2.c: Regenerate.
24 * aarch64-opc-2.c: Regenerate.
26 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
28 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
29 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
30 * aarch64-asm-2.c: Regenerate.
31 * aarch64-dis-2.c: Regenerate.
32 * aarch64-opc-2.c: Regenerate.
34 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
36 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
37 (AARCH64_OPERANDS): Add Rm_SP.
38 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
39 * aarch64-asm-2.c: Regenerate.
40 * aarch64-dis-2.c: Regenerate.
41 * aarch64-opc-2.c: Regenerate.
43 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
45 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
46 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
48 * aarch64-asm-2.c: Regenerate.
49 * aarch64-dis-2.c: Regenerate.
50 * aarch64-opc-2.c: Regenerate.
52 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
54 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
55 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
56 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
57 (aarch64_sys_reg_supported_p): Add feature test for new registers.
59 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
61 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
62 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
63 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
65 * aarch64-asm-2.c: Regenerate.
66 * aarch64-dis-2.c: Regenerate.
68 2016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
70 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
72 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
75 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
76 * i386-dis.c (EdqwS): Removed.
77 (dqw_swap_mode): Likewise.
78 (intel_operand_size): Don't check dqw_swap_mode.
79 (OP_E_register): Likewise.
80 (OP_E_memory): Likewise.
83 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
84 * i386-tbl.h: Regerated.
86 2016-11-09 H.J. Lu <hongjiu.lu@intel.com>
88 * i386-opc.tbl: Merge AVX512F vmovq.
89 * i386-tbl.h: Regerated.
91 2016-11-08 H.J. Lu <hongjiu.lu@intel.com>
94 * i386-dis.c (THREE_BYTE_0F7A): Removed.
95 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
96 (three_byte_table): Remove THREE_BYTE_0F7A.
98 2016-11-07 H.J. Lu <hongjiu.lu@intel.com>
101 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
102 (FGRPd9_4): Replace 1 with 2.
103 (FGRPd9_5): Replace 2 with 3.
104 (FGRPd9_6): Replace 3 with 4.
105 (FGRPd9_7): Replace 4 with 5.
106 (FGRPda_5): Replace 5 with 6.
107 (FGRPdb_4): Replace 6 with 7.
108 (FGRPde_3): Replace 7 with 8.
109 (FGRPdf_4): Replace 8 with 9.
110 (fgrps): Add an entry for Bad_Opcode.
112 2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
114 * arc-opc.c (arc_flag_operands): Add F_DI14.
115 (arc_flag_classes): Add C_DI14.
116 * arc-nps400-tbl.h: Add new exc instructions.
118 2016-11-03 Graham Markall <graham.markall@embecosm.com>
120 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
122 * arc-nps-400-tbl.h: Add dcmac instruction.
123 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
124 (insert_nps_rbdouble_64): Added.
125 (extract_nps_rbdouble_64): Added.
126 (insert_nps_proto_size): Added.
127 (extract_nps_proto_size): Added.
129 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
131 * arc-dis.c (struct arc_operand_iterator): Remove all fields
132 relating to long instruction processing, add new limm field.
133 (OPCODE): Rename to...
134 (OPCODE_32BIT_INSN): ...this.
136 (skip_this_opcode): Handle different instruction lengths, update
138 (special_flag_p): Update parameter type.
139 (find_format_from_table): Update for more instruction lengths.
140 (find_format_long_instructions): Delete.
141 (find_format): Update for more instruction lengths.
142 (arc_insn_length): Likewise.
143 (extract_operand_value): Update for more instruction lengths.
144 (operand_iterator_next): Remove code relating to long
146 (arc_opcode_to_insn_type): New function.
147 (print_insn_arc):Update for more instructions lengths.
148 * arc-ext.c (extInstruction_t): Change argument type.
149 * arc-ext.h (extInstruction_t): Change argument type.
150 * arc-fxi.h: Change type unsigned to unsigned long long
151 extensively throughout.
152 * arc-nps400-tbl.h: Add long instructions taken from
153 arc_long_opcodes table in arc-opc.c.
154 * arc-opc.c: Update parameter types on insert/extract handlers.
155 (arc_long_opcodes): Delete.
156 (arc_num_long_opcodes): Delete.
157 (arc_opcode_len): Update for more instruction lengths.
159 2016-11-03 Graham Markall <graham.markall@embecosm.com>
161 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
163 2016-11-03 Graham Markall <graham.markall@embecosm.com>
165 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
167 (find_format_long_instructions): Likewise.
168 * arc-opc.c (arc_opcode_len): New function.
170 2016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
172 * arc-nps400-tbl.h: Fix some instruction masks.
174 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
176 * i386-dis.c (REG_82): Removed.
177 (X86_64_82_REG_0): Likewise.
178 (X86_64_82_REG_1): Likewise.
179 (X86_64_82_REG_2): Likewise.
180 (X86_64_82_REG_3): Likewise.
181 (X86_64_82_REG_4): Likewise.
182 (X86_64_82_REG_5): Likewise.
183 (X86_64_82_REG_6): Likewise.
184 (X86_64_82_REG_7): Likewise.
186 (dis386): Use X86_64_82 instead of REG_82.
187 (reg_table): Remove REG_82.
188 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
189 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
190 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
193 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
196 * i386-dis.c (REG_82): New.
197 (X86_64_82_REG_0): Likewise.
198 (X86_64_82_REG_1): Likewise.
199 (X86_64_82_REG_2): Likewise.
200 (X86_64_82_REG_3): Likewise.
201 (X86_64_82_REG_4): Likewise.
202 (X86_64_82_REG_5): Likewise.
203 (X86_64_82_REG_6): Likewise.
204 (X86_64_82_REG_7): Likewise.
205 (dis386): Use REG_82.
206 (reg_table): Add REG_82.
207 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
208 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
209 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
211 2016-11-03 H.J. Lu <hongjiu.lu@intel.com>
213 * i386-dis.c (REG_82): Renamed to ...
216 (reg_table): Likewise.
218 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
220 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
221 * i386-dis-evex.h (evex_table): Updated.
222 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
223 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
224 (cpu_flags): Add CpuAVX512_4VNNIW.
225 * i386-opc.h (enum): (AVX512_4VNNIW): New.
226 (i386_cpu_flags): Add cpuavx512_4vnniw.
227 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
228 * i386-init.h: Regenerate.
231 2016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
233 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
234 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
235 * i386-dis-evex.h (evex_table): Updated.
236 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
237 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
238 (cpu_flags): Add CpuAVX512_4FMAPS.
239 (opcode_modifiers): Add ImplicitQuadGroup modifier.
240 * i386-opc.h (AVX512_4FMAP): New.
241 (i386_cpu_flags): Add cpuavx512_4fmaps.
242 (ImplicitQuadGroup): New.
243 (i386_opcode_modifier): Add implicitquadgroup.
244 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
245 * i386-init.h: Regenerate.
248 2016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
249 Andrew Waterman <andrew@sifive.com>
251 Add support for RISC-V architecture.
252 * configure.ac: Add entry for bfd_riscv_arch.
253 * configure: Regenerate.
254 * disassemble.c (disassembler): Add support for riscv.
255 (disassembler_usage): Likewise.
256 * riscv-dis.c: New file.
257 * riscv-opc.c: New file.
259 2016-10-21 H.J. Lu <hongjiu.lu@intel.com>
261 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
262 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
263 (rm_table): Update the RM_0FAE_REG_7 entry.
264 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
265 (cpu_flags): Remove CpuPCOMMIT.
266 * i386-opc.h (CpuPCOMMIT): Removed.
267 (i386_cpu_flags): Remove cpupcommit.
268 * i386-opc.tbl: Remove pcommit.
269 * i386-init.h: Regenerated.
270 * i386-tbl.h: Likewise.
272 2016-10-20 H.J. Lu <hongjiu.lu@intel.com>
275 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
276 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
277 32-bit mode. Don't check vex.register_specifier in 32-bit
279 (OP_VEX): Check for invalid mask registers.
281 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
284 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
287 2016-10-18 H.J. Lu <hongjiu.lu@intel.com>
290 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
292 2016-10-18 Maciej W. Rozycki <macro@imgtec.com>
294 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
295 local variable to `index_regno'.
297 2016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
299 * arc-tbl.h: Removed any "inv.+" instructions from the table.
301 2016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
303 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
306 2016-10-11 Jiong Wang <jiong.wang@arm.com>
309 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
311 2016-10-07 Jiong Wang <jiong.wang@arm.com>
314 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
317 2016-10-07 Alan Modra <amodra@gmail.com>
319 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
321 2016-10-06 Alan Modra <amodra@gmail.com>
323 * aarch64-opc.c: Spell fall through comments consistently.
324 * i386-dis.c: Likewise.
325 * aarch64-dis.c: Add missing fall through comments.
326 * aarch64-opc.c: Likewise.
327 * arc-dis.c: Likewise.
328 * arm-dis.c: Likewise.
329 * i386-dis.c: Likewise.
330 * m68k-dis.c: Likewise.
331 * mep-asm.c: Likewise.
332 * ns32k-dis.c: Likewise.
333 * sh-dis.c: Likewise.
334 * tic4x-dis.c: Likewise.
335 * tic6x-dis.c: Likewise.
336 * vax-dis.c: Likewise.
338 2016-10-06 Alan Modra <amodra@gmail.com>
340 * arc-ext.c (create_map): Add missing break.
341 * msp430-decode.opc (encode_as): Likewise.
342 * msp430-decode.c: Regenerate.
344 2016-10-06 Alan Modra <amodra@gmail.com>
346 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
347 * crx-dis.c (print_insn_crx): Likewise.
349 2016-09-30 H.J. Lu <hongjiu.lu@intel.com>
352 * i386-dis.c (putop): Don't assign alt twice.
354 2016-09-29 Jiong Wang <jiong.wang@arm.com>
357 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
359 2016-09-29 Alan Modra <amodra@gmail.com>
361 * ppc-opc.c (L): Make compulsory.
362 (LOPT): New, optional form of L.
363 (HTM_R): Define as LOPT.
365 (L32OPT): New, optional for 32-bit L.
366 (L2OPT): New, 2-bit L for dcbf.
369 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
370 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
372 <tlbiel, tlbie>: Use LOPT.
373 <wclr, wclrall>: Use L2.
375 2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
377 * Makefile.in: Regenerate.
378 * configure: Likewise.
380 2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
382 * arc-ext-tbl.h (EXTINSN2OPF): Define.
383 (EXTINSN2OP): Use EXTINSN2OPF.
384 (bspeekm, bspop, modapp): New extension instructions.
385 * arc-opc.c (F_DNZ_ND): Define.
390 * arc-tbl.h (dbnz): New instruction.
391 (prealloc): Allow it for ARC EM.
394 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
396 * aarch64-opc.c (print_immediate_offset_address): Print spaces
397 after commas in addresses.
398 (aarch64_print_operand): Likewise.
400 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
402 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
403 rather than "should be" or "expected to be" in error messages.
405 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
407 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
408 (print_mnemonic_name): ...here.
409 (print_comment): New function.
410 (print_aarch64_insn): Call it.
411 * aarch64-opc.c (aarch64_conds): Add SVE names.
412 (aarch64_print_operand): Print alternative condition names in
415 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
417 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
418 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
419 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
420 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
421 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
422 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
423 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
424 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
425 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
426 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
427 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
428 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
429 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
430 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
431 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
432 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
433 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
434 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
435 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
436 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
437 (OP_SVE_XWU, OP_SVE_XXU): New macros.
438 (aarch64_feature_sve): New variable.
440 (_SVE_INSN): Likewise.
441 (aarch64_opcode_table): Add SVE instructions.
442 * aarch64-opc.h (extract_fields): Declare.
443 * aarch64-opc-2.c: Regenerate.
444 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
445 * aarch64-asm-2.c: Regenerate.
446 * aarch64-dis.c (extract_fields): Make global.
447 (do_misc_decoding): Handle the new SVE aarch64_ops.
448 * aarch64-dis-2.c: Regenerate.
450 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
452 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
453 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
455 * aarch64-opc.c (fields): Add corresponding entries.
456 * aarch64-asm.c (aarch64_get_variant): New function.
457 (aarch64_encode_variant_using_iclass): Likewise.
458 (aarch64_opcode_encode): Call it.
459 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
460 (aarch64_opcode_decode): Call it.
462 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
464 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
465 and FP register operands.
466 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
467 (FLD_SVE_Vn): New aarch64_field_kinds.
468 * aarch64-opc.c (fields): Add corresponding entries.
469 (aarch64_print_operand): Handle the new SVE core and FP register
471 * aarch64-opc-2.c: Regenerate.
472 * aarch64-asm-2.c: Likewise.
473 * aarch64-dis-2.c: Likewise.
475 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
477 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
479 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
480 * aarch64-opc.c (fields): Add corresponding entry.
481 (operand_general_constraint_met_p): Handle the new SVE FP immediate
483 (aarch64_print_operand): Likewise.
484 * aarch64-opc-2.c: Regenerate.
485 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
486 (ins_sve_float_zero_one): New inserters.
487 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
488 (aarch64_ins_sve_float_half_two): Likewise.
489 (aarch64_ins_sve_float_zero_one): Likewise.
490 * aarch64-asm-2.c: Regenerate.
491 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
492 (ext_sve_float_zero_one): New extractors.
493 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
494 (aarch64_ext_sve_float_half_two): Likewise.
495 (aarch64_ext_sve_float_zero_one): Likewise.
496 * aarch64-dis-2.c: Regenerate.
498 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
500 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
501 integer immediate operands.
502 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
503 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
504 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
505 * aarch64-opc.c (fields): Add corresponding entries.
506 (operand_general_constraint_met_p): Handle the new SVE integer
508 (aarch64_print_operand): Likewise.
509 (aarch64_sve_dupm_mov_immediate_p): New function.
510 * aarch64-opc-2.c: Regenerate.
511 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
512 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
513 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
514 (aarch64_ins_limm): ...here.
515 (aarch64_ins_inv_limm): New function.
516 (aarch64_ins_sve_aimm): Likewise.
517 (aarch64_ins_sve_asimm): Likewise.
518 (aarch64_ins_sve_limm_mov): Likewise.
519 (aarch64_ins_sve_shlimm): Likewise.
520 (aarch64_ins_sve_shrimm): Likewise.
521 * aarch64-asm-2.c: Regenerate.
522 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
523 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
524 * aarch64-dis.c (decode_limm): New function, split out from...
525 (aarch64_ext_limm): ...here.
526 (aarch64_ext_inv_limm): New function.
527 (decode_sve_aimm): Likewise.
528 (aarch64_ext_sve_aimm): Likewise.
529 (aarch64_ext_sve_asimm): Likewise.
530 (aarch64_ext_sve_limm_mov): Likewise.
531 (aarch64_top_bit): Likewise.
532 (aarch64_ext_sve_shlimm): Likewise.
533 (aarch64_ext_sve_shrimm): Likewise.
534 * aarch64-dis-2.c: Regenerate.
536 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
538 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
540 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
541 the AARCH64_MOD_MUL_VL entry.
542 (value_aligned_p): Cope with non-power-of-two alignments.
543 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
544 (print_immediate_offset_address): Likewise.
545 (aarch64_print_operand): Likewise.
546 * aarch64-opc-2.c: Regenerate.
547 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
548 (ins_sve_addr_ri_s9xvl): New inserters.
549 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
550 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
551 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
552 * aarch64-asm-2.c: Regenerate.
553 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
554 (ext_sve_addr_ri_s9xvl): New extractors.
555 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
556 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
557 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
558 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
559 * aarch64-dis-2.c: Regenerate.
561 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
563 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
565 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
566 (FLD_SVE_xs_22): New aarch64_field_kinds.
567 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
568 (get_operand_specific_data): New function.
569 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
570 FLD_SVE_xs_14 and FLD_SVE_xs_22.
571 (operand_general_constraint_met_p): Handle the new SVE address
573 (sve_reg): New array.
574 (get_addr_sve_reg_name): New function.
575 (aarch64_print_operand): Handle the new SVE address operands.
576 * aarch64-opc-2.c: Regenerate.
577 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
578 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
579 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
580 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
581 (aarch64_ins_sve_addr_rr_lsl): Likewise.
582 (aarch64_ins_sve_addr_rz_xtw): Likewise.
583 (aarch64_ins_sve_addr_zi_u5): Likewise.
584 (aarch64_ins_sve_addr_zz): Likewise.
585 (aarch64_ins_sve_addr_zz_lsl): Likewise.
586 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
587 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
588 * aarch64-asm-2.c: Regenerate.
589 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
590 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
591 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
592 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
593 (aarch64_ext_sve_addr_ri_u6): Likewise.
594 (aarch64_ext_sve_addr_rr_lsl): Likewise.
595 (aarch64_ext_sve_addr_rz_xtw): Likewise.
596 (aarch64_ext_sve_addr_zi_u5): Likewise.
597 (aarch64_ext_sve_addr_zz): Likewise.
598 (aarch64_ext_sve_addr_zz_lsl): Likewise.
599 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
600 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
601 * aarch64-dis-2.c: Regenerate.
603 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
605 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
606 AARCH64_OPND_SVE_PATTERN_SCALED.
607 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
608 * aarch64-opc.c (fields): Add a corresponding entry.
609 (set_multiplier_out_of_range_error): New function.
610 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
611 (operand_general_constraint_met_p): Handle
612 AARCH64_OPND_SVE_PATTERN_SCALED.
613 (print_register_offset_address): Use PRIi64 to print the
615 (aarch64_print_operand): Likewise. Handle
616 AARCH64_OPND_SVE_PATTERN_SCALED.
617 * aarch64-opc-2.c: Regenerate.
618 * aarch64-asm.h (ins_sve_scale): New inserter.
619 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis.h (ext_sve_scale): New inserter.
622 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
623 * aarch64-dis-2.c: Regenerate.
625 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
627 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
628 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
629 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
630 (FLD_SVE_prfop): Likewise.
631 * aarch64-opc.c: Include libiberty.h.
632 (aarch64_sve_pattern_array): New variable.
633 (aarch64_sve_prfop_array): Likewise.
634 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
635 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
636 AARCH64_OPND_SVE_PRFOP.
637 * aarch64-asm-2.c: Regenerate.
638 * aarch64-dis-2.c: Likewise.
639 * aarch64-opc-2.c: Likewise.
641 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
643 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
644 AARCH64_OPND_QLF_P_[ZM].
645 (aarch64_print_operand): Print /z and /m where appropriate.
647 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
649 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
650 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
651 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
652 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
653 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
654 * aarch64-opc.c (fields): Add corresponding entries here.
655 (operand_general_constraint_met_p): Check that SVE register lists
656 have the correct length. Check the ranges of SVE index registers.
657 Check for cases where p8-p15 are used in 3-bit predicate fields.
658 (aarch64_print_operand): Handle the new SVE operands.
659 * aarch64-opc-2.c: Regenerate.
660 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
661 * aarch64-asm.c (aarch64_ins_sve_index): New function.
662 (aarch64_ins_sve_reglist): Likewise.
663 * aarch64-asm-2.c: Regenerate.
664 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
665 * aarch64-dis.c (aarch64_ext_sve_index): New function.
666 (aarch64_ext_sve_reglist): Likewise.
667 * aarch64-dis-2.c: Regenerate.
669 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
671 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
672 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
673 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
674 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
677 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
679 * aarch64-opc.c (get_offset_int_reg_name): New function.
680 (print_immediate_offset_address): Likewise.
681 (print_register_offset_address): Take the base and offset
682 registers as parameters.
683 (aarch64_print_operand): Update caller accordingly. Use
684 print_immediate_offset_address.
686 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
688 * aarch64-opc.c (BANK): New macro.
689 (R32, R64): Take a register number as argument
692 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
694 * aarch64-opc.c (print_register_list): Add a prefix parameter.
695 (aarch64_print_operand): Update accordingly.
697 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
699 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
701 * aarch64-asm.h (ins_fpimm): New inserter.
702 * aarch64-asm.c (aarch64_ins_fpimm): New function.
703 * aarch64-asm-2.c: Regenerate.
704 * aarch64-dis.h (ext_fpimm): New extractor.
705 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
706 (aarch64_ext_fpimm): New function.
707 * aarch64-dis-2.c: Regenerate.
709 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
711 * aarch64-asm.c: Include libiberty.h.
712 (insert_fields): New function.
713 (aarch64_ins_imm): Use it.
714 * aarch64-dis.c (extract_fields): New function.
715 (aarch64_ext_imm): Use it.
717 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
719 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
720 with an esize parameter.
721 (operand_general_constraint_met_p): Update accordingly.
722 Fix misindented code.
723 * aarch64-asm.c (aarch64_ins_limm): Update call to
724 aarch64_logical_immediate_p.
726 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
728 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
730 2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
732 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
734 2016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
736 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
738 2016-09-14 Peter Bergner <bergner@vnet.ibm.com>
740 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
741 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
742 xor3>: Delete mnemonics.
743 <cp_abort>: Rename mnemonic from ...
744 <cpabort>: ...to this.
745 <setb>: Change to a X form instruction.
746 <sync>: Change to 1 operand form.
747 <copy>: Delete mnemonic.
748 <copy_first>: Rename mnemonic from ...
750 <paste, paste.>: Delete mnemonics.
751 <paste_last>: Rename mnemonic from ...
752 <paste.>: ...to this.
754 2016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
756 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
758 2016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
760 * s390-mkopc.c (main): Support alternate arch strings.
762 2016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
764 * s390-opc.txt: Fix kmctr instruction type.
766 2016-09-07 H.J. Lu <hongjiu.lu@intel.com>
768 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
769 * i386-init.h: Regenerated.
771 2016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
773 * opcodes/arc-dis.c (print_insn_arc): Changed.
775 2016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
777 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
780 2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
782 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
783 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
784 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
786 2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
788 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
789 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
790 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
791 PREFIX_MOD_3_0FAE_REG_4.
792 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
793 PREFIX_MOD_3_0FAE_REG_4.
794 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
795 (cpu_flags): Add CpuPTWRITE.
796 * i386-opc.h (CpuPTWRITE): New.
797 (i386_cpu_flags): Add cpuptwrite.
798 * i386-opc.tbl: Add ptwrite instruction.
799 * i386-init.h: Regenerated.
800 * i386-tbl.h: Likewise.
802 2016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
804 * arc-dis.h: Wrap around in extern "C".
806 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
808 * aarch64-tbl.h (V8_2_INSN): New macro.
809 (aarch64_opcode_table): Use it.
811 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
813 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
814 CORE_INSN, __FP_INSN and SIMD_INSN.
816 2016-08-23 Richard Sandiford <richard.sandiford@arm.com>
818 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
819 (aarch64_opcode_table): Update uses accordingly.
821 2016-07-25 Andrew Jenner <andrew@codesourcery.com>
822 Kwok Cheung Yeung <kcy@codesourcery.com>
825 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
826 'e_cmplwi' to 'e_cmpli' instead.
827 (OPVUPRT, OPVUPRT_MASK): Define.
828 (powerpc_opcodes): Add E200Z4 insns.
829 (vle_opcodes): Add context save/restore insns.
831 2016-07-27 Maciej W. Rozycki <macro@imgtec.com>
833 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
834 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
837 2016-07-27 Graham Markall <graham.markall@embecosm.com>
839 * arc-nps400-tbl.h: Change block comments to GNU format.
840 * arc-dis.c: Add new globals addrtypenames,
841 addrtypenames_max, and addtypeunknown.
842 (get_addrtype): New function.
843 (print_insn_arc): Print colons and address types when
845 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
846 define insert and extract functions for all address types.
847 (arc_operands): Add operands for colon and all address
849 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
850 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
851 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
852 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
853 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
854 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
856 2016-07-21 H.J. Lu <hongjiu.lu@intel.com>
858 * configure: Regenerated.
860 2016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
862 * arc-dis.c (skipclass): New structure.
863 (decodelist): New variable.
864 (is_compatible_p): New function.
865 (new_element): Likewise.
866 (skip_class_p): Likewise.
867 (find_format_from_table): Use skip_class_p function.
868 (find_format): Decode first the extension instructions.
869 (print_insn_arc): Select either ARCEM or ARCHS based on elf
871 (parse_option): New function.
872 (parse_disassembler_options): Likewise.
873 (print_arc_disassembler_options): Likewise.
874 (print_insn_arc): Use parse_disassembler_options function. Proper
875 select ARCv2 cpu variant.
876 * disassemble.c (disassembler_usage): Add ARC disassembler
879 2016-07-13 Maciej W. Rozycki <macro@imgtec.com>
881 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
882 annotation from the "nal" entry and reorder it beyond "bltzal".
884 2016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
886 * sparc-opc.c (ldtxa): New macro.
887 (sparc_opcodes): Use the macro defined above to add entries for
888 the LDTXA instructions.
889 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
892 2016-07-07 James Bowman <james.bowman@ftdichip.com>
894 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
897 2016-07-01 Jan Beulich <jbeulich@suse.com>
899 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
900 (movzb): Adjust to cover all permitted suffixes.
902 * i386-tbl.h: Re-generate.
904 2016-07-01 Jan Beulich <jbeulich@suse.com>
906 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
907 (lgdt): Remove Tbyte from non-64-bit variant.
908 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
909 xsaves64, xsavec64): Remove Disp16.
910 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
911 Remove Disp32S from non-64-bit variants. Remove Disp16 from
913 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
914 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
915 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
917 * i386-tbl.h: Re-generate.
919 2016-07-01 Jan Beulich <jbeulich@suse.com>
921 * i386-opc.tbl (xlat): Remove RepPrefixOk.
922 * i386-tbl.h: Re-generate.
924 2016-06-30 Yao Qi <yao.qi@linaro.org>
926 * arm-dis.c (print_insn): Fix typo in comment.
928 2016-06-28 Richard Sandiford <richard.sandiford@arm.com>
930 * aarch64-opc.c (operand_general_constraint_met_p): Check the
931 range of ldst_elemlist operands.
932 (print_register_list): Use PRIi64 to print the index.
933 (aarch64_print_operand): Likewise.
935 2016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
937 * mcore-opc.h: Remove sentinal.
938 * mcore-dis.c (print_insn_mcore): Adjust.
940 2016-06-23 Graham Markall <graham.markall@embecosm.com>
942 * arc-opc.c: Correct description of availability of NPS400
945 2016-06-22 Peter Bergner <bergner@vnet.ibm.com>
947 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
948 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
949 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
950 xor3>: New mnemonics.
951 <setb>: Change to a VX form instruction.
952 (insert_sh6): Add support for rldixor.
953 (extract_sh6): Likewise.
955 2016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
957 * arc-ext.h: Wrap in extern C.
959 2016-06-21 Graham Markall <graham.markall@embecosm.com>
961 * arc-dis.c (arc_insn_length): Add comment on instruction length.
962 Use same method for determining instruction length on ARC700 and
964 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
965 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
966 with the NPS400 subclass.
967 * arc-opc.c: Likewise.
969 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
971 * sparc-opc.c (rdasr): New macro.
977 (sparc_opcodes): Use the macros above to fix and expand the
978 definition of read/write instructions from/to
979 asr/privileged/hyperprivileged instructions.
980 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
981 %hva_mask_nz. Prefer softint_set and softint_clear over
982 set_softint and clear_softint.
983 (print_insn_sparc): Support %ver in Rd.
985 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
987 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
988 architecture according to the hardware capabilities they require.
990 2016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
992 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
993 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
994 bfd_mach_sparc_v9{c,d,e,v,m}.
995 * sparc-opc.c (MASK_V9C): Define.
996 (MASK_V9D): Likewise.
997 (MASK_V9E): Likewise.
998 (MASK_V9V): Likewise.
999 (MASK_V9M): Likewise.
1000 (v6): Add MASK_V9{C,D,E,V,M}.
1001 (v6notlet): Likewise.
1005 (v9andleon): Likewise.
1013 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1015 2016-06-15 Nick Clifton <nickc@redhat.com>
1017 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1018 constants to match expected behaviour.
1019 (nds32_parse_opcode): Likewise. Also for whitespace.
1021 2016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1023 * arc-opc.c (extract_rhv1): Extract value from insn.
1025 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1027 * arc-nps400-tbl.h: Add ldbit instruction.
1028 * arc-opc.c: Add flag classes required for ldbit.
1030 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1032 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1033 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1034 support the above instructions.
1036 2016-06-14 Graham Markall <graham.markall@embecosm.com>
1038 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1039 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1040 csma, cbba, zncv, and hofs.
1041 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1042 support the above instructions.
1044 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1046 * arc-nps400-tbl.h: Add andab and orab instructions.
1048 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1050 * arc-nps400-tbl.h: Add addl-like instructions.
1052 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1054 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1056 2016-06-06 Graham Markall <graham.markall@embecosm.com>
1058 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1061 2016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1063 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1065 (init_disasm): Handle new command line option "insnlength".
1066 (print_s390_disassembler_options): Mention new option in help
1068 (print_insn_s390): Use the encoded insn length when dumping
1069 unknown instructions.
1071 2016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1073 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1074 to the address and set as symbol address for LDS/ STS immediate operands.
1076 2016-06-07 Alan Modra <amodra@gmail.com>
1078 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1079 cpu for "vle" to e500.
1080 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1081 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1082 (PPCNONE): Delete, substitute throughout.
1083 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1084 except for major opcode 4 and 31.
1085 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1087 2016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1089 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1090 ARM_EXT_RAS in relevant entries.
1092 2016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1095 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1098 2016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1101 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1102 (indir_v_mode): New.
1103 Add comments for '&'.
1104 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1105 (putop): Handle '&'.
1106 (intel_operand_size): Handle indir_v_mode.
1107 (OP_E_register): Likewise.
1108 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1109 64-bit indirect call/jmp for AMD64.
1110 * i386-tbl.h: Regenerated
1112 2016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1114 * arc-dis.c (struct arc_operand_iterator): New structure.
1115 (find_format_from_table): All the old content from find_format,
1116 with some minor adjustments, and parameter renaming.
1117 (find_format_long_instructions): New function.
1118 (find_format): Rewritten.
1119 (arc_insn_length): Add LSB parameter.
1120 (extract_operand_value): New function.
1121 (operand_iterator_next): New function.
1122 (print_insn_arc): Use new functions to find opcode, and iterator
1124 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1125 (extract_nps_3bit_dst_short): New function.
1126 (insert_nps_3bit_src2_short): New function.
1127 (extract_nps_3bit_src2_short): New function.
1128 (insert_nps_bitop1_size): New function.
1129 (extract_nps_bitop1_size): New function.
1130 (insert_nps_bitop2_size): New function.
1131 (extract_nps_bitop2_size): New function.
1132 (insert_nps_bitop_mod4_msb): New function.
1133 (extract_nps_bitop_mod4_msb): New function.
1134 (insert_nps_bitop_mod4_lsb): New function.
1135 (extract_nps_bitop_mod4_lsb): New function.
1136 (insert_nps_bitop_dst_pos3_pos4): New function.
1137 (extract_nps_bitop_dst_pos3_pos4): New function.
1138 (insert_nps_bitop_ins_ext): New function.
1139 (extract_nps_bitop_ins_ext): New function.
1140 (arc_operands): Add new operands.
1141 (arc_long_opcodes): New global array.
1142 (arc_num_long_opcodes): New global.
1143 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1145 2016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1147 * nds32-asm.h: Add extern "C".
1148 * sh-opc.h: Likewise.
1150 2016-06-01 Graham Markall <graham.markall@embecosm.com>
1152 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1153 0,b,limm to the rflt instruction.
1155 2016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1157 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1160 2016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1163 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1164 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1165 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1166 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1167 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1168 * i386-init.h: Regenerated.
1170 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1173 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1174 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1175 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1176 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1177 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1178 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1179 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1180 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1181 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1182 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1183 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1184 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1185 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1186 CpuRegMask for AVX512.
1187 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1189 (set_bitfield_from_cpu_flag_init): New function.
1190 (set_bitfield): Remove const on f. Call
1191 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1192 * i386-opc.h (CpuRegMMX): New.
1193 (CpuRegXMM): Likewise.
1194 (CpuRegYMM): Likewise.
1195 (CpuRegZMM): Likewise.
1196 (CpuRegMask): Likewise.
1197 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1199 * i386-init.h: Regenerated.
1200 * i386-tbl.h: Likewise.
1202 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1205 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1206 (opcode_modifiers): Add AMD64 and Intel64.
1207 (main): Properly verify CpuMax.
1208 * i386-opc.h (CpuAMD64): Removed.
1209 (CpuIntel64): Likewise.
1210 (CpuMax): Set to CpuNo64.
1211 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1213 (Intel64): Likewise.
1214 (i386_opcode_modifier): Add amd64 and intel64.
1215 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1217 * i386-init.h: Regenerated.
1218 * i386-tbl.h: Likewise.
1220 2016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1223 * i386-gen.c (main): Fail if CpuMax is incorrect.
1224 * i386-opc.h (CpuMax): Set to CpuIntel64.
1225 * i386-tbl.h: Regenerated.
1227 2016-05-27 Nick Clifton <nickc@redhat.com>
1230 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1231 (msp430dis_opcode_unsigned): New function.
1232 (msp430dis_opcode_signed): New function.
1233 (msp430_singleoperand): Use the new opcode reading functions.
1234 Only disassenmble bytes if they were successfully read.
1235 (msp430_doubleoperand): Likewise.
1236 (msp430_branchinstr): Likewise.
1237 (msp430x_callx_instr): Likewise.
1238 (print_insn_msp430): Check that it is safe to read bytes before
1239 attempting disassembly. Use the new opcode reading functions.
1241 2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1243 * ppc-opc.c (CY): New define. Document it.
1244 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1246 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1248 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1249 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1250 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1251 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1253 * i386-init.h: Regenerated.
1255 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1258 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1259 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1260 * i386-init.h: Regenerated.
1262 2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1264 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1265 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1266 * i386-init.h: Regenerated.
1268 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1270 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1272 (print_insn_arc): Set insn_type information.
1273 * arc-opc.c (C_CC): Add F_CLASS_COND.
1274 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1275 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1276 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1277 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1278 (brne, brne_s, jeq_s, jne_s): Likewise.
1280 2016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1282 * arc-tbl.h (neg): New instruction variant.
1284 2016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1286 * arc-dis.c (find_format, find_format, get_auxreg)
1287 (print_insn_arc): Changed.
1288 * arc-ext.h (INSERT_XOP): Likewise.
1290 2016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1292 * tic54x-dis.c (sprint_mmr): Adjust.
1293 * tic54x-opc.c: Likewise.
1295 2016-05-19 Alan Modra <amodra@gmail.com>
1297 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1299 2016-05-19 Alan Modra <amodra@gmail.com>
1301 * ppc-opc.c: Formatting.
1302 (NSISIGNOPT): Define.
1303 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1305 2016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1307 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1308 replacing references to `micromips_ase' throughout.
1309 (_print_insn_mips): Don't use file-level microMIPS annotation to
1310 determine the disassembly mode with the symbol table.
1312 2016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1314 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1316 2016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1318 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1320 * mips-opc.c (D34): New macro.
1321 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1323 2016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1325 * i386-dis.c (prefix_table): Add RDPID instruction.
1326 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1327 (cpu_flags): Add RDPID bitfield.
1328 * i386-opc.h (enum): Add RDPID element.
1329 (i386_cpu_flags): Add RDPID field.
1330 * i386-opc.tbl: Add RDPID instruction.
1331 * i386-init.h: Regenerate.
1332 * i386-tbl.h: Regenerate.
1334 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1336 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1337 branch type of a symbol.
1338 (print_insn): Likewise.
1340 2016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1342 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1343 Mainline Security Extensions instructions.
1344 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1345 Extensions instructions.
1346 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1348 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1351 2016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1353 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1355 2016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1357 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1358 (arcExtMap_genOpcode): Likewise.
1359 * arc-opc.c (arg_32bit_rc): Define new variable.
1360 (arg_32bit_u6): Likewise.
1361 (arg_32bit_limm): Likewise.
1363 2016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1365 * aarch64-gen.c (VERIFIER): Define.
1366 * aarch64-opc.c (VERIFIER): Define.
1367 (verify_ldpsw): Use static linkage.
1368 * aarch64-opc.h (verify_ldpsw): Remove.
1369 * aarch64-tbl.h: Use VERIFIER for verifiers.
1371 2016-04-28 Nick Clifton <nickc@redhat.com>
1374 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1375 * aarch64-opc.c (verify_ldpsw): New function.
1376 * aarch64-opc.h (verify_ldpsw): New prototype.
1377 * aarch64-tbl.h: Add initialiser for verifier field.
1378 (LDPSW): Set verifier to verify_ldpsw.
1380 2016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1384 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1385 smaller than address size.
1387 2016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1389 * alpha-dis.c: Regenerate.
1390 * crx-dis.c: Likewise.
1391 * disassemble.c: Likewise.
1392 * epiphany-opc.c: Likewise.
1393 * fr30-opc.c: Likewise.
1394 * frv-opc.c: Likewise.
1395 * ip2k-opc.c: Likewise.
1396 * iq2000-opc.c: Likewise.
1397 * lm32-opc.c: Likewise.
1398 * lm32-opinst.c: Likewise.
1399 * m32c-opc.c: Likewise.
1400 * m32r-opc.c: Likewise.
1401 * m32r-opinst.c: Likewise.
1402 * mep-opc.c: Likewise.
1403 * mt-opc.c: Likewise.
1404 * or1k-opc.c: Likewise.
1405 * or1k-opinst.c: Likewise.
1406 * tic80-opc.c: Likewise.
1407 * xc16x-opc.c: Likewise.
1408 * xstormy16-opc.c: Likewise.
1410 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1412 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1413 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1414 calcsd, and calcxd instructions.
1415 * arc-opc.c (insert_nps_bitop_size): Delete.
1416 (extract_nps_bitop_size): Delete.
1417 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1418 (extract_nps_qcmp_m3): Define.
1419 (extract_nps_qcmp_m2): Define.
1420 (extract_nps_qcmp_m1): Define.
1421 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1422 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1423 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1424 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1425 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1428 2016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1430 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1432 2016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1434 * Makefile.in: Regenerated with automake 1.11.6.
1435 * aclocal.m4: Likewise.
1437 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1439 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1441 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1442 (extract_nps_cmem_uimm16): New function.
1443 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1445 2016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1447 * arc-dis.c (arc_insn_length): New function.
1448 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1449 (find_format): Change insnLen parameter to unsigned.
1451 2016-04-13 Nick Clifton <nickc@redhat.com>
1454 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1455 the LD.B and LD.BU instructions.
1457 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1459 * arc-dis.c (find_format): Check for extension flags.
1460 (print_flags): New function.
1461 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1463 * arc-ext.c (arcExtMap_coreRegName): Use
1464 LAST_EXTENSION_CORE_REGISTER.
1465 (arcExtMap_coreReadWrite): Likewise.
1466 (dump_ARC_extmap): Update printing.
1467 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1468 (arc_aux_regs): Add cpu field.
1469 * arc-regs.h: Add cpu field, lower case name aux registers.
1471 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1473 * arc-tbl.h: Add rtsc, sleep with no arguments.
1475 2016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1477 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1479 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1480 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1481 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1482 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1483 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1484 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1485 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1486 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1487 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1488 (arc_opcode arc_opcodes): Null terminate the array.
1489 (arc_num_opcodes): Remove.
1490 * arc-ext.h (INSERT_XOP): Define.
1491 (extInstruction_t): Likewise.
1492 (arcExtMap_instName): Delete.
1493 (arcExtMap_insn): New function.
1494 (arcExtMap_genOpcode): Likewise.
1495 * arc-ext.c (ExtInstruction): Remove.
1496 (create_map): Zero initialize instruction fields.
1497 (arcExtMap_instName): Remove.
1498 (arcExtMap_insn): New function.
1499 (dump_ARC_extmap): More info while debuging.
1500 (arcExtMap_genOpcode): New function.
1501 * arc-dis.c (find_format): New function.
1502 (print_insn_arc): Use find_format.
1503 (arc_get_disassembler): Enable dump_ARC_extmap only when
1506 2016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1508 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1509 instruction bits out.
1511 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1513 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1514 * arc-opc.c (arc_flag_operands): Add new flags.
1515 (arc_flag_classes): Add new classes.
1517 2016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1519 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1521 2016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1523 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1524 encode1, rflt, crc16, and crc32 instructions.
1525 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1526 (arc_flag_classes): Add C_NPS_R.
1527 (insert_nps_bitop_size_2b): New function.
1528 (extract_nps_bitop_size_2b): Likewise.
1529 (insert_nps_bitop_uimm8): Likewise.
1530 (extract_nps_bitop_uimm8): Likewise.
1531 (arc_operands): Add new operand entries.
1533 2016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1535 * arc-regs.h: Add a new subclass field. Add double assist
1536 accumulator register values.
1537 * arc-tbl.h: Use DPA subclass to mark the double assist
1538 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1539 * arc-opc.c (RSP): Define instead of SP.
1540 (arc_aux_regs): Add the subclass field.
1542 2016-04-05 Jiong Wang <jiong.wang@arm.com>
1544 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1546 2016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
1548 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1551 2016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1553 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1554 issues. No functional changes.
1556 2016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1558 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1559 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1560 (RTT): Remove duplicate.
1561 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1562 (PCT_CONFIG*): Remove.
1563 (D1L, D1H, D2H, D2L): Define.
1565 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1567 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
1569 2016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1571 * arc-tbl.h (invld07): Remove.
1572 * arc-ext-tbl.h: New file.
1573 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1574 * arc-opc.c (arc_opcodes): Add ext-tbl include.
1576 2016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1578 Fix -Wstack-usage warnings.
1579 * aarch64-dis.c (print_operands): Substitute size.
1580 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1582 2016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1584 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1585 to get a proper diagnostic when an invalid ASR register is used.
1587 2016-03-22 Nick Clifton <nickc@redhat.com>
1589 * configure: Regenerate.
1591 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1593 * arc-nps400-tbl.h: New file.
1594 * arc-opc.c: Add top level comment.
1595 (insert_nps_3bit_dst): New function.
1596 (extract_nps_3bit_dst): New function.
1597 (insert_nps_3bit_src2): New function.
1598 (extract_nps_3bit_src2): New function.
1599 (insert_nps_bitop_size): New function.
1600 (extract_nps_bitop_size): New function.
1601 (arc_flag_operands): Add nps400 entries.
1602 (arc_flag_classes): Add nps400 entries.
1603 (arc_operands): Add nps400 entries.
1604 (arc_opcodes): Add nps400 include.
1606 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1608 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1609 the new class enum values.
1611 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1613 * arc-dis.c (print_insn_arc): Handle nps400.
1615 2016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1617 * arc-opc.c (BASE): Delete.
1619 2016-03-18 Nick Clifton <nickc@redhat.com>
1622 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1623 of MOV insn that aliases an ORR insn.
1625 2016-03-16 Jiong Wang <jiong.wang@arm.com>
1627 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1629 2016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1631 * mcore-opc.h: Add const qualifiers.
1632 * microblaze-opc.h (struct op_code_struct): Likewise.
1633 * sh-opc.h: Likewise.
1634 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1635 (tic4x_print_op): Likewise.
1637 2016-03-02 Alan Modra <amodra@gmail.com>
1639 * or1k-desc.h: Regenerate.
1640 * fr30-ibld.c: Regenerate.
1641 * rl78-decode.c: Regenerate.
1643 2016-03-01 Nick Clifton <nickc@redhat.com>
1646 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1648 2016-02-24 Renlin Li <renlin.li@arm.com>
1650 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1651 (print_insn_coprocessor): Support fp16 instructions.
1653 2016-02-24 Renlin Li <renlin.li@arm.com>
1655 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1656 vminnm, vrint(mpna).
1658 2016-02-24 Renlin Li <renlin.li@arm.com>
1660 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1661 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1663 2016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1665 * i386-dis.c (print_insn): Parenthesize expression to prevent
1666 truncated addresses.
1669 2016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1670 Janek van Oirschot <jvanoirs@synopsys.com>
1672 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1675 2016-02-04 Nick Clifton <nickc@redhat.com>
1678 * msp430-dis.c (print_insn_msp430): Add a special case for
1679 decoding an RRC instruction with the ZC bit set in the extension
1682 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1684 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1685 * epiphany-ibld.c: Regenerate.
1686 * fr30-ibld.c: Regenerate.
1687 * frv-ibld.c: Regenerate.
1688 * ip2k-ibld.c: Regenerate.
1689 * iq2000-ibld.c: Regenerate.
1690 * lm32-ibld.c: Regenerate.
1691 * m32c-ibld.c: Regenerate.
1692 * m32r-ibld.c: Regenerate.
1693 * mep-ibld.c: Regenerate.
1694 * mt-ibld.c: Regenerate.
1695 * or1k-ibld.c: Regenerate.
1696 * xc16x-ibld.c: Regenerate.
1697 * xstormy16-ibld.c: Regenerate.
1699 2016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1701 * epiphany-dis.c: Regenerated from latest cpu files.
1703 2016-02-01 Michael McConville <mmcco@mykolab.com>
1705 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1708 2016-01-25 Renlin Li <renlin.li@arm.com>
1710 * arm-dis.c (mapping_symbol_for_insn): New function.
1711 (find_ifthen_state): Call mapping_symbol_for_insn().
1713 2016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1715 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1716 of MSR UAO immediate operand.
1718 2016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1720 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1721 instruction support.
1723 2016-01-17 Alan Modra <amodra@gmail.com>
1725 * configure: Regenerate.
1727 2016-01-14 Nick Clifton <nickc@redhat.com>
1729 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1730 instructions that can support stack pointer operations.
1731 * rl78-decode.c: Regenerate.
1732 * rl78-dis.c: Fix display of stack pointer in MOVW based
1735 2016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1737 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1738 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1739 erxtatus_el1 and erxaddr_el1.
1741 2016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1743 * arm-dis.c (arm_opcodes): Add "esb".
1744 (thumb_opcodes): Likewise.
1746 2016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1748 * ppc-opc.c <xscmpnedp>: Delete.
1749 <xvcmpnedp>: Likewise.
1750 <xvcmpnedp.>: Likewise.
1751 <xvcmpnesp>: Likewise.
1752 <xvcmpnesp.>: Likewise.
1754 2016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1757 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1760 2016-01-01 Alan Modra <amodra@gmail.com>
1762 Update year range in copyright notice of all files.
1764 For older changes see ChangeLog-2015
1766 Copyright (C) 2016 Free Software Foundation, Inc.
1768 Copying and distribution of this file, with or without modification,
1769 are permitted in any medium without royalty provided the copyright
1770 notice and this notice are preserved.
1776 version-control: never